TW201042951A - A stretchable form of single crystal silicon for high performance electronics on rubber substrates - Google Patents

A stretchable form of single crystal silicon for high performance electronics on rubber substrates Download PDF

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TW201042951A
TW201042951A TW099127004A TW99127004A TW201042951A TW 201042951 A TW201042951 A TW 201042951A TW 099127004 A TW099127004 A TW 099127004A TW 99127004 A TW99127004 A TW 99127004A TW 201042951 A TW201042951 A TW 201042951A
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semiconductor
strain
substrate
extendable
extensible
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TWI489523B (en
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John A Rogers
Dahl-Young Khang
yu-gang Sun
Etienne Menard
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Univ Illinois
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    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
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    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7781Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606Graphene
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
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    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Description

201042951 六、發明說明: 【發明所屬之技術領域】 本發明係關於用在橡膠基板卜古t 喂签败上间效能電子組件之可延伸 形式之單晶矽。 【先前技術】201042951 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a single crystal crucible in an extendable form of a performance electronic component used in a rubber substrate. [Prior Art]

自1994年-印製的全聚合物電晶體之第—次演示以來, 人們對在塑膠基板上包含可挽性積體電子裝置之一潛在的 新類別電子系統產生了巨大的興趣。[Garnik f·, Hajlaoui,R.,Ya謝,A.及⑽邮議,p , ^⑽第泌 卷,第1684-1686頁]近來,大量研究已針對發展新的用於 可撓性塑性電子裝置之導體、介電質及半導體元件之溶液 可處理材料。然而,可撓性電子裝置領域中之進步不僅由 新的溶液可處理材料的發展來驅動,而且由新裝置組件幾 何形態、高效裝置及裝置組件處理方法及可應用於塑膠基 板之咼解析度圖案化技術所驅動。預期此等材料、裝置組 態及製造方法將在迅速出現之新型可撓性積體電子裝置、 系統及電路中起到關鍵作用。 對可撓性電子裝置領域之興趣是由此技術提供之若干重 要優勢而引起。首先,塑膠基板材料之機械耐用性提供不 易知壞及/或不易受到由機械應力引起之電子效能降級的 電子農置。其次,此等基板材料之固有的可撓性允許將其 整合為許多形狀,從而提供不可能藉由脆性的習知的基於 電子裝置來^供的大量有用裝置組態。最後,溶液可 處理組件材料與塑膠基板之組合使得藉由能在大基板面積 150175.doc 201042951 上以低成本產生電子裝置之連續、高速、印製技術的製造 成為可能。 然而,呈現良好電子效能之可撓性電子裝置之設計及製 &存在若干顯著挑戰。首先,用於製造習知的基於矽之電 子裝置的已良好發展的方法與大部分塑膠材料不相容。舉 例而言,諸如單晶石夕或錯半導體之傳統的高纟質無機半導 體組件通常藉由在某些溫度(>攝氏1000度)下生長薄膜來 處理,該等溫纟顯著超過大部分塑職板的㈣或分解溫 度。另外,大部分無機半導體在允許基於溶液之處理及傳 送之適宜溶劑中本質地不可溶。其次,儘管許多非晶系 矽、有機或混合有機_無機半導體可相容地併入塑膠基板 :’且可在相對較低溫度下處王里,但是此等材料不具有能 提供具有良好電子效能之積體電子裝置之電子性質。舉例 而言,具有由此等材料製造之半導體元件的薄膜電晶體顯 示出比互補的基於單晶石夕夕駐要丄, 平Ba矽之裝置低大約三個數量級之場效 應遷移率。作為此等侷限性之結果,可撓性電子裝置目前 限於無需高效能的特定應用,諸如用於具有非發射性像素 之主動矩陣平板顯示器之開關元件中及發光二極體中。’、 在擴展塑膠基板上的積體電子裝置之電子效能能力方t 已獲得進步以將其適用性擴展至一更廣泛範圍之電子』 用。舉例而5 ’已出現若干新型壤肢蕾曰Mm ' I π i溽膜電晶體(TFT)設計 其與塑膠基板材料上之處理相交g ls _ , a 处相谷且顯不出顯著高於具有与 晶系石夕、有機或混合有機-益機丰遵_牌_灿 戌…、機牛導體兀件之薄臈電晶^ 之裝置效能特性。一類更高效能夕沉枯^ & ^ ^ 之可撓性電子裝置係基戈 150175.doc 201042951 藉^對非晶切薄膜之脈衝雷射退火而製造之多晶石夕薄膜 半ν體π件。㈣此類可撓性電子裝置提供增強之裝置電 子效此特性,但是對脈衝雷射退火之使用限制了此等裝置 裝&的谷易性及靈活性,進而顯著增加了成本。另一有希 望之新型更兩效能之可撓性電子裝置是使用諸如奈米線、 奈^、奈米微粒及奈米碳管之溶液可處理奈米級材料作 為右干宏觀電子及微電子裝置中之主動功能性組件之裝 Ο ❹ 離散單結晶奈米線或奈米帶之使用已被評估為於塑膠基 板上提供I頁不增強裝置效&特性之可印刷電子I置的一可 能之手段。Duan等人描述具有複數個作為半導體通道之可 選擇性定向之單結晶石夕奈米線或Cds奈米帶的薄膜電晶體 設計[Duan,X·, Niu,c, Sahl,v,Chen,】,parce,】Since the first demonstration of the all-polymer transistor printed in 1994, there has been a great interest in the potential new class of electronic systems that contain a programmable integrated electronic device on a plastic substrate. [Garnik f., Hajlaoui, R., Ya Xie, A. and (10) Post, p, ^(10) Dict, pp. 1684-1686] Recently, a large number of studies have been directed to the development of new flexible plastics. A solution of the conductor, dielectric and semiconductor components of the device can process the material. However, advances in the field of flexible electronic devices have not only been driven by the development of new solution-processable materials, but also by new device component geometries, high-efficiency devices and device component processing methods, and 咼 resolution patterns that can be applied to plastic substrates. Driven by technology. It is expected that these materials, device configurations and manufacturing methods will play a key role in the rapid emergence of new flexible integrated electronic devices, systems and circuits. Interest in the field of flexible electronic devices is caused by several important advantages provided by this technology. First, the mechanical durability of the plastic substrate material provides an electronic farm that is less susceptible to damage and/or less susceptible to degradation in electronic performance caused by mechanical stress. Second, the inherent flexibility of such substrate materials allows for their integration into many shapes, thereby providing a large number of useful device configurations that are not available by conventional electronic devices based on brittleness. Finally, the combination of the solution processable component material and the plastic substrate makes it possible to manufacture continuous, high speed, printing technology capable of producing electronic devices at low cost over a large substrate area of 150175.doc 201042951. However, there are several significant challenges in the design and manufacture of flexible electronic devices that exhibit good electronic performance. First, well-developed methods for fabricating conventional germanium-based electronic devices are incompatible with most plastic materials. For example, conventional high tantalum inorganic semiconductor components such as monocrystalline or erroneous semiconductors are typically processed by growing a film at certain temperatures (> 1000 degrees Celsius), which is significantly more than most plastics. (4) or decomposition temperature of the grade board. In addition, most inorganic semiconductors are substantially insoluble in suitable solvents that allow for solution based processing and delivery. Secondly, although many amorphous germanium, organic or hybrid organic-inorganic semiconductors are compatiblely incorporated into plastic substrates: 'and can be used at relatively low temperatures, these materials do not provide good electronic performance. The electronic properties of the integrated electronic device. For example, a thin film transistor having a semiconductor component fabricated from such materials exhibits a field effect mobility of about three orders of magnitude lower than a complementary single crystal based device. As a result of these limitations, flexible electronic devices are currently limited to specific applications that do not require high performance, such as in switching elements for active matrix flat panel displays having non-emissive pixels and in light emitting diodes. The electronic performance capability of integrated electronic devices on extended plastic substrates has advanced to extend its applicability to a wider range of electronic applications. For example, 5' has appeared several new type of lobe buds Mm ' I π i溽 film transistor (TFT) designed to intersect with the processing on the plastic substrate material g ls _ , a at the phase valley and is not significantly higher than And the crystal system Shi Xi, organic or mixed organic - Yi machine Feng Zun _ card _ Chan 戌 ..., machine cattle conductor pieces of thin 臈 臈 ^ ^ ^ ^ ^ ^ ^ ^ ^ A class of higher-efficiency singularity ^ & ^ ^ flexible electronic device system Ji Ge 150175.doc 201042951 by polyfluoride annealing of amorphous thin film by a pulsed laser annealing . (d) Such flexible electronic devices provide enhanced electronic characteristics of the device, but the use of pulsed laser annealing limits the flexibility and flexibility of such devices, thereby significantly increasing costs. Another promising new and more efficient flexible electronic device is to process nano-materials as right-hand macroscopic electronic and microelectronic devices using solutions such as nanowires, nanoparticles, nanoparticles and carbon nanotubes.主动 主动 主动 主动 主动 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散 离散means. Duan et al. describe a thin film transistor design with a plurality of selectively oriented single crystal nanowires or Cds nanobelts as semiconductor channels [Duan, X·, Niu, c, Sahl, v, Chen,] ,parce,]

Empedocles,S.及 Goldman,J_,Nature,第 425卷,第 274 . 278頁]。該等作者報告一據稱可與塑膠基板上之溶液處理 相容之製造過程,其中具有少於或等於15〇奈米之厚度的 單結晶石夕奈米線或CdS奈米帶被分散於溶液中,且使用流 置定向對準方法將其組裝於一基板之表面上以產生薄膜電 晶體之半導體元件。由該等作者提供之一光學顯微圖暗示 所揭示之製造過程製備了呈大體上平行取向且間隔約5〇〇 奈米至約1000奈米的多個奈米線或奈米帶之單層。儘管該 等作者報告了個別奈米線或奈米帶之相對高的本質場效應 遷移率(=119 cm2 V-1 S-1),但是總的裝置場效應遷移率近 來已被判定為比由Duan等人報告之本質場效應遷移率值小 150175.doc 201042951 ”大約兩個數量級"。[Mitzi,D.B,Kosbar,L.L·, Murmy, C.E.,Copel,M. Afzali,A” Nature,第 428頁,第 299 3〇3 頁]。此裝置場效應遷移率比習知單結晶無機薄膜電晶體 之裝置場效應遷移率低若干數量級’且可能係歸因於使用 Duan等人揭示之方法及裝置組態進行對準、緊密封裝及電 接觸離散奈米線或奈米帶中的實際挑戰。 亦已探索了將奈米晶體溶液用作多晶系無機半導體薄膜 之先驅體,以將其作為在塑膠基板上提供呈現更高裝置效 能特性之可印刷電子裝置之手段。Ridley等人揭示一溶液 處理製造方法,其中具有約2奈米尺寸之硒化鎘奈米晶體 溶液在塑膠相容溫度下被處理以提供場效應電晶體之半導 體元件。[Ridley,B.A·,Nivi,B.及 Jacobs〇n,j M, Science,第286卷,746-749 (1999)]該等作者報告一方 法,其中在硒化鎘奈米晶體溶液中的低溫晶粒生長提供包 3數百奈米晶體之早晶區域。雖然Ridley等人報告了相對 於具有有機半導體元件之比較裝置的改良之電子性質作 是藉由此等技術達成的裝置遷移率(;sl cm2 v·! 比習知 單結晶無機薄膜電晶體之裝置場效應遷移率低若干數量 級。藉由Ridley等人之裝置組態及製造方法所達成之場效 應遷移率的限制可能是由在個別奈米微粒之間建立之電接 觸產生的。詳言之,對用以穩定奈米晶體溶液及防止凝聚 之有機端基的使用可阻止在鄰近奈米微粒之間建立良好電 接觸,此種良好電接觸對於提供高裝置場效應遷移率係必 要的。 ’~ J50175.doc 201042951 儘g Duan等人及Ridley等人提供用於在塑膠基板上製造 薄膜電晶體之方法,所描述之裝置組態係包含諸如電極、 半導體及/或介電質的機械剛性裝置組件之電晶體。選用 具有良好機械性質之塑膠基板可提供能在延伸或扭曲定向 中工作的電子裝置,然而,預期此種形變會在個別剛性電 晶體襄置組件上產生機械應力。此機械應力可導致對個別 組件之損傷,例如,裂紋,且亦可降級或中斷裝置組件之 間的電接觸。 ° 料,由Duan等人、Ridley等人及其他人發展之基於塑 膠基板之電子系統是否提供對於許多重要裝置應用(包括 可撓性感測器陣列、電子紙,及可佩帶電子裝置)為必要 的機械延伸性並不明朗。雖然此等團隊展示了有能力承受 由撓曲引起之變形的電子裝置,但是此等基於塑滕基板之 ^統不可能進行可觀的延伸而無損傷、機械失效或裳置效 旎之顯者降級。因此,此等系統不可能承受由膨脹或壓縮 ◎弓丨起之變形’或承文等形覆蓋高度起伏之表面(諸如具有 大曲率半徑的彎曲表面)所要求之變形。 如上述,預期可撓性電子裝置領域中之進步會在若干重 要新技術及已有技術中起到關鍵作用。然而,可撓性電子 裝置技術之此等應用之成功極大地取決於新材料、裝置組 態及用於製造在撓曲、變形及彎曲構形中展示良好電子、 機械及光學性質的積體電子電路及裝置之商業上可行的製 造途徑之持續發展。特定言之,需要在延伸或收縮構形中 展不有用之電子及機械性質的高效能、可機械延伸的材料 150l75.doc 201042951 及裝置組態。 【發明内容】 本發明提供可延伸半導體及可延伸電子裝置、裝置植件 及電路。如本文所使用,術語"可延伸"指材料、結構、裝 置及裝置組件能承受應變而無破裂或機械失效。本發明之 可延伸半導體及電子裝置係可延伸的,且因此能至少在某 種程度上延伸及/或壓縮而無損壞、機械失效或裝置效能 之顯著降級。較佳用於某些應用的本發明之可延伸半導體 及電子電路為可撓性的(除了為可延伸的之外),且因此能 顯著伸長、撓曲’彎曲或進行沿一或多個軸之其他變形。Empedocles, S. and Goldman, J_, Nature, Vol. 425, 274. p. 278]. The authors report a manufacturing process that is said to be compatible with solution processing on a plastic substrate in which a single crystal nanowire or CdS nanowire having a thickness of less than or equal to 15 nanometers is dispersed in solution. And using a flow-oriented alignment method to assemble it on the surface of a substrate to produce a semiconductor element of a thin film transistor. An optical micrograph provided by the authors suggests that the disclosed manufacturing process produces a single layer of multiple nanowires or nanoribbons in substantially parallel orientation and spaced from about 5 nanometers to about 1000 nanometers. . Although the authors reported relatively high intrinsic field-effect mobility (=119 cm2 V-1 S-1) for individual nanowires or nanobelts, the total device field-effect mobility has recently been judged as Duan et al. reported an intrinsic field effect mobility value of 150175.doc 201042951 "approximately two orders of magnitude". [Mitzi, DB, Kosbar, LL., Murmy, CE, Copel, M. Afzali, A" Nature, page 428 Page, page 299 3〇3]. The field effect mobility of this device is several orders of magnitude lower than that of the conventional single crystal inorganic thin film transistor's device and may be attributed to alignment, tight packaging, and electricity using the method and device configuration disclosed by Duan et al. Contact the actual challenges in discrete nanowires or nanobelts. Nanocrystalline crystal solutions have also been explored as precursors for polycrystalline inorganic semiconductor thin films as a means of providing printable electronic devices that exhibit higher device performance characteristics on plastic substrates. Ridley et al. disclose a solution processing process in which a solution of cadmium selenide crystals having a size of about 2 nanometers is treated at a plastic compatible temperature to provide a semiconductor component of a field effect transistor. [Ridley, BA·, Nivi, B. and Jacobs〇n, j M, Science, Vol. 286, 746-749 (1999)] The authors report a method in which the low temperature in cadmium selenide crystals Grain growth provides an early crystalline region of the inclusion of three hundred nanometer crystals. Although Ridley et al. reported an improved electronic property relative to a comparison device having an organic semiconductor device as a device mobility achieved by such techniques (sl cm2 v·! device than a conventional single crystal inorganic thin film transistor) Field effect mobility is orders of magnitude lower. The limitation of field effect mobility achieved by Ridley et al.'s device configuration and fabrication methods may be due to electrical contact established between individual nanoparticles. The use of organic end groups to stabilize the nanocrystal solution and prevent agglomeration prevents the formation of good electrical contact between adjacent nanoparticles, which is necessary to provide high device field mobility. J50175.doc 201042951 G. Duan et al. and Ridley et al. provide a method for fabricating a thin film transistor on a plastic substrate, the device configuration described comprising mechanically rigid device components such as electrodes, semiconductors and/or dielectrics. The use of a plastic substrate with good mechanical properties provides an electronic device that can operate in an extended or twisted orientation. However, it is expected Deformation can create mechanical stress on individual rigid optoelectronic device components. This mechanical stress can cause damage to individual components, such as cracks, and can also degrade or interrupt electrical contact between device components. Whether electronic systems based on plastic substrates developed by et al., Ridley et al. and others provide the necessary mechanical extensibility for many important device applications, including flexible sensor arrays, electronic paper, and wearable electronic devices. Clearly. Although these teams have demonstrated electronic devices capable of withstanding the deformation caused by deflection, such a system based on plastic embossing is unlikely to undergo considerable extension without damage, mechanical failure, or efficacious effects. The system is degraded. Therefore, such systems are unlikely to withstand the deformation required by the deformation or expansion of the expansion or compression profile to cover highly undulating surfaces, such as curved surfaces having large radii of curvature. It is expected that advances in the field of flexible electronic devices will play a key role in several important new technologies and prior art. However, flexible The success of such applications of SEO technology is highly dependent on new materials, device configurations, and integrated electronic circuits and devices used to fabricate good electrical, mechanical, and optical properties in flexure, deformation, and bending configurations. The continuous development of commercially viable manufacturing processes. In particular, high-performance, mechanically extensible materials and mechanical configurations of electronic and mechanical properties that are not useful in extending or shrinking configurations are required. The present invention provides extendable semiconductors and extendable electronic devices, device implants, and circuits. As used herein, the term "extensible" refers to materials, structures, devices, and device components that can withstand strain without cracking or mechanical failure. The extendable semiconductor and electronic devices of the present invention are extensible and, therefore, extend and/or compress at least to some extent without damage, mechanical failure, or significant degradation in device performance. The extendable semiconductor and electronic circuits of the present invention, which are preferred for certain applications, are flexible (except for being extensible) and are therefore capable of significant elongation, flexing, bending or performing along one or more axes Other variants.

C 本發明之有用的可延伸半導體及電子裝置能伸長、壓 縮、,扭曲及/或膨脹而無機械失效。另外,本發明之可延 伸半導體及電子電路即使當承受顯著應變(諸如大於或等 於約0.5%,較佳1%且最好為2%的應變)時亦展示良好電子 效能。可撓性的可延伸半導體及電子裝置、裝置组件及電 路當處於撓曲、彎曲及/或變形狀態時亦顯示良好的電子 效能。因為本發明之可延伸半導體元件及可延伸電子裝 置裝置組件及電路在撓曲、延伸、壓缩或變形的裝置定 向中可提供有用之電子性f及機械耐用性,所以其適 泛範圍的裝置應用及裝置組態。 本發明之可延伸及/或可撓性半導體亦可(視情況)為可印 刷的’且(視情況)可包含複合半導體元件,其具有_可操 作地與其他結構、材料及/或裝置組件(諸如介電材料Z 層、電極及其他半導體材料及層)連接之半導體結構。本 150175.doc 201042951 發明包括具有可延伸及/或可撓性半導體之廣泛範圍之可 延伸及/或可撓性電子及/或光電子裝置,包括(但不限於) 電晶體、二極體、發光二極體(led)、有機發光二極體 (OLED)、雷射器、微機電裝置及奈米機電裝置、微流體 裝置及奈米流體裝置、記憶體裝置,及系統層級積體電子 電路(諸如互補邏輯電路)。 在一個態樣中,本發明提供當處於撓曲、膨脹、壓縮、C Useful extendable semiconductor and electronic devices of the present invention are capable of elongating, compressing, twisting and/or expanding without mechanical failure. In addition, the extendable semiconductor and electronic circuits of the present invention exhibit good electrical performance even when subjected to significant strains such as greater than or equal to about 0.5%, preferably 1% and preferably 2% strain. Flexible extensible semiconductor and electronic devices, device components, and circuits also exhibit good electrical performance when in a flexed, bent, and/or deformed state. Because the extendable semiconductor component and the extensible electronic device assembly and circuit of the present invention provide useful electronic f and mechanical durability in the orientation of the device for flexing, extending, compressing or deforming, a wide range of device applications are provided. And device configuration. The extendable and/or flexible semiconductor of the present invention may also (as appropriate) be printable and (optionally) may comprise a composite semiconductor component having operatively associated with other structures, materials and/or device components. A semiconductor structure (such as a dielectric material Z layer, electrodes, and other semiconductor materials and layers). The present invention includes a wide range of extendable and/or flexible electronic and/or optoelectronic devices having extendable and/or flexible semiconductors including, but not limited to, transistors, diodes, illumination Diodes, organic light-emitting diodes (OLEDs), lasers, microelectromechanical devices and nanomechanical devices, microfluidic devices and nanofluid devices, memory devices, and system-level integrated electronic circuits ( Such as complementary logic circuits). In one aspect, the invention provides that when in flexion, expansion, compression,

彎曲及/或變形狀態中時可提供有用之功能性質之可延伸 半導體元件。如本文所使用,表述”半導體元件"及”半導 體結構”在本文中等同地使用且泛指任何半導體材料、組 合物或結構,且特別包括高品質單晶及多晶半導體、經由 高溫處理製造之半導體材料、摻雜半導體材料、有機及無 機半導體及具有一或多種額外半導體組份及/或非半導體 組份(諸如’介電層或材料及/或導電層或材料)的複合 體材料及結構。 口 本發明之可延伸半導體元件包含—具有—切表面之可 撓性基板及m㈣表面(例如,由該半導體結構 之-彎曲構形提供的一曲線内表面)之半導體結構。在此 I施例中,該半導黯構之至少—部分曲線 板之㈣表面結合。具有本發明中有用之曲線内I 处,.’匕不吐半導體結構包含彎曲結構。在本文巾,"彎曲 曲具::施加力而導致之曲線構形之結構。本發 …構可具有一或多個折疊區域、凸起區域及/ 或凹入區域。舉例而言’本發明中有用之彎曲結構可以一 150175.doc 201042951 捲曲構形 皺褶構形、一翹棱構形及/或一波狀(意即波 形)組態來提供。 彎曲、構(諸如具有曲線内表面之可延伸彎曲半導體結 構及電子電路)可與諸如聚合物及/或彈性基板之可撓性基 板以-其中該弯曲結構承受應變的構形來結合。在某些實 施例中’忒彎曲結構(諸如一彎曲帶狀結構)承受等於或小 於約30%之應變,在較佳用於某些應用之實施例中承受等 於或】於約1〇/0的應變,及/或在較佳用於某些應用之實施 例十承受等於或小於約1%之應變。在某些實施例中,該 彎曲結構(諸如—冑曲帶狀結構)承受選自約1%至約30%之 範圍之應變。 在有用之實施例中,具有一曲線内表面之半導體結構 包含一至少部分地與該支撐可撓性基板結合的可轉移半導 體元件。在本文中,”可轉移半導體元件”係一能例如經由 沈積技術、印刷技術、圖案化技術及/或其他材料轉移方 法自一供體表面轉移至—受體表面之半導體結構。本方法 中有用之可轉移半導體元件、複合物及裝置包括(但不限 於)可印刷半導體元件。 適用之可撓性基板包括(但不限於)聚合物基板、塑膠基 板及/或彈性基板。舉例而言,在一實施例中,本發明包 含一經轉移且結合至一預應變之彈性基板之可轉移、且 (視情況)可印刷之半導體元件。本發明之此態樣中的有用 之轉移方法包括印刷技術,如接觸印刷或溶液印刷。彈性 基板之隨後鬆弛在該可轉移且(視情況)可印刷之半導體元 i50175.doc -10- 201042951 件上產生一應變,從而導致(例如經由該半導體元件之彎 曲及/或翹> 曲)該曲線内表面之形成。 在某些實施例中,製造(例如如上述)具有曲線内表面之 半導體元件,且隨後將其自用於產生其曲線表面之彈性基 板轉移至一不同可撓性基板且將其與該不同可撓性基板結 合。本發明之此態樣之有用實施例包括一可轉移且(視情 況)可印刷之半導體結構,其包含具有曲線内表面之、彎曲 半導體帶、線、條、碟片、小板、方塊、柱或圓柱,該内 〇 表面具有一敵權、翹棱及/或波形組態。然而,本發明包 括可延伸半導體,其中該半導體元件未經由印刷構件而提 供至該可撓性基板及/或其中該半導體元件係不可印刷 的。 本發明包括可延伸半導體,該等可延伸半導體包含具有 由單一可撓性基板支撐之曲線内表面之單一半導體元件。 或者本發明之可延伸半導體包含複數個可延伸半導體元 〇 # ’該等可延伸半導體元件具有由單-可撓性基板支揮之 曲線内表面。本發明之實施例包括可延伸半導體元件之陣 列或圖案,該等可延伸半導體元件具有由單一可挽性基板 支揮的曲線内表面。可選擇地,該陣列或圖案中之可延伸 半導體元件具有良好界定的、預選擇之實體尺寸、位置及 相對空間取向。 立本::亦包括可延伸電子裝置、裴置組件及/或電路, 或夕個可延伸半導體結構,及額外積體裝置組 ★電觸點、電極、導電層、介電層,及/或額外半 150175.doc 201042951 導體層(例如,摻雜層,面等等)。在此實施例中, 可延伸半導體結構及額外積體裳置組件係可操作地搞合, 以便提供選擇之裝置功能性,且可彼此電接觸或絕緣。在 某些有用之實施例中,額外積體裝置組件(及該(等)可延伸 半導體)之至少一部分或所有部分具有曲線内表面,該等 曲線内表面係由可撓性基板之支撐表面來支撐且提供於 f曲結構中’例如—具有捲曲、波形、趣棱及/或敵摺 構形之彎曲結構。額外積體裝置組件及可延伸半導體之曲 線:表面可具有大體上相同或不同的輪麼形狀。本發明包 括只轭例,其中可延伸裝置組件係經由展示本質可延伸性 之金屬互連件或亦具有波形、皺肖、f曲及/或翹棱構形 之金屬互連件來互連。 額外積體裝置組件之曲線内表面組態係藉由諸如捲曲、 波形、翹棱及/或皺褶組態之電子裝置的一總體上彎曲結 構提供於某些實施例中。在此等實施例中,彎曲結構使此 等裝置即使當承受顯著應變時也能展示良好電子效能諸 如當處於延伸、壓縮及/或彎曲組態時保持與一半導體元 件之導電性或絕緣性。可延伸電子電路可使用與如此處描 述之彼等用以製造可延伸半導體元件之技術類似的技術來 製造。舉例而言,在一實施例中’包括一可延伸半導體元 件之可延伸裝置組件係獨立製造且然後互連。或者,一包 含半導體之裝置可以一平坦組態來製造,且隨後處理所得 平坦裝置以提供一總體上彎曲的裝置結構,其具有某此或 所有裝置組件之曲線内表面。 150175.doc 12 201042951 本發明包括可延㈣子裝置,該等電子裝置包含且有由 早一可撓性基板支樓之曲線内表面之單—電子裝置。或 者’本發明包括可延伸電子裝置陣列,該等陣列包含複數 個可延伸電子裝置或裝置组件,每一者具有由單一可換性 基板支撐之曲線内表面。可選擇地,本發明之裝置陣列中 之可延伸電子農置具有良好界定的、預選擇之實體尺寸、 位置及相對空間取向。 ❹ 〇 在本發明之某些實施例中’半導體結構或電子裝置之曲 線内表面係由—彎曲結構來提供。本發明之半導體及/或 电子裝置之弯曲結構及曲線内表面可具有提供可延伸性及 /或可撓性的任何輪廓形狀,包括(但不限 起區域、至少一凹入區域或至少、_几如广;V個凸 只次至沙一個凸起區域與至少一個 凹入區域之一組合為特徵之輪廓形狀。本發明中有用之輪 廓形狀包括在-個或兩個空間維度上變化之輪廊形狀。使 用具有一内表面(其具有在多個空間維度上展示週期或非 週期變化之輪廓形狀)之彎曲社 一 交的方向之多個方向丄延=有:於提供能在包括正 墊縮、撓曲或進行其他變形 之可延伸半導體及/或電子裝置。 有用之貫施例包括由彎曲半導 供mu h 牛導體…構及/或電子裝置提 i、的曲線内表面,該等彎曲半導體結構及/或電子 ==個凸起及凹入區域之構形,例如以波形組態提 i、之凸起與凹人區域之交替圖案。在—實施例中,可 或可撓性半導體元件或電子裝置之曲㈣表面,或⑽ 情況)整個截面組件具有以大體上週期波形或者大體上非 150175.doc Ί3- 201042951 週期波形為特徵之輪廓形狀。在本文中,週期波形可包含 任何兩維或二維維度波形,包括(但不限於)—或多個正弦 皮方波 Aries函數、高斯(Gaussian)波形、洛仁子 ( Zlan)波形,或此等波形之組合。在另一實施例中, 半導體或電子褒置之曲線内表面,或(視情況)整個截面組 件具有由*數個具有較大振幅及寬度之非週期_棱組成的 輪廓形狀。在另一實施财,半導體或電子裝置之曲線内 表面’或(視情況)整個截面組件具有由週期波形及複數個 非週期翹棱組成的輪廓形狀。 在-實施例中’本發明之可延伸半導體元件或電子裝置 包:二:曲結構’諸如-具有沿其長度及(視情況)寬度之 至/ °卩刀擴展的一週期或非週期波形構形之彎曲帶狀結 冓+例而口,本發明包括彎曲結構,該等彎曲結構包括 具有週期在約1微米與⑽微米之間且振幅在約奈米與 勺微米之間的正弦波構形之彎曲帶狀結構。彎曲結構可 以其他週期波形構形提供,諸如沿此等結構之至少一部分 長度及/或寬度擴展之方波及/或高斯波形。包含彎曲帶狀 D構之可延伸及可撓性半導體元件及可延伸電子裝置可沿 著沿該半導體帶之县# & 長度擴展的軸(諸如沿該曲線内表面之 第一主波形方向擴展之軸)膨脹、壓縮、彎曲及/或變形,且 (視h况)可&多個其他轴(諸如沿該等彎曲結構及曲線 内表面之其他波形方向擴展之軸)膨脹、壓縮、弯曲及/或 變形。 在某二實;^例中’本發明之此態樣之半導體結構及電子 150175.doc •14· 201042951 裝置的構形當受到機械應力或被施加力時會改變。舉例而 言,具有波形或翹棱構形之彎曲半導體結構及電子裝置之 . 週期及/或振幅可回應於所施加機械應力及/或力而改變。 • 在某些實施例中,此改變構形之能力提供了可延伸半導體 結構及電子電路膨脹、麈縮、撓曲、變形及/或弯曲而無 顯著機械損傷、破裂或實質性的電子性質及/或電子裝置 效能之降低的能力。 該半導體結構及/或可延伸電子裝置之曲線内表面可連 續地結合至該支撐表面(意即在沿該曲線内表面之大體上 所有點(例如約9G%)處結合p或者’該半導體結構及/或可 延伸電子裝置之曲線内表面可間斷地與該支樓表面結合, 其中該曲線内表面在沿該曲線内表面的所選點處與該支樓 表面結合。本發明包括實施例,其中該半導體結構或電^ 裝置之曲線内表面與該可撓性基板在離散點處結合,且在 該内表面與該可撓性基板之間的離散的結合點之間該内表 〇 ^具有—曲線構形。本發明包括具有-内表面之彎曲半導 =構及電子裝置’該内表面與該可撓性基板在離散點處 。’其巾㈣離散的結合點藉由未與該可撓性基板直接 結合之翹棱區域而彼此隔離。 在本發明之某些可撓性半導體及/或可撓性電子裝置 :二堇丰導體結構或電子裝置之内表面以一曲線構形提 -〆者’本發明包括以一彎曲構形提供之可延伸半導體 及可延伸電子裝置,其中該彎曲半導體結構或電子裝置之 截面、、且件以一曲線構形提供,諸如波形、敏褶、麵棱 150175.doc •15- 201042951 或捲曲構形。在 導體結構構㈣展穿過該半 -,本二 部分的整個厚度。舉例而 /咬捲曲:能之可延伸半導體包括具有波形、皺褶、勉棱及 :捲曲組態之彎曲半導體帶或條。本發明亦包括組合物 <電子裝置,纟中整個半導體結 體結構或電子裝置之至少大部分以一曲J置或該丰導 波形、敗相或弯曲構形。 肖線_提供,諸如 =些實施例中,該波形、趣棱及/或可延伸構形提供 :―種調節本發明之組合物、材料及裝置之性質的適用性 :途徑。舉例而言,半導體之遷移率及其觸點之性質至少 ::分地取決於應變。本發明中空間變化的應變有助於以有 利的方式調節材料及裝置性質。如另一實例,在波導中之 空間變化之應變引起空間變化之折射率性質(經由彈光效 應)’其亦可有利地用於不同類型光栅耦合器。 可延伸半導體結構及/或電子衆置之内表面與可挽性基 板的外表面之間的結合可使用任何可提供機械上有用之系 、、先的組合物、結構或結合機制來提供,該機械上有用之系 統應能承受延伸及/壓縮移位而無機械失效或電子性質及/ 或效能之顯著降級且(視情況)能撓曲移位而無機械失效或 電子性質及/或效能的顯著降級。該半導體結構及/或電子 裝置與該可撓性基板之間的有用之結合提供了當處於多種 延伸、壓縮及/或撓曲組態或變形時展示有益的電子性質 之機械穩固結構。在本發明之此態樣之一實施例中,該半 ㈣結構及/或電子裝置之内表面之至少一部分與該可撓 150175.doc 16- 201042951 性基板的外表面之間之結合係藉由該半導體結構或電子裝 置與該可撓性基板之外表面之間的共價及/或非共價鍵結 .純供。此等結構巾有用之例示性結合_包括使用該半 - #體結構或電子裳置與該可撓性基板之外表面之間的凡得 瓦爾力交互作用、偶極-偶極交互作用及/或氫鍵結交互作 用。本發明亦包括實施例,其中結合係藉由該半導體結構 或電子裝置與該可撓性基板之外表面之間的一黏接或層屋 f塗層或薄膜來提供。有用之黏接層包括(但不限於;)金 屬層、聚合物層、部分聚合化聚合物前驅層,及複合材料 層。本發明亦包括使用具有一化學改質之外表面之可挽性 基板,以便利(例如)具有置於其外表面上之複數個經基基 團的可撓性基板(諸如聚合物基板)與半導體元件或電子裝 置之結合。本發明包括可撓性半導體及電子電路,其中該 半導體結構或電子電路整體或部分地囊封於一囊封層或塗 層中,諸如一聚合物層。 〇 該半導體結構或電子裝置之實體尺寸及組合物至少部分 地影響本發明之可延伸半導體元件的總體機械及電子性 質。如本文所使用’術語"薄”指一結構具有一小於或等於 約100微米之厚度,且對於某些應用較佳為小於或等於約 50微米之厚度。諸如薄半導體帶、小板及條或薄膜電晶體 之薄半導體結構或電子裝置之使用在某些實施例中係重要 的’以便利諸如波形、捲曲或彎曲曲線内表面之曲線内表 面之形成,從而提供能延伸、收縮及/或繞曲而無損傷、 機械失效或電子性質的顯著降級之構形。諸如薄可印刷半 150175.doc -17· 201042951 導體結構之薄半導體結構及電子裝置之使用對包含諸如單 晶及/或多晶無機半導體的脆性半導體材料之可延伸半導體 及可延伸電子裝置尤其有用。在一有用之實施例中,該半 導體結構或電子電路具有在約1微米至約1厘米之範圍上選 擇之寬度及在約50奈米至約50微米的範圍上選擇之厚度。An extendable semiconductor component that provides useful functional properties in a bent and/or deformed state. As used herein, the expression "semiconductor element" and "semiconductor structure" are used equally herein and generally refer to any semiconductor material, composition or structure, and particularly include high quality single crystal and polycrystalline semiconductor, fabricated via high temperature processing. Semiconductor materials, doped semiconductor materials, organic and inorganic semiconductors, and composite materials having one or more additional semiconductor components and/or non-semiconductor components such as 'dielectric layers or materials and/or conductive layers or materials. The extensible semiconductor device of the present invention comprises a semiconductor structure having a flexible substrate having a -cut surface and an m (four) surface (eg, a curved inner surface provided by the curved configuration of the semiconductor structure). In the embodiment, at least the surface of the semi-conductive structure is bonded to the (four) surface of the curved plate. There is a curve in the useful curve of the present invention, and the semiconductor structure of the semiconductor structure comprises a curved structure. In this paper, "bend Having: a structure in which a curve is formed by applying a force. The present invention may have one or more folded regions, raised regions, and/or recessed regions. For example, 'the curved structure useful in the present invention can be provided by a 150175.doc 201042951 crimp configuration, a warp configuration, and/or a wave (ie, waveform) configuration. An extendable curved semiconductor structure such as a curved inner surface and an electronic circuit can be combined with a flexible substrate such as a polymer and/or an elastic substrate in a configuration in which the curved structure is strained. In some embodiments A meandering curved structure, such as a curved ribbon structure, is subjected to a strain of equal to or less than about 30%, and is subjected to strains equal to or at about 1 Torr/0 in embodiments preferred for certain applications, and/or Embodiments that are preferred for certain applications are subjected to strains equal to or less than about 1%. In certain embodiments, the curved structure, such as a tortuous ribbon structure, is selected to be selected from about 1% to about 30. A strain in the range of %. In a useful embodiment, a semiconductor structure having a curved inner surface includes a transferable semiconductor component at least partially bonded to the support flexible substrate. In this context, "transferable semiconductor component" Department one Transferring semiconductor structures from a donor surface to a receptor surface, for example, via deposition techniques, printing techniques, patterning techniques, and/or other material transfer methods. Useful transferable semiconductor components, composites, and devices useful in the method include However, it is not limited to a printable semiconductor component. Suitable flexible substrates include, but are not limited to, polymer substrates, plastic substrates, and/or elastic substrates. For example, in one embodiment, the invention includes a transfer and combination Transferable and (as appropriate) printable semiconductor components to a pre-strained elastomeric substrate. Useful transfer methods in this aspect of the invention include printing techniques such as contact printing or solution printing. Subsequent relaxation of the elastic substrate Producing a strain on the transferable and (as appropriate) printable semiconductor element i50175.doc -10- 201042951, resulting in (for example via bending and/or warping of the semiconductor component) the inner surface of the curve form. In some embodiments, a semiconductor component having a curved inner surface is fabricated (eg, as described above) and subsequently transferred from a flexible substrate used to create its curved surface to a different flexible substrate and is otherwise flexible The substrate is bonded. A useful embodiment of this aspect of the invention includes a transferable and (as appropriate) printable semiconductor structure comprising curved semiconductor strips, wires, strips, discs, plates, blocks, columns having curved inner surfaces Or a cylinder having an enemies, ridges, and/or wave configuration. However, the invention includes an extendable semiconductor wherein the semiconductor component is not provided to the flexible substrate via a printed member and/or wherein the semiconductor component is unprintable. The present invention includes extendable semiconductors comprising a single semiconductor component having a curved inner surface supported by a single flexible substrate. Or the extensible semiconductor of the present invention comprises a plurality of extensible semiconductor elements 〇 # ' such extensible semiconductor elements having curved inner surfaces that are supported by a single-flex flexible substrate. Embodiments of the invention include an array or pattern of extensible semiconductor components having curved inner surfaces that are supported by a single leutable substrate. Optionally, the extensible semiconductor component in the array or pattern has a well defined, pre-selected physical size, location, and relative spatial orientation.立本:: Also includes extendable electronics, device components and/or circuits, or extended semiconductor structures, and additional integrated device sets ★ electrical contacts, electrodes, conductive layers, dielectric layers, and/or Extra half 150175.doc 201042951 Conductor layer (eg doped layer, face, etc.). In this embodiment, the extendable semiconductor structure and the additional integrated skirt assembly are operatively coupled to provide selected device functionality and are electrically or insulative to each other. In certain useful embodiments, at least a portion or all of the additional integrated device components (and the extendable semiconductor) have curved inner surfaces that are supported by the support surface of the flexible substrate. Supported and provided in a curved structure of, for example, a curved structure having a curled, wavy, interesting, and/or entrapped configuration. Additional integrated device components and curves of extendable semiconductors: the surfaces may have substantially the same or different wheel shapes. The present invention includes a yoke-only example in which the extendable device components are interconnected via metal interconnects that exhibit substantial extensibility or metal interconnects that also have a corrugated, corrugated, f-curved, and/or raised configuration. The curved inner surface configuration of the additional integrated device assembly is provided in certain embodiments by a generally curved configuration of electronic devices such as crimp, wave, rib, and/or wrinkle configurations. In such embodiments, the curved structure allows such devices to exhibit good electrical performance even when subjected to significant strain, such as maintaining electrical conductivity or insulation with a semiconductor component when in an extended, compressed, and/or curved configuration. The extendable electronic circuitry can be fabricated using techniques similar to those described herein for fabricating extensible semiconductor components. For example, in one embodiment, an extensible device component comprising an extendable semiconductor component is fabricated separately and then interconnected. Alternatively, a semiconductor-containing device can be fabricated in a flat configuration and the resulting planar device can be subsequently processed to provide a generally curved device structure having a curved inner surface of one or all of the device components. 150175.doc 12 201042951 The present invention includes extendable (four) sub-devices comprising and having a single-electronic device from the curved inner surface of the early flexible substrate support. Or the invention includes an array of extendable electronic devices comprising a plurality of extendable electronic devices or device components, each having a curved inner surface supported by a single interchangeable substrate. Alternatively, the extendable electronic farm in the array of devices of the present invention has well defined, pre-selected physical dimensions, locations, and relative spatial orientations. ❹ 〇 In some embodiments of the invention, the inner surface of the curved surface of the semiconductor structure or electronic device is provided by a curved structure. The curved structure and curved inner surface of the semiconductor and/or electronic device of the present invention may have any contour shape that provides extensibility and/or flexibility, including (but not limited to, at least one recessed area or at least, _ a plurality of V-convex to sand and one convex region combined with one of the at least one concave region as a characteristic contour shape. The contour shape useful in the present invention includes a wheel that varies in one or two spatial dimensions. The shape of the gallery. The use of an inner surface (which has a contour shape that exhibits a periodic or aperiodic change in a plurality of spatial dimensions) is extended in a plurality of directions. An extendable semiconductor and/or electronic device that shrinks, flexes, or otherwise deforms. Useful embodiments include curved inner surfaces of curved halves for mu h bovine conductors and/or electronic devices. Curved semiconductor structure and/or electron == configuration of raised and recessed regions, for example, in a waveform configuration, an alternating pattern of raised and concave regions. In an embodiment, may be flexible or flexible Semiconductor element (Iv) or the curved surface of the electronic device, or the case ⑽) the entire cross section of the assembly has a profile shape is characterized by a substantially periodic waveform or substantially non 150175.doc Ί3- 201042951 periodic waveform. In this context, the periodic waveform may comprise any two-dimensional or two-dimensional dimensional waveform, including (but not limited to) - or a plurality of sine-skin square wave Aries functions, Gaussian waveforms, Zlan waveforms, or the like. A combination of waveforms. In another embodiment, the curved inner surface of the semiconductor or electronic device, or (as appropriate) the entire cross-section assembly has a contour shape consisting of *a plurality of aperiodic _ ribs having a large amplitude and width. In another implementation, the curved inner surface of the semiconductor or electronic device or (as appropriate) the entire cross-section assembly has a contour shape consisting of a periodic waveform and a plurality of non-periodic warps. In an embodiment, the extensible semiconductor component or electronic device package of the present invention: two: a curved structure such as - has a period or aperiodic waveform structure extending along its length and (as appropriate) width to / ° boring tool A curved ribbon-like knot + exemplified, the present invention includes a curved structure comprising a sinusoidal configuration having a period between about 1 micrometer and (10) micrometer and an amplitude between about nanometer and scoop micron. Curved ribbon structure. The curved structure can be provided in other periodic waveform configurations, such as square and/or Gaussian waveforms that extend along at least a portion of the length and/or width of the structures. An extendable and flexible semiconductor component comprising a curved ribbon D structure and an extendable electronic device extendable along an axis extending along the length of the semiconductor strip (such as along a first main waveform of the inner surface of the curved surface) The axis) expands, compresses, bends, and/or deforms, and (depending on the condition) can expand, compress, and bend a plurality of other axes, such as an axis extending along the curved structures and other directions of the inner surface of the curved surface. And / or deformation. In a certain embodiment, the semiconductor structure and the electron of the aspect of the invention are changed. The configuration of the device changes when subjected to mechanical stress or when a force is applied. By way of example, the curved semiconductor structure and electronic device having a wavy or warped configuration may have a period and/or amplitude that may vary in response to applied mechanical stress and/or force. • In some embodiments, the ability to modify the configuration provides for extensible semiconductor structures and electronic circuits to expand, collapse, flex, deform, and/or bend without significant mechanical damage, cracking, or substantial electronic properties and / or the ability to reduce the performance of electronic devices. The curved inner surface of the semiconductor structure and/or the extendable electronic device can be continuously bonded to the support surface (ie, bonding p or 'the semiconductor structure) at substantially all points (eg, about 9 G%) along the inner surface of the curve And/or the curved inner surface of the extendable electronic device is intermittently engageable with the surface of the support, wherein the curved inner surface is joined to the surface of the support at a selected point along the inner surface of the curve. The present invention includes an embodiment, Wherein the curved inner surface of the semiconductor structure or the electrical device is bonded to the flexible substrate at discrete points, and the inner surface between the inner surface and the discrete bonding point between the flexible substrate has a curved configuration. The invention includes a curved semiconductor with an inner surface = an electronic device 'the inner surface and the flexible substrate are at discrete points. 'The wipe (4) discrete joints are not The flexible substrates are directly isolated from each other by the ridged regions. In some flexible semiconductors and/or flexible electronic devices of the present invention: the inner surface of the Erfengfeng conductor structure or electronic device is provided in a curved configuration - 〆 The invention includes an extendable semiconductor and an extendable electronic device provided in a curved configuration, wherein the curved semiconductor structure or electronic device has a cross section, and the member is provided in a curved configuration, such as a waveform, a pleat, a face rib 150175 .doc •15- 201042951 or crimped configuration. The conductor structure (4) extends through the half-, the entire thickness of the two parts. For example, / bite curl: energy extendable semiconductors include waveforms, wrinkles, ridges And: a curved configuration of a curved semiconductor strip or strip. The invention also includes a composition <electronic device, wherein at least a majority of the entire semiconductor junction structure or electronic device is in a curved or fused phase Or curved configuration. The chord line provides, for example, some of the embodiments, the waveform, the interesting edge and/or the extendable configuration provide: - Applicability to adjust the properties of the compositions, materials and devices of the invention: For example, the mobility of the semiconductor and the nature of its contacts are at least: the ground depends on the strain. The spatially varying strain in the present invention helps to adjust the material and device properties in an advantageous manner. In one example, the spatially varying strain in the waveguide causes spatially variable refractive index properties (via the bounce effect) 'which can also be advantageously used for different types of grating couplers. Extensible semiconductor structures and/or electronic condominiums The bonding between the surface and the outer surface of the levable substrate can be provided using any mechanically useful system, prior composition, structure or bonding mechanism that is capable of withstanding extension and/or compression. Displacement without mechanical failure or significant degradation of electronic properties and/or performance and (as appropriate) flexural displacement without mechanical failure or significant degradation of electronic properties and/or performance. The semiconductor structure and/or electronic device The useful combination between the flexible substrates provides a mechanically stable structure that exhibits beneficial electronic properties when subjected to a variety of extension, compression, and/or flexing configurations or deformations. In an embodiment of this aspect of the invention, the bonding between at least a portion of the inner surface of the semi-four structure and/or electronic device and the outer surface of the flexible 150175.doc 16-201042951 substrate is Covalent and/or non-covalent bonding between the semiconductor structure or electronic device and the outer surface of the flexible substrate. An exemplary combination of such structural towels useful - including the use of the half-# body structure or electronic skirt and the van der Waals interaction between the outer surface of the flexible substrate, dipole-dipole interaction and / Or hydrogen bonding interactions. The invention also includes embodiments in which bonding is provided by a bond or laminate or film between the semiconductor structure or electronic device and the outer surface of the flexible substrate. Useful bonding layers include, but are not limited to, metal layers, polymer layers, partially polymerized polymer precursor layers, and composite layers. The invention also includes the use of a leutable substrate having a chemically modified outer surface to facilitate, for example, a flexible substrate (such as a polymer substrate) having a plurality of radical groups disposed on an outer surface thereof. A combination of semiconductor components or electronic devices. The present invention includes flexible semiconductors and electronic circuits in which the semiconductor structure or electronic circuitry is wholly or partially encapsulated in an encapsulation layer or coating, such as a polymeric layer. The physical dimensions and compositions of the semiconductor structure or electronic device at least partially affect the overall mechanical and electronic properties of the extensible semiconductor component of the present invention. As used herein, the term "thin" refers to a structure having a thickness of less than or equal to about 100 microns, and preferably less than or equal to about 50 microns for certain applications, such as thin semiconductor strips, small plates, and strips. The use of a thin semiconductor structure or electronic device of a thin film transistor is important in some embodiments to facilitate the formation of a curved inner surface such as a curved, curled or curved inner surface to provide extension, contraction and/or Winding without damage, mechanical failure, or significantly degraded configuration of electronic properties. Such as thin printable half 150175.doc -17· 201042951 The thin semiconductor structure of the conductor structure and the use of electronic devices include such as single crystal and / or more Extendable semiconductors and extendable electronic devices of fragile semiconductor materials of crystalline inorganic semiconductors are particularly useful. In a useful embodiment, the semiconductor structure or electronic circuit has a width selected over a range of from about 1 micron to about 1 cm and A thickness selected from the range of from about 50 nanometers to about 50 micrometers.

該支撑可撓性基板之組合物及實體尺寸亦可至少部分地 影響本發明之可延伸半導體元件及可延伸電子裝置的總體 機械性質。有用之可撓性基板包括(但不限於)厚度選自約 0.1毫米至約1〇〇微米之範圍的可撓性基板。在一有用之實 0 施例中,該可撓性基板包含一聚(二曱基矽氧烷)PDMS 層,且具有在約0.1毫米至約10毫米的範圍上選擇之厚 度。 本發明亦包括部分處理之可延伸半導體元件或部分處理 之可延伸半導體電路。舉例而言在一實施例中,本發明 包括Si帶,其上具有pn二極體裝置。以一波形構形提供之 si帶被可選擇地提供於一PDMS基板上。於此等(絕緣)二極 體之間提供互連件,以使得該二極體輸出(例如,光電流)0 能被放大,例如經由利用蔭罩(shadow mask)之金屬蒸鍍。 在貝把例中,在彈性體上製造複數個獨立的可延伸電晶 體。以某些方式連線個別電晶體(例如藉由蔭罩蒸鍍)以製 造其他有用之電路,例如由以特定方式連接之若干電晶體 組成之電路。對於此等狀況,該#互連金屬線亦為可延伸 的,因此吾人具有在彈性體上的完全可延伸電路。 在另一態樣中’本發明提供用以製造一可延伸半導體元 150175.doc -18- 201042951 件之方法,其包含以下步驟:(丨)提供具有内表面之可轉移 半導體結構;(2)提供處於一膨脹狀態之預應變彈性基板, 其中該彈性基板具有一外表面;將該可轉移半導體結構 的内表面之至少一部分與處於膨脹狀態之預應變彈性基板 之外表面結合;及(4)允許彈性基板至少部分地鬆弛至一鬆 弛狀悲,其中該彈性基板的鬆弛使該可轉移半導體結構之 内表面f曲,進而產生具有一曲線内表面之可延伸半導體 元件。在本發明之此態樣之某些實施例中,該預應變彈性 〇 基板沿第一轴膨脹,且視情況沿一相對該第一軸正交地定 位的第二軸膨脹。在一有用之實施例中,提供至該預應變 彈性基板之可轉移半導體元件係一可印刷半導體元件。 在另一態樣中,本發明提供一用以製造一可延伸電子電 路之方法’其包含以下步驟:⑴提供-具有-内表面之可 轉移電子包路,(2)提供處於一膨脹狀態之預應變彈性基 板,其中該彈性基板具有一外表面;(3)將該可轉移電子電 0 路的内表面之至少一部分與處於膨脹狀態之預應變彈性基 板之外表面結合;及⑷允許該彈性基板至少部分地鬆弛至 -鬆他狀態,其中該彈性基板的鬆他使該電子電路之内表 面彎曲,進而產生該可延伸電子電路。在一有用之實施例 中,提供至該預應變彈性基之可轉移電子電路係—可印 刷電子电路,諸如能經由印刷技術(諸如乾式轉移接觸印 刷)轉移之電子電路。在某些實施例中,電子電路包含複 數個積體褒置組件,包括(但不限於):一或多個半導體元 件(諸如可轉移、且(視情況)可印刷之半導體元件)、介電 150175.doc -19· 201042951 70件電極、包括超導元件之導電元件、及摻雜半導體元 k也本發明之该態樣之方法可進一步包含自該支擇 彈性基板㈣可延伸半導體或可延伸電子電路轉移至—接 收基板之步驟,該轉移之方式至少部分地保留該半導體元 件或電子電路的曲線内表面及/或彎曲結構。該半導體妹 構或電子電路被轉移至一接收基板,該接收基板係可撓: 的,諸如一聚合物接收基板,或一包含紙、金屬或半導體 之接收基板。在此實施例中,所轉移之可延伸半導體或可 延伸電子裝置可經由廣泛範圍之手段而與該接收基板(如 可撓性、聚合物接收基板)結合,該等手段包括(但不限 於)使用黏接及/或層壓層、薄膜及/或塗層,諸如黏接層 (如聚醯亞胺膠層)。或者,所轉移的可延伸半導體或可延 伸電子哀置可經由所轉移的可延伸半導體或可延伸電子裝 置與接收基板之間之氫鍵結、共價鍵結、偶極-偶極交互 作用及凡得瓦爾力交互作用而與諸如可撓性、聚合物接收 基板的接收基板結合。 在一實施例中,在製造具有由一彈性基板支撐之波形、 翹棱、皺褶或捲曲構形之彎曲半導體結構及/或電子電路 後,使用一適當黏接層或塗層將此等結構轉移至另一基板 上。舉例而言’纟-實施例中,纟一彈性體基板上製備波 形光伏打裝置,且然後(例如)使用聚醯亞胺作為膠層將其 轉移至金屬$上。在該等光伏打裝置與下㈣金屬羯(其 可充當集極之一,例如藉由圖案化、蝕刻以製造通孔以曝 150175.doc -20- 201042951 露金屬表面、金屬沈積物等等)之間建立電連接。此組態 之光伏打裝置之波狀表面可被利用以增強光捕獲(或減少 光反射)。舉例而言,為獲得更好之抗反射結果’可在此 皮狀表面上作進一步處理,諸如使表面粗趟度遠小於波狀 半導體之波長。簡單說來,可將部分或全部處理之波狀/ 彎曲半導體/電路轉移至其他基板上(不限於卿),且若 必要可藉由添加進一步處理來獲得更增強的使用效能。 可、土也本發明之方法可進—步包含囊封、覆蓋或層壓 該可延伸半導體或可延伸電子裝置之步驟。在此上下文 囊封在刀層翹棱結構之狀況下包括其中該囊封材料被 提供於該等趣棱之凸起區域下以完全丧入該麵棱結構的所 有側面的幾何形狀及構形。囊封亦包括在該彎曲半導體結 構或電子電路之凸起及未凸起特徵之頂部提供一囊封層, 諸如聚口物層。在一實施例中,將諸如預聚合物之 預聚合物洗鍀ϋ固化於該可延料導體或可延伸電子裝置 ◎上對於某些應用,囊封或覆蓋處理步驟有助於增強本發 明之可延伸半導體及電子裝置之機械穩定性及穩固性。本 發明包括當處於延伸、壓縮、彎曲及/或撓曲構形時展示 良好機械及電子效$之囊封、I蓋及/或Μ之可延伸半 導體及電子裝置。 可選地,本發明之此態樣之方法包括在諸如聚合物基板 (例如,2D超溥聚合物基板)或無機基板(例如Si〇2)之供體 基板上組裝半導體元件、裝置组件及/或功能性裝置之步 驟。在此實施例中,然後將在該供體基板上組裝之結構轉 150175.doc -21- 201042951 移至預應變彈性體基板以形成可延伸材料、裝置或裝置組 件。在一實施例中,電晶體、電晶體陣列或具有電晶體之 電子裝置首先被組裝在供體基板上,例如經由使用可印刷 半導體元件之印刷技術。接著,將整個裝置及/或裝置陣 列轉移至預應變彈性基板(例如藉由接觸印刷法)以形成可 延伸波开乂及/或翹棱系統。當在轉移至可延伸彈性體支撲 物之前在一薄的、非彈性體材料(類似聚醯亞胺或苯幷環 丁烯或PET等等)上製備裝置互連件及製造實際尺寸電路較 為有利時此方法係有用的。在此類系統中,在組合電晶體 /聚合物膜/彈性體基板系統中將獲得非週期2D波形或翹棱 結構。 對在本方法中有用的彈性基板進行預應變之方法包括在 與半導體結構及/或電子裝置接觸及結合之前及/或期間中 ’考曲、捲曲、撓曲、及膨脹該彈性基板(例如,藉由使用 一機械平臺)。在多個方向上預應變彈性基板之一尤其有 用之方法包含在與半導體結構及/或電子裝置接觸及結合 之前及/或期間中藉由升高彈性基板的溫度而使該彈性基 板熱膨脹。在此等實施例中,彈性基板的鬆弛是藉由在與 忒可轉移、且(視情況)可印刷之半導體元件或電子裝置接 觸及/或結合之後降低該彈性基板之溫度來達成。在某些 方法中,藉由引入約1%至約3〇%之應變來將該彈性基板預 應變。 在本文中’表述"彈性基板”指可延伸或變形且可返回至 其原始形狀而無實質上永久變形之基板。彈性基板通常承 150175.doc -22- 201042951 受實質上彈性的變形。本發明中有用之例示性彈性基板包 括(但不限於)彈性體及强极拼 頫及彈性體、展示彈性之聚合物及共聚 物之複合材料或混合物。在某些方法中,經由一提供該彈 f基板β或夕個主轴膨脹之機構來預應變該彈性基板。 舉例而言’可藉由沿第-軸膨脹該彈性基板來提供預應 變。然而,本發明亦包括沿複數個轴使該彈性基板膨脹之 方法,例如經由沿相對彼此正交定位之第一及第二韩的膨 ❹ Ο 脹。本方法中可用的經由提供彈性基板之膨服的機構而預 應變彈性基板之手段包括變曲'捲曲、撓曲、整平、㈣ 或以其它方式使該彈性基板變形。本發明亦包括藉由升高 该彈性基板之溫度進而提供該彈性基板的熱膨服而提供預 應變之手段。 本發明之方法亦能自不同於半導體材料之材料製造可延 伸疋件、裝置及裝置組件。本發明包括將諸如絕緣體、超 導體’及半金屬之非半導體結構轉移並結合至一預應變彈 性基板之方法。允許彈性基板至少部分地鬆他會導致且有 =内表面之可延伸非半導體結構(例如具有波形及/或勉 棱輪廓形狀之非半導體姓Μ、& , Ή等體…構)的形成。本發明之此態樣包 括具有彎曲結構之可延伸非半導體結構,該彎曲結構諸如 以捲曲構形 '皺相構形 '赵棱構形及/或以波形組態提供 之内表面及(視情況)外表面。 :本發明之可延伸半導體、電子裝置及/或裝置組件中 之可触基板包括(但不限於)聚合物基板及/或塑膠基 反。可延伸半導體包括包含-或多個可轉移 '(視情況)可 150175.doc •23- 201042951 印刷之半導體結構(諸如可印刷半導體元件)之組合物,其 由在製造期間預應變的一彈性基板支撐,以產生該半導體 曲線内表面。或者’可延伸半導體包括包含一或多個可轉 移半導體結構(諸如可印刷半導體元件)之組合物,其由不 同於在製造期間預應變的彈性基板之可撓性基板支撐,以 產生該半導體曲線内表面。舉例而言,本發明包括可延伸 半導體,其中具有一曲線内表面之半導體結構被自該彈性 基板轉移至一不同可撓性基板。 【實施方式】 參看該等圖式,類似參考號指示類似元件且在多個圖式 中出現之相同參考號指相同元件。另外,在下文中,以下 定義適用: tl ’·可印刷,,係關於能轉移、裝配、圖案化、組織及/或整合 至基板上或其中之材料、結構、裝置組件及/或積體功能 裝置。在本發明之一實施财,可印刷材料、元件、裝置 組件及裝置能經由溶液印刷或乾式轉移接觸印刷而轉移、 裝配、圖案化、組織及/或整合至基板上 本發明之"可印刷半導體元件,,包含能(例域用乾式轉移 接觸印刷及/或溶液印刷方法)裝配及/或整合至基板表面上 之半導體結構。在一f絲你丨φ,士 & η 杜么敕Μ 本發明之可印刷半導體元 半導^ /晶⑽吻eryStaUine)、多晶或微晶無機 的單體H ο在本文中,整體結構係具有機械相連之特徵 件。本發明之半導體元件可為未摻雜或摻雜的, 有摻雜劑之選擇的空間分佈,且可以包括咖型摻雜 150175.doc -24- 201042951 Ο Ο 劑的複數個不同摻雜劑材料來摻雜。本發明包括:至少_ 個截面尺寸大於或等於約1微米之微結構可印刷半導體元 件、及至少一個截面尺寸小於或等於約㈣米的奈米結構 可印刷半導體元件。在許多應用中有用之可印刷半導體包 含由對高純度塊體材料(諸如使用習知高溫處理技術產生 之高純度結晶半導體晶圓)之"由上而下"處理而獲取之元 件。在-實施例中,本發明之可印刷半導體元件包含複合 結構,其具有一操作地連接至至少一個額外裝置組件或結 構(諸如導電層、介電層、電極、額外半導體結構或此等 之任何組合)之半導體。在—實施例中,本發明之可印刷 半導體元件包含可延仲丰導_練; 、彳甲牛導體兀件及/或異質半導體元 件。 "截面尺寸”指裝置、裝置組件或材料之截面之尺寸。截 面尺寸包括寬度、厚度、半徑及直徑。舉例而言,具有帶 形狀之半導體元件以-長度及兩個截面尺寸:厚度及寬 度,為特徵。舉例而言,且有 有圓柱形狀之可印刷半導體元 件以-長度及截面尺寸:直徑(或者半徑),為特徵。 由一基板支撐”指至少部分地存在於-基板表面或至少 ^ 刀地存在於一或多個位於該結構與該基板表面之間的中 篏入基板之結構。 基板支樓亦可指部分或全部 ”溶液印刷m旨諸如可印刷半導體 構藉以分散入-載體介質 一戈夕個結 面之所選區域的過程。Γ二Γ 至基板表 紅在一例不性溶液印刷方法中,結構 150175.doc •25- 201042951 被傳送至一基极矣ιϋ夕π、雜r- 、區域係藉由與經受圖案化之其 板表面的形態及/或實體 ’、之基 中可伟田 ㈣特性㈣之方法來達成。本發明 中可使用之溶液印刷方法 ^ 73 匕括(但不限於)噴墨印刷、埶韓 移印刷’及毛細作用印刷。 … "大體上縱向取向”指使得諸 群體之縱軸的方向…* 附導體几件之元件 ^大體上與—所選對準財行的取向。在 此疋義之上下文中,盘— — 〃斤選軸大體上平行指在與絕對平 订方向偏差10度圍肉人 偏差' 11 ,較佳為在與絕對平行方向 偏差5度乾圍内的取向。 可延伸”指材料、結構、梦罟弋駐罢47 苒裝置或裝置組件承受應變而盔 破裂之能力。在一例示性實施例中,-可延伸材料、: 構、裝置或裝置組件可承受大於約〇5%之應變而無破裂, 對於某些應錄佳可承受大於約1%之應變而無破裂,且 對於某些應用最好可承受大於約3%的應變而無破裂。 術語”可撓性,,及,,可彎曲,,在本文中等同地使用,且指材 料、結構、裝置或裝置組件變形為一曲線形狀而不經受會 引入顯著應變的轉換之能力’該等顯著應變可諸如特徵化 材料、结構、裝置或裴置組件之失效點的應變。在—例示 性實施例中,可撓性材料、結構、裝置或裝置組件可變形 為曲線形狀而不引入大於或等於約5%之應變,對於某些 應用較佳不引入大於或等於約1%之應變’且對於某些應 用最好不引入大於或等於約〇 5%之應變。 該術語,,翹棱,,指當薄元件' 結構及/或裝置藉由在該元 件”構及/或纟置之平面外的方向上膏曲❿回應於一壓 150175.doc • 26 - 201042951 縮應變時發生的實體變形。本發明包括具有一或多個表面 之可延伸半導體、裝置及組件,該或該等表面具有包含一 或多個翹棱之輪廓形狀。 ”半導體”指任何在極低溫度下係一絕緣體但在約300絕 對溫度下具有一明顯導電性之材料。在本文中,對術語半 導體之使用希望與此術語在微電子及電子裝置之技術領域 中的使用一致。適用於本發明之半導體可包含諸如矽、鍺 及金剛石之元素半導體,以及複合半導體,諸如第IV族複 〇 合半導體(諸如SiC及SiGe)、第III-V族半導體(諸如AlSb、 AlAs、Ain、A1P、BN、GaSb、GaAs、GaN、GaP、InSb、 InAs、InN及InP)、第III-V族三元半導體合金(諸如AUGa^As) 、第 II-VI族半導體(諸如 CsSe、CdS、CdTe、ZnO、ZnSe、 ZnS,及ZnTe)、第I-VII族半導體CuCl、第IV-VI族半導體 (諸如PbS、PbTe及SnS)、層半導體(諸如Pbl2、MoS2及 GaSe)、氧化物半導體(諸如CuO及Cu20)。術語半導體包括 以一或多種選擇之材料摻雜的外質半導體及本質半導體 〇 (包括具有P型摻雜材料及η型摻雜材料的半導體)以提供適 用於給定應用或裝置之有利電子性質。術語半導體包括包 含半導體及/或摻雜劑之一混合物之複合材料。適用於本 發明之某些應用之特殊半導體材料包括(但不限於)Si、 Ge、SiC、A1P、AlAs、AlSb、GaN、GaP ' GaAs、GaSb、 InP、InAs、GaSb、InP、InAs、InSb、ZnO、ZnSe、 ZnTe 、 CdS 、 CdSe 、 ZnSe 、 ZnTe 、 CdS 、 CdSe 、 CdTe 、 HgS、PbS、PbSe、PbTe、AlGaAs、AlInAs、AllnP、 150175.doc -27- 201042951The composition and physical dimensions of the support flexible substrate can also at least partially affect the overall mechanical properties of the extensible semiconductor component and the extendable electronic device of the present invention. Useful flexible substrates include, but are not limited to, flexible substrates having a thickness selected from the range of from about 0.1 mm to about 1 μm. In a useful embodiment, the flexible substrate comprises a poly(dimercaptodecane) PDMS layer and has a thickness selected from the range of from about 0.1 mm to about 10 mm. The invention also includes partially processed extendable semiconductor components or partially processed extendable semiconductor circuits. For example, in one embodiment, the invention includes a Si ribbon having a pn diode device thereon. The si strips provided in a waveform configuration are optionally provided on a PDMS substrate. Interconnects are provided between the (insulated) diodes such that the diode output (e.g., photocurrent) 0 can be amplified, such as by metal evaporation using a shadow mask. In the case of the shell, a plurality of independent extensible transistors are fabricated on the elastomer. Individual transistors are wired in some manner (e.g., by shadow mask evaporation) to make other useful circuits, such as circuits composed of a number of transistors connected in a particular manner. For these conditions, the #interconnect metal wire is also extensible, so we have a fully extendable circuit on the elastomer. In another aspect, the invention provides a method for fabricating an extensible semiconductor element 150175.doc -18- 201042951, comprising the steps of: (丨) providing a transferable semiconductor structure having an inner surface; (2) Providing a pre-strained elastic substrate in an expanded state, wherein the elastic substrate has an outer surface; at least a portion of an inner surface of the transferable semiconductor structure is bonded to an outer surface of the pre-strained elastic substrate in an expanded state; and (4) The elastic substrate is allowed to at least partially relax to a relaxed shape, wherein the relaxation of the elastic substrate causes the inner surface of the transferable semiconductor structure to be curved, thereby producing an extendable semiconductor component having a curved inner surface. In some embodiments of this aspect of the invention, the pre-strained elastic 基板 substrate expands along a first axis and optionally expands along a second axis that is orthogonally positioned relative to the first axis. In a useful embodiment, the transferable semiconductor component provided to the pre-strained flexible substrate is a printable semiconductor component. In another aspect, the present invention provides a method for fabricating an extendable electronic circuit that includes the steps of: (1) providing a transferable electronic packet with an inner surface, and (2) providing an expanded state. a pre-strained elastic substrate, wherein the elastic substrate has an outer surface; (3) combining at least a portion of an inner surface of the transferable electronic circuit with an outer surface of the pre-strained elastic substrate in an expanded state; and (4) allowing the elasticity The substrate is at least partially relaxed to a relaxed state wherein the elastic substrate elastically bends an inner surface of the electronic circuit to produce the extendable electronic circuit. In a useful embodiment, a transferable electronic circuit to the pre-strained elastomeric circuit is provided - a printable electronic circuit, such as an electronic circuit that can be transferred via a printing technique such as a dry transfer contact printing. In some embodiments, the electronic circuit includes a plurality of integrated device components, including but not limited to: one or more semiconductor components (such as transferable and (as appropriate) printable semiconductor components), dielectric 150175.doc -19· 201042951 70 pieces of electrodes, conductive elements including superconducting elements, and doped semiconductor elements k. The method of this aspect of the invention may further comprise extensible semiconductors or extensions from the selective elastic substrate (4) The electronic circuit is transferred to a receiving substrate in a manner that at least partially retains the curved inner surface and/or curved structure of the semiconductor component or electronic circuit. The semiconductor component or electronic circuit is transferred to a receiving substrate that is flexible, such as a polymer receiving substrate, or a receiving substrate comprising paper, metal or semiconductor. In this embodiment, the transferred extensible semiconductor or extendable electronic device can be combined with the receiving substrate (eg, a flexible, polymer receiving substrate) via a wide range of means including, but not limited to, Adhesive and/or laminate layers, films and/or coatings are used, such as adhesive layers (eg, polyimide layers). Alternatively, the transferred extensible semiconductor or extensible electrons may be hydrogen bonded, covalently bonded, dipole-dipole interaction between the transferred extensible semiconductor or extendable electronic device and the receiving substrate, and Van Valle interacts with a receiving substrate such as a flexible, polymer-receiving substrate. In one embodiment, after fabricating a curved semiconductor structure and/or electronic circuit having a wavy, warped, pleated or crimped configuration supported by an elastomeric substrate, the structure is applied using a suitable adhesive layer or coating. Transfer to another substrate. For example, in the embodiment, a corrugated photovoltaic device is prepared on a ruthenium elastomer substrate, and then transferred to the metal $, for example, using polyimine as a glue layer. In the photovoltaic device and the lower (four) metal ruthenium (which can serve as one of the collectors, for example, by patterning, etching to make via holes to expose 150175.doc -20- 201042951 exposed metal surface, metal deposits, etc.) Establish an electrical connection between them. The wavy surface of this configured photovoltaic device can be utilized to enhance light capture (or reduce light reflection). For example, a better anti-reflection result can be further processed on the skin surface, such as making the surface roughness much less than the wavelength of the wavy semiconductor. Briefly, some or all of the processed wavy/curved semiconductor/circuit can be transferred to other substrates (not limited to qing) and, if necessary, further processing can be added to achieve enhanced performance. The method of the present invention may further comprise the step of encapsulating, covering or laminating the extensible semiconductor or extendable electronic device. In this context, the encapsulation of the scalloped structure includes the geometry and configuration in which the encapsulating material is provided under the raised regions of the ribs to completely immerse the rib structure. Encapsulation also includes providing an encapsulation layer, such as a layer of agglomerates, on top of the convex and non-protruding features of the curved semiconductor structure or electronic circuit. In one embodiment, a prepolymer such as a prepolymer is cured on the extendable conductor or extendable electronic device ◎. For some applications, the encapsulation or overlay processing steps help to enhance the invention. It can extend the mechanical stability and stability of semiconductors and electronic devices. The present invention includes expandable semiconductors and electronic devices that exhibit good mechanical and electronic effectiveness when in extended, compressed, bent and/or flexed configurations. Optionally, the method of this aspect of the invention comprises assembling a semiconductor component, a device component, and/or on a donor substrate such as a polymer substrate (eg, a 2D ultra-twisted polymer substrate) or an inorganic substrate (eg, Si〇2). Or the steps of a functional device. In this embodiment, the structure assembled on the donor substrate is then transferred 150175.doc -21 - 201042951 to a pre-strained elastomeric substrate to form an extensible material, device or device assembly. In one embodiment, a transistor, an array of transistors, or an electronic device having a transistor is first assembled on a donor substrate, such as via a printing technique using a printable semiconductor component. Next, the entire apparatus and/or array of devices is transferred to a pre-strained elastic substrate (e.g., by contact printing) to form an extendable wave opening and/or warping system. Preparation of device interconnects and fabrication of actual size circuits on a thin, non-elastomeric material (similar to polyimide or benzoquinone cyclobutene or PET, etc.) prior to transfer to an extensible elastomeric patch This method is useful when advantageous. In such systems, aperiodic 2D waveforms or warped edges will be obtained in a combined transistor/polymer film/elastomer substrate system. The method of pre-straining an elastic substrate useful in the method includes 'study, curl, flex, and expand the elastic substrate (e.g., before, during, and/or during contact with and in conjunction with the semiconductor structure and/or electronic device). By using a mechanical platform). One method of pre-straining an elastic substrate in a plurality of directions is particularly useful for thermally expanding the elastic substrate by increasing the temperature of the elastic substrate before and/or during contact with and bonding with the semiconductor structure and/or electronic device. In such embodiments, the relaxation of the elastic substrate is achieved by lowering the temperature of the flexible substrate after contact and/or bonding with the transferable and (as appropriate) printable semiconductor component or electronic device. In some methods, the elastic substrate is pre-strained by introducing a strain of from about 1% to about 3%. As used herein, the term 'elastic substrate' refers to a substrate that can be extended or deformed and can be returned to its original shape without substantial permanent deformation. The elastic substrate is typically subjected to a substantially elastic deformation of 150175.doc -22- 201042951. Exemplary elastic substrates useful in the invention include, but are not limited to, elastomers and composites or mixtures of elastomers and elastomers, elastomeric polymers and copolymers. In some methods, the cartridge is provided via one f substrate β or a main axis expansion mechanism to pre-strain the elastic substrate. For example, 'the pre-strain can be provided by expanding the elastic substrate along the first axis. However, the present invention also includes the elasticity along a plurality of axes. The method of expanding the substrate, for example, via first and second enthalpy expansions positioned orthogonally relative to each other. The means available in the method for pre-straining the elastic substrate via a mechanism that provides expansion of the elastic substrate includes variability 'Curling, flexing, leveling, (d) or otherwise deforming the elastic substrate. The invention also includes providing the elastic group by raising the temperature of the elastic substrate Thermal expansion provides a means of pre-straining. The method of the present invention can also produce extensible components, devices and device components from materials other than semiconductor materials. The invention includes non-semiconductors such as insulators, superconductors' and semi-metals. A method of transferring and bonding a structure to a pre-strained elastic substrate. Allowing the elastic substrate to at least partially loosen the resulting non-semiconductor structure with an inner surface (eg, a non-semiconductor surname with a wavy and/or ridged profile) The formation of &, Ή, etc.. The aspect of the invention includes an extensible non-semiconductor structure having a curved structure, such as a wrinkle configuration of a crimped configuration, and a configuration of a ridge structure and/or Or an inner surface and (as appropriate) an outer surface provided in a waveform configuration. The touchable substrate in the extensible semiconductor, electronic device and/or device assembly of the present invention includes, but is not limited to, a polymer substrate and/or plastic The base semiconductor includes a semiconductor structure comprising - or a plurality of transferable (as appropriate) 150175.doc • 23- 201042951 printed (such as printable semi-conductive a composition of elements that is supported by an elastomeric substrate that is pre-strained during fabrication to produce the inner surface of the semiconductor curve. Or 'extensible semiconductors include one or more transferable semiconductor structures (such as printable semiconductor components). a composition supported by a flexible substrate different from an elastic substrate pre-strained during manufacture to produce an inner surface of the semiconductor curve. For example, the invention includes an extendable semiconductor having a semiconductor structure having a curved inner surface The same reference numerals are used to refer to like elements and the same reference numerals are used in the various drawings to refer to the same elements. In addition, in the following The following definitions apply: tl '·printable, relating to materials, structures, device components and/or integrated functional devices that can be transferred, assembled, patterned, organized and/or integrated onto or into a substrate. In one embodiment of the invention, printable materials, components, device components and devices can be transferred, assembled, patterned, organized, and/or integrated onto a substrate via solution printing or dry transfer contact printing. The semiconductor component comprises a semiconductor structure that can be assembled (eg, by dry transfer contact printing and/or solution printing methods) and/or integrated onto the surface of the substrate. In a f wire you 丨φ,士& η杜么敕Μ The invention of the printable semiconductor element semiconducting ^ / crystal (10) kiss eryStaUine), polycrystalline or microcrystalline inorganic monomer H ο In this article, the overall structure It has mechanically connected features. The semiconductor device of the present invention may be undoped or doped, with a selected spatial distribution of dopants, and may include a plurality of different dopant materials that are doped with a 150175.doc-24-201042951 咖 剂 agent. To dope. The invention includes at least one microstructure-printable semiconductor component having a cross-sectional dimension greater than or equal to about 1 micron and at least one nanostructure printable semiconductor component having a cross-sectional dimension of less than or equal to about (four) meters. Printable semiconductors useful in many applications include those obtained from "top-down" processing of high purity bulk materials such as high purity crystalline semiconductor wafers produced using conventional high temperature processing techniques. In an embodiment, the printable semiconductor component of the present invention comprises a composite structure having an operative connection to at least one additional device component or structure (such as a conductive layer, a dielectric layer, an electrode, an additional semiconductor structure, or any of these) Combined) semiconductor. In an embodiment, the printable semiconductor component of the present invention comprises a semiconductor element, and an ortho semiconductor element. "Sectional dimension" refers to the dimensions of the cross-section of a device, device component or material. The cross-sectional dimensions include width, thickness, radius and diameter. For example, a semiconductor component having a strip shape with a length and two cross-sectional dimensions: thickness and width For example, a cylindrically printable semiconductor component is characterized by a length and a cross-sectional dimension: diameter (or radius). Supported by a substrate means at least partially present on the surface of the substrate or at least ^ Knife is present in one or more structures that are interposed between the structure and the surface of the substrate. The substrate support may also refer to a process in which some or all of the solution printing is performed, such as a printable semiconductor structure, to be dispersed into a selected region of the carrier medium. The substrate is red in the case of an inactive solution. In the printing method, the structure 150175.doc •25- 201042951 is transferred to a base 矣ιϋ π, the hetero-r-, the region is formed by the morphology and/or the entity of the surface of the plate subjected to patterning. It can be achieved by the method of Weitian (4) characteristic (4). The solution printing method which can be used in the present invention includes, but is not limited to, ink jet printing, yttrium printing, and capillary printing. ... "substantial longitudinal orientation "refers to the orientation of the longitudinal axes of the groups...* The elements of the conductors are generally aligned with the selected alignment. In the context of this derogatory meaning, the disk---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- . "Extensible" means the ability of a material, structure, nightmare device or device assembly to withstand strain and rupture of the helmet. In an exemplary embodiment, the extensible material, structure, device or device component can withstand greater than A strain of about 5% without cracking, for some applications, can withstand strains greater than about 1% without cracking, and for some applications it is best to withstand strains greater than about 3% without cracking. Flexibility, and, bendable, is used equally herein, and refers to the ability of a material, structure, device, or device component to be deformed into a curved shape without undergoing a transformation that introduces significant strains. Strain such as the point of failure of a characterization of a material, structure, device, or component. In an exemplary embodiment, the flexible material, structure, device, or device component can be deformed into a curved shape without introducing a strain greater than or equal to about 5%, and for some applications preferably does not introduce greater than or equal to about 1%. The strain' and for some applications it is preferred not to introduce a strain greater than or equal to about 5%. The term, rib, means that when a thin component 'structure and/or device is smeared in a direction outside the plane of the component's configuration and/or placement, it responds to a pressure 150175.doc • 26 - 201042951 Solid deformation that occurs when strain is reduced. The invention includes extensible semiconductors, devices and assemblies having one or more surfaces having a contour shape comprising one or more ridges. "Semiconductor" means any pole A material that is an insulator at low temperatures but has a significant conductivity at about 300 absolute temperatures. In this context, the use of the term semiconductor is intended to be consistent with the use of this term in the art of microelectronics and electronic devices. The semiconductor of the present invention may comprise elemental semiconductors such as ruthenium, iridium and diamond, and composite semiconductors such as Group IV complex conjugated semiconductors (such as SiC and SiGe), Group III-V semiconductors (such as AlSb, AlAs, Ain, A1P). , BN, GaSb, GaAs, GaN, GaP, InSb, InAs, InN, and InP), Group III-V ternary semiconductor alloys (such as AUGa^As), Group II-VI semiconductors (such as CsSe, CdS, CdTe, ZnO, ZnSe, ZnS, and ZnTe), Group I-VII semiconductor CuCl, Group IV-VI semiconductors (such as PbS, PbTe, and SnS), layer semiconductors (such as Pbl2, MoS2, and GaSe), oxide semiconductors (such as CuO) And Cu20). The term semiconductor includes an exogenous semiconductor and an intrinsic semiconductor germanium (including a semiconductor having a P-type dopant material and an n-type dopant material) doped with one or more selected materials to provide a suitable application or device. Advantageous electronic properties. The term semiconductor includes composite materials comprising a mixture of semiconductors and/or dopants. Specific semiconductor materials suitable for use in certain applications of the invention include, but are not limited to, Si, Ge, SiC, AlP, AlAs , AlSb, GaN, GaP 'GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO, ZnSe, ZnTe, CdS, CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe , AlGaAs, AlInAs, AllnP, 150175.doc -27- 201042951

GaInP、AlGaAsSb、AlGalnP 及GaInP, AlGaAsSb, AlGalnP and

GaAsP、GalnAs 夕孔矽半導體材料適用於本發明在感測器及諸 如發光二極體(LED)及固態雷射之發光材料領域中之應 用半導體材料之雜質係不同於該(等)半導體材料自身或 任何提供至半導體材料之摻雜劑的原子、元素、離子及/ 或分子。雜質係可對半導體材料之電子性f造成負面影響 之存^於半導體材料中的不當物質,纟包括(但不限於) 氧厌及包括重金屬之金屬。重金屬雜質包括(但不限 於)週期表上銅與錯之 間之元素族、鈣、鈉,及其所有離 子、複合物及/或錯合物。 塑陡♦日任何合成或自然產生之材料或材料之組合,通 常當加熱時可將其模製或成型且硬化為一所要形狀。適用 於本發明之裝置及方法之例示性塑膠包括(但不限於)聚合 物、樹脂及纖維素衍生物。在本文中,術語塑性用以包括 包含具有-或多種添加物之一或多種塑膠的複合塑性材 料,該等添加物可諸如結構增強劑、填充劑、纖維、增塑 劑、穩定劑或可提供所要之化學或物理性質之添加物。 介電質”及"介電材料”在本文中等同地使用,且指對電 流具高阻抗之物質。適用之介電材料包括(但不限 於)Si〇2、Ta205、Ti02、Zr02、Y2〇3、siN4、ST〇、BST、 PLZT、PMN及 PZT。 聚合物"指包含複數個通常稱為單體之重複化學基團之 分子。聚合物通常以高分子質量為特徵。本發明中可用之 聚合物可為有機聚合物或無機聚合物,且可處於非晶系、 150175.doc -28- 201042951 Ο Ο 半非晶系、晶體或部分晶體狀態。聚合物可包含具有相同 化學組成之單體或可包含具有不同化學組成的複數個單體 (諸如共聚物)。具有鏈結的單體鏈之交聯聚合物尤其適用 於本發明之某些應用。可用於本發明之方法、裝置及裝置 組件之聚合物包括(但不限於)塑膠、彈性體、熱塑性彈性 體、彈性塑膠、彈性塑膠、恆溫器(thermostat)、熱塑膠及 丙烯酸酯。例示性聚合物包括(但不限於)縮醛聚合物、生 物可降解聚合物、纖維素聚合物、含氣聚合物、耐論、聚 丙烯腈聚合物、聚醯胺_醯亞胺聚合物 '聚醯亞胺、聚芳 醋化合物、聚苯幷咪唾、聚丁烯、聚碳酸酯、聚酯、聚醚 酿亞胺、聚乙稀、聚乙稀共聚物及經改質聚乙稀、聚綱、 聚^甲基丙稀酸甲醋)' 聚甲基戊婦、聚苯謎及聚苯硫喊、 聚苯二甲醯胺、聚丙婦、聚胺基甲酸醋、苯乙稀樹脂、硬 基樹脂、乙烯基樹脂或其任何組合。 彈性體"指可延伸或變形且返回至其原始形狀而無實質 上永久變形的聚合材料。彈性體通常經受實質上彈性變 形。適用於本發明之彈性基板至少部分包含一或多個彈性 體。適用於本發明之例示性彈性體可包含聚合物、共聚 物、複合材料或聚合物與共聚物之混合物。彈性體層指包 3至J -個彈性體之層。彈性體層亦可包括推雜劑及其他 非彈性體材料°適用於本發明之彈性體可包括(但不限於) …i I·生彈!·生體、苯乙婦類材料、婦煙材料、聚稀煙、聚胺 基甲酸S曰熱塑性彈性體、聚酸胺、合成橡膠、鳩、聚 丁二稀、聚異丁烯、聚(苯乙烯-丁二缚-苯乙,烯)、聚胺基 I50175.doc •29- 201042951 曱酸酯、聚氯丁二烯及聚矽氧。 良好電子效能”及”高效能"在本文中等同地使用,且指 裝置及裝置組件具有可提供諸如電子訊號開關及/或放大 之所要功能性的諸如場效應遷移率、臨限電壓及開-關比 例之電子特性。本發明之展示良好電子效能之例示性可轉 移2、且視情況可印刷之半導體元件可具有大於或等於1〇〇 cmV sl的本質場效應遷移率,對於某些應用較佳具有 大於或等於約30WV、、本質場效應遷移率。本發明 之展不良好電子效能之例示性電晶體可具有大於或等於⑥〇 100 cm V S的寰置場效應遷移率’對於某些應用較佳具 有大於或等於約300 cm2 V“ s-i的裝置場效應遷移率,且對 於某些應用最好具有大於或等於約_ 一 γ 一的裝置場 效應遷移率。本發明之展示良好電子效能之例示性電晶體 可具有小於約5伏特的臨限電壓及/或大於約ΐχΐ〇4之開_關比 例。GaAsP, GalnAs 矽 矽 semiconductor material is suitable for use in the field of sensors and luminescent materials such as light-emitting diodes (LEDs) and solid-state lasers, and the impurity of the semiconductor material is different from the semiconductor material itself. Or any atom, element, ion and/or molecule that provides a dopant to the semiconductor material. Impurities are undesired substances in semiconductor materials that can adversely affect the electronic properties of semiconductor materials, including but not limited to oxo and metals including heavy metals. Heavy metal impurities include, but are not limited to, the family of elements, calcium, sodium, and all their ions, complexes, and/or complexes between copper and copper on the periodic table. Plastic Steep ♦ Any synthetic or naturally occurring material or combination of materials that is typically molded or shaped and hardened into a desired shape when heated. Exemplary plastics suitable for use in the devices and methods of the present invention include, but are not limited to, polymers, resins, and cellulose derivatives. As used herein, the term plasticity is intended to include composite plastic materials comprising one or more plastics having - or a plurality of additives, such additives may be provided as structural enhancers, fillers, fibers, plasticizers, stabilizers or may be provided Additives of desired chemical or physical properties. Dielectric "dielectric materials" are used equivalently herein and refer to materials that have a high impedance to current. Suitable dielectric materials include, but are not limited to, Si〇2, Ta205, Ti02, Zr02, Y2〇3, siN4, ST〇, BST, PLZT, PMN, and PZT. Polymer " refers to a molecule comprising a plurality of repeating chemical groups commonly referred to as monomers. Polymers are generally characterized by high molecular weight. The polymer usable in the present invention may be an organic polymer or an inorganic polymer, and may be in an amorphous state, 150175.doc -28- 201042951 Ο Ο semi-amorphous, crystalline or partially crystalline state. The polymer may comprise monomers having the same chemical composition or may comprise a plurality of monomers (such as copolymers) having different chemical compositions. Crosslinked polymers having a chained monomeric chain are especially useful in certain applications of the invention. Polymers useful in the methods, devices, and device components of the present invention include, but are not limited to, plastics, elastomers, thermoplastic elastomers, elastomers, elastomers, thermostats, thermoplastics, and acrylates. Exemplary polymers include, but are not limited to, acetal polymers, biodegradable polymers, cellulosic polymers, gas-containing polymers, resistance, polyacrylonitrile polymers, polyamido-imine polymers Polyimine, polyaryl vinegar, polybenzoquinone, polybutene, polycarbonate, polyester, polyetherimide, polyethylene, polyethylene copolymer and modified polyethylene, Polymethane, polymethyl methacrylate, 'polymethyl valerate, poly benzene and polyphenyl sulfonate, polyphthalamide, polypropylene, polyurethane, styrene resin, Hard base resin, vinyl resin or any combination thereof. Elastomer " refers to a polymeric material that can be stretched or deformed and returned to its original shape without substantial permanent deformation. Elastomers are typically subjected to substantial elastic deformation. The elastic substrate suitable for use in the present invention at least partially comprises one or more elastomers. Exemplary elastomers suitable for use in the present invention may comprise a polymer, a copolymer, a composite or a mixture of a polymer and a copolymer. The elastomer layer refers to a layer of 3 to J - an elastomer. The elastomer layer may also include a dopant and other non-elastomeric materials. The elastomers suitable for use in the present invention may include, but are not limited to, ... i I · bio-bombs; bio-materials, benzene-based materials, maternity materials, Polystyrene, polycarbamic acid S 曰 thermoplastic elastomer, polyamine, synthetic rubber, hydrazine, polybutylene, polyisobutylene, poly(styrene-butyl bis-phenylene, olefin), polyamine I50175 .doc •29- 201042951 Phthalate, polychloroprene and polyfluorene. "Good electronic performance" and "high performance" are used equally herein, and means that the device and device components have such desirable functions as electronic signal switching and/or amplification, such as field effect mobility, threshold voltage, and on. - Off-line electronic characteristics. Exemplary transferable semiconductor devices of the present invention that exhibit good electronic performance, and optionally printable semiconductor components, can have an intrinsic field effect mobility greater than or equal to 1 〇〇 cmV sl, preferably greater than or equal to about some applications. 30WV, the nature of field effect mobility. An exemplary transistor of the present invention that exhibits poor electronic performance can have a field effect mobility greater than or equal to 6 〇 100 cm VS'. For some applications, it preferably has a device field effect greater than or equal to about 300 cm2 V" si Mobility, and for some applications, preferably has a device field effect mobility greater than or equal to about _ gamma 1. An exemplary transistor exhibiting good electronic performance of the present invention can have a threshold voltage of less than about 5 volts and/or Or greater than about ΐχΐ〇4 open_off ratio.

”大面積',指大於或等於約36平方英忖之面積,諸如用於 裝置製造之基板的—接收表面的面積。 ’’裝置場效應遷移率"指使用與電子裝置對應之 产 資料計算得之諸如電晶體的電子裂置之場效應遷移率。μ "楊氏模數”係、材料、裝置或層之-機械性質,其指—給 定物質之應力與應變的比例。楊氏模數可由以下陳述 供: Χ 應變zj, (II) 150175.doc ·30· 201042951 其中E係楊氏模數,L係平 0你十衡長度’ AL係在所施加應力 下之長度變化’ F係所施加之力且錢施加力的面積。揚氏 •模數亦可通過以下方程式根據Lame常數來表示: Ε — μ(3λ + 2μ). λ + μ, (HI) 其中λ及μ係Lame常數。高揚氏模數(或”高模數,,)及低揚 氏模數(或"低模數”)係對—給定材料、層或裝置中揚氏模 數之大小的相對描述。在本發明中,高楊氏模數比低揚氏 ¢) 減更大,對於某些應用而言較佳約大⑽,對於其他應 用而言最好約大100倍,且對於另一些應用而言最好約大 1000 倍。 在下文中’闡明本發明之裝置、裝置組件及方法之大量 特定細節以提供對本發明的準確性質之詳細說明。然而, 對於熟習此項技術者將顯而易見的是,無此等特定細節也 可實踐本發明。 本發明提供當延n縮、撓曲或者以其他方式變形時 ❹ ㊣提供良好效能之可延伸半導體及電子電路。另外,本發 月之可延伸半導體及電子電路可經調適用於廣泛範圍的裝 置組態以提供完全可撓性的電子及光電子裝置。 圖1提供一展示本發明之可延伸半導體結構之原子力顯 微圖。該可延伸半導體元件700包含一具有一支撐表面710 之可撓性基板705(諸如聚合物及/或彈性基板)及一具有一 曲線内表面720之彎曲半導體結構715。在此實施例中,彎 曲半導體結構715之曲線内表面72〇之至少一部分與該可撓 150175.doc -31 - 201042951 性基板705之支撐表面71〇結合。曲線内表面72〇可在沿内 表面720之經選擇點處或在沿内表面72〇的大體上所有點處 與支撐表面m結合。圖i中所說明之例示性半導體結構包 含一具有一等於約100微米之寬度及一等於約100奈米之厚 度之單晶矽彎曲帶。圖i中說明之可撓性基板係一具有約i 毫米之厚度之PDMS基板。曲線内表面72〇具有一彎曲結 構,其包含沿該帶之長度擴展之一大體上週期性的波形。 如圖1所不,忒波之振幅約為5〇〇奈米且該尖鋒間距約為 微米。圖2展示了提供具有曲線内表面72Q之彎曲半導體結 構715之展開視圖的原子力顯微圖。圖3展示本發明之可延 伸半導體結構之一陣列的原子力顯微圖。對圖3中原子力 顯微圖之分析展示該等弯曲半導體結構被壓縮了約 1·27%。圖4展示本發明之可延伸半導體結構之光學顯微 圖0 曲線内表面720之輪廓形狀允許彎曲 形㈣轉脹或壓縮而不經受大量機械//、,。構715沿變 又亢里機械應變。此輪廓形狀 彎曲、結構在不同於變形軸730方向的方向上 :=或變形而無由應變引發之顯著機械損傷或效能 貝失本發明之半導體結構之曲線表面可 機械,|·生暂l $提供’良好 ==如可延伸性、可撓性及/或可彎曲性)及/或良 應遷移率……… 甲次變㈣展示良好場效 j)的任何輪廓㈣。例示性輪廓形狀可具有以下 特徵、、有複數個凸起及/或凹入區域,且 波、高斯波、Aries函數、方波、洛;有包括正弦 子波、週期波、無週 150l75.doc -32· 201042951 期波或此等波之任何組合之多種波形。適用於本發明之波 形可關於兩個或三個實體維度而變化。 ^圖5展示本發明之可延伸半導體結構的原子力顯微圖, 該結構之半導體結構715結合至具有三維起伏圖案之可撓 性基板705 ’該二維起伏圖案位於該基板之支撐表面no 上。該三維起伏圖案包含凹入區域750及起伏特徵76〇。如 圖5所示,彎曲半導體結構715在凹入區域75〇中及起伏特 徵760上與支撐表面71〇結合。 圖6展不一說明製造本發明之可延伸半導體結構之一例 不性方法的流程圖。在該例示性方法中,提供處於一膨脹 狀態之一預應變彈性基板。預應變可藉由該項技術中習知 之任何方法來達成,其包括(但不限於)輥壓及/或預彎曲該 彈性基板。肖應變亦可經由熱方法,例如通過由升高該彈 性基板之溫度引發之熱膨脹來達成。經由熱方法之預應變 之一優勢係可達成沿複數個不同軸(諸如正交的軸)之膨 脹。 本發明之此方法中可用之例示性彈性基板係一具有等於 約1亳米的厚度之PDMS基板。該彈性基板可藉由沿一單 軸之膨脹或藉由沿複數個軸之膨脹來預應變。如圖6所 示,可印刷半導體元件之至少一部分内表面與處於一膨脹 狀態之預應變彈性基板的外表面結合,結合可藉由該半導 體表面之内表面之間的共價鍵結、藉由凡得瓦爾力、藉由 使用黏結劑或藉由此等方法之任何組合來達成。在該彈性 基板係PDMS之例示性實施例中,該1>〇1^8基板之支撐表面 150175.doc -33- 201042951 ,農化學改貝使得其具有複數個自其表面擴展的羥基以促進 ’、矽半導體結構之共價鍵結。再參看圖6,在將該預應 變彈性基板與半導體結構結合之後,允許該彈性基板至少 部分地鬆弛至-鬆弛狀態。在此實施例中,該彈性基板之 鬆弛使該半導體結構之内表面彎曲,$而產生—具有曲線 内表面的半導體元件。 如圖6中所示,該製造方法可視情況包括一第二轉移步 驟及視情況之鍵結步驟,其中將具有—曲線内表面72〇之 可轉移半導體元件715自該彈性基板轉移至另—基板較 佳-可撓性基板,諸如-聚合物基板。此第二轉移步驟可 藉由使具有-曲線内表面72()之半導體結構715之曝露表面 與另一與该半導體結構71 5的曝露表面結合之基板之一接 收表面接觸來達成。與該另—基板之結合可藉由能至少部 分保持該半導體元件之彎曲結構的任何途徑來完成,其包 括共價鍵、經由凡得瓦爾力之鍵結、偶極_偶極交^作 用、倫敦(1^“)力之鍵結及/或氫鍵結。本發明亦包括使 用提供於該可轉移半導體結構之—曝露表面與該接收表面 之間的黏接層、塗層及/或薄膜。 本發明之可延伸半導體元件可有效地整合人大量功能性 裝置及裝置組件’諸如電晶體、二極體、雷射、編s、 MS、LEDS及OLEDS。本發明之可延伸半導體元件盘習 知剛性無機半導體相比具有某些功能性優勢。首先,;延 伸半導體元件可為可撓性的,且因此比習知剛性 體更少受由挽曲、f曲及/或變形引起之結構損壞:: 150175.doc -34- 201042951 響”人因為彎曲半導體結構可處於一輕微機械應變狀 〜、以提供曲線内表面,所以本發明之可延伸半導體元件 ,、習知無應變剛性半導體相比可展示更高之本質場效應遷 移率最後,因為可延伸半導體元件在裝置溫度循環中能 自由膨脹及收縮,所以其可能提供良好之熱性質。 Ο ❹ 曰展示具有一波狀構形之縱向對準的可延伸丰導體之 :列之影像:如圖7所示,該等半導體帶被以=: 提供且由一單一可撓性橡膠基板支撐。 圖8展示本發明之可延料導體元件之—截面影像,其 +導體結構776由該可撓性基板m來支撑。如圖8所 二半導體結構776具有内表面,該等内表面具有一週期 波之輪廓形狀。亦如圖8所 半導雜结構―::;。該週期波構形擴展穿過 延=Γ當延伸、撓曲或變形時具有良好效能之可 延伸電子電路、裝置及裝置陣列。盥 件類似,本發明提供可延#雷i " I伸半導體元 4徒供了延伸電路及電子裝置,其且 有一支撐表㈣可撓性基板,該切 :表面(諸如展示-波形結構之曲線内表面;的裝置:置線 觸。r結構排列中,該裝置、裝置陣:ΐ 电塔結構之至少一部分曲结 ^ 丨刀曲線内表面與該可撓性 結合。本發明之此態樣之裝置、裝置陣列:電路係’ 體之積體裝置組件的多組件元件。在—例示導 具有小於約ι〇微米之淨厚度之可挽性電路、裝置及2陣 150175.doc -35. 201042951 列包含複數個積體裝置組件,其至少一部分具有週期波曲 線結構。 在本發明之-有用之實施例中,提供包含複數個互連組 件的獨立式電子電路或裝置。言亥電子電路或裳置之一内表 面與-處於-膨脹狀態之預應變彈性基板接觸且至少部分 結合。預應變可藉由該項技術中已知之任何方法來達成, 其包括(但不限於)輥壓及/或預彎曲該彈性基板,且可藉由 沿-單-軸之膨脹或藉由沿複數個軸的膨脹來預應變該彈 性基板。結合可直接藉由該電子電路或裝置之至少一部分 内表面與該預應變彈性基板之間的共價鍵或凡得瓦爾力來 實現,或藉由使用黏接劑或一中間結合層來達成。在使該 預應變彈性基板與該電子電路或裝置結合之後,允許該彈 性基板至少部分地鬆弛至一麩补壯能 鬆弛狀恶,其使該半導體結構 之内表面彎曲。該電子電路或裝置之内表面之彎曲產生一 曲線内表面,其在某些有用的實施例中具有一週期或益週 期波構形。本發明包括多個實施例,纟中包含電子裝置或 電路之所有組件皆存在於一週期或無週期波組離中。 J延伸電子電路、裝置及裝置陣列之週期或無„波組 其遵守延伸或幫曲組態而不在該等電路或裝置之個 別組件上產生大應變。本發明之此態樣提供可延伸電子電 路、裝置及裝置陣列當處於弯曲、延伸或變形狀態時之有 =之電子性質。藉由本方法形成之週期波組態之週期可根 據以下來變化:⑴包含該電路或裝置的積體組件之集人之 淨厚度及⑼包含積體裝置組件的材料之諸如楊氏錢 150175.doc • 36 - 201042951 撓曲剛性之機械性質。 圖9A展不一說明製造可延伸薄膜電晶體之陣列之例示性 方法之流程圖。如圖9A所示,使用本發明之技術提供獨立 式可印刷薄膜電晶體之-陣列。將薄膜電晶體之陣列經由 乾式轉移接觸印刷方法以一曝露該等電晶體之内表面之方 式轉移至一 PDMS基板。接著將所曝露内表面與處於一膨 脹狀態之室溫固化預應變PDMS層接觸。該預應變1>〇1^3層"Large area" means an area greater than or equal to about 36 square feet, such as the area of the receiving surface of the substrate used for device fabrication. ''Device field effect mobility' refers to the calculation of the production data corresponding to the electronic device. The field effect mobility of electron-cracking such as a transistor. μ "Young's modulus, the mechanical property of a material, device, or layer, which refers to the ratio of stress to strain for a given material. Young's modulus can be stated by: Χ strain zj, (II) 150175.doc ·30· 201042951 where E is the Young's modulus, L is flat 0, and you are the length of the 'AL system' under the applied stress. 'F is the area exerted by force and the amount of force exerted by the money. Young's modulus can also be expressed by the following equation according to the Lame constant: Ε — μ(3λ + 2μ). λ + μ, (HI) where λ and μ are the Lame constants. High Young's modulus (or "high modulus,") and low Young's modulus (or "low modulus") are pairs of relative descriptions of the magnitude of Young's modulus in a given material, layer, or device. In the present invention, the high Young's modulus is much less than the lower Young's modulus, preferably greater (10) for some applications, and about 100 times larger for other applications, and for other applications. It is best to say that it is about 1000 times larger. In the following, a number of specific details of the apparatus, device components and methods of the invention are set forth to provide a detailed description of the precise nature of the invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without the specific details. The present invention provides extendable semiconductors and electronic circuits that provide good performance when extended, deflected, or otherwise deformed. In addition, the extended semiconductor and electronic circuits of this month can be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices. Figure 1 provides an atomic force micrograph showing an extensible semiconductor structure of the present invention. The extendable semiconductor component 700 includes a flexible substrate 705 (such as a polymer and/or elastomeric substrate) having a support surface 710 and a curved semiconductor structure 715 having a curved inner surface 720. In this embodiment, at least a portion of the curved inner surface 72 of the curved semiconductor structure 715 is bonded to the support surface 71 of the flexible 150175.doc -31 - 201042951 substrate 705. The curved inner surface 72A can be joined to the support surface m at selected points along the inner surface 720 or at substantially all points along the inner surface 72〇. The exemplary semiconductor structure illustrated in Figure i includes a single crystal germanium ribbon having a width equal to about 100 microns and a thickness equal to about 100 nanometers. The flexible substrate illustrated in Figure i is a PDMS substrate having a thickness of about i mm. Curved inner surface 72A has a curved configuration that includes a substantially periodic waveform that extends along one of the lengths of the strip. As shown in Figure 1, the amplitude of the chopping is about 5 nanometers and the pitch of the spikes is about micrometers. Figure 2 illustrates an atomic force micrograph providing an expanded view of a curved semiconductor structure 715 having a curved inner surface 72Q. Figure 3 shows an atomic force micrograph of an array of extensible semiconductor structures of the present invention. Analysis of the atomic force micrographs in Figure 3 shows that the curved semiconductor structures were compressed by about 127%. Figure 4 shows an optical microscopy of the extensible semiconductor structure of the present invention. The contoured shape of the curved inner surface 720 allows the curved shape (4) to be swollen or compressed without undergoing substantial mechanical//,. The structure of the 715 is changed along with the mechanical strain. The contour shape is curved, and the structure is in a direction different from the direction of the deformation axis 730: = or deformation without significant mechanical damage caused by strain or loss of performance. The curved surface of the semiconductor structure of the present invention can be mechanically, | Provide 'good == extensibility, flexibility and / or bendability) and / or good mobility ... ... A change (4) shows any contour (4) of good field effect j). The exemplary contour shape may have the following features, a plurality of convex and/or concave regions, and waves, Gaussian waves, Aries functions, square waves, and Luo; including sinusoidal wavelets, periodic waves, and no cycles 150l75.doc -32· 201042951 Period wave or multiple waveforms of any combination of these waves. Waveforms suitable for use in the present invention may vary with respect to two or three physical dimensions. Figure 5 shows an atomic force micrograph of an extensible semiconductor structure of the present invention bonded to a flexible substrate 705' having a three-dimensional relief pattern on the support surface no of the substrate. The three-dimensional relief pattern includes a recessed region 750 and an undulating feature 76〇. As shown in FIG. 5, the curved semiconductor structure 715 is bonded to the support surface 71A in the recessed region 75A and on the undulating feature 760. Figure 6 is a flow chart showing an exemplary method of fabricating an extensible semiconductor structure of the present invention. In the exemplary method, a pre-strained elastic substrate in one expanded state is provided. Pre-straining can be achieved by any method known in the art including, but not limited to, rolling and/or pre-bending the elastomeric substrate. The slant strain can also be achieved via a thermal process, such as by thermal expansion caused by raising the temperature of the elastomeric substrate. One of the advantages of pre-straining via thermal methods is that expansion along a plurality of different axes, such as orthogonal axes, can be achieved. An exemplary elastomeric substrate useful in the method of the present invention is a PDMS substrate having a thickness equal to about 1 mil. The elastic substrate can be pre-strained by expansion along a single axis or by expansion along a plurality of axes. As shown in FIG. 6, at least a portion of the inner surface of the printable semiconductor component is bonded to the outer surface of the pre-strained elastic substrate in an expanded state, and the bonding can be performed by covalent bonding between the inner surfaces of the semiconductor surface. Van der Valli is achieved by using a binder or by any combination of such methods. In an exemplary embodiment of the elastic substrate system PDMS, the support surface of the substrate 1150 175.doc -33- 201042951, which has a plurality of hydroxyl groups extending from its surface to promote ' , covalent bonding of semiconductor structures. Referring again to Figure 6, after bonding the pre-strained elastic substrate to the semiconductor structure, the elastic substrate is allowed to at least partially relax to a relaxed state. In this embodiment, the relaxation of the elastic substrate causes the inner surface of the semiconductor structure to be bent to produce a semiconductor element having a curved inner surface. As shown in FIG. 6, the manufacturing method may optionally include a second transfer step and optionally a bonding step, wherein the transferable semiconductor element 715 having the curved inner surface 72〇 is transferred from the elastic substrate to the other substrate. Preferred is a flexible substrate such as a polymer substrate. This second transfer step can be accomplished by contacting the exposed surface of the semiconductor structure 715 having the curved inner surface 72() with another receiving surface of the substrate bonded to the exposed surface of the semiconductor structure 71 5 . The bonding to the other substrate can be accomplished by any means that at least partially maintains the curved structure of the semiconductor component, including covalent bonds, bonding via van der Waals force, dipole-dipole interaction, London (1^") bond and/or hydrogen bonding. The invention also includes the use of an adhesive layer, coating and/or film provided between the exposed surface and the receiving surface of the transferable semiconductor structure. The extensible semiconductor component of the present invention can effectively integrate a large number of functional devices and device components such as transistors, diodes, lasers, s, MS, LEDS and OLEDS. It is known that rigid inorganic semiconductors have certain functional advantages. First, extended semiconductor components can be flexible and therefore less subject to structural damage caused by buckling, f-bending and/or deformation than conventional rigid bodies. :: 150175.doc -34- 201042951 The "extendable semiconductor component of the present invention, the conventional unstrained just because the curved semiconductor structure can be in a slight mechanical strain ~ to provide a curved inner surface Sex semiconductors can exhibit higher intrinsic field effect migration rates. Finally, because the extensible semiconductor components are free to expand and contract during device temperature cycling, they may provide good thermal properties. Ο ❹ 曰 shows an extendable conductor with a longitudinal alignment of a wavy configuration: an image of the columns: as shown in Figure 7, the semiconductor strips are provided with =: and supported by a single flexible rubber substrate . Figure 8 shows a cross-sectional image of a extendable conductor element of the present invention with a + conductor structure 776 supported by the flexible substrate m. The semiconductor structure 776 of Fig. 8 has an inner surface having a contour shape of a periodic wave. Also shown in Figure 8 is a semi-conductive structure -::;. The periodic wave configuration extends through an array of extendable electronic circuits, devices, and devices that have good performance when extended, flexed, or deformed. Similarly, the present invention provides an extension circuit and an electronic device, and has a support table (4) flexible substrate, the surface: such as a display-wave structure The inner surface of the curve; the device: the line contact. In the r structure arrangement, the device, the device array: at least a part of the structure of the ΐ electric tower structure, the inner surface of the trowel curve is combined with the flexibility. This aspect of the invention Device, device array: multi-component component of the integrated device component of the circuit body. In the example, the switchable circuit, device and the two-layer 150175.doc-35. 201042951 The column comprises a plurality of integrated device components, at least a portion of which has a periodic wave curve structure. In a useful embodiment of the invention, a stand-alone electronic circuit or device comprising a plurality of interconnecting components is provided. One of the inner surfaces is in contact with and at least partially bonded to the pre-strained elastic substrate in an -expanded state. The pre-strain can be achieved by any method known in the art including, but not limited to, rollers And/or pre-bending the elastic substrate and pre-straining the elastic substrate by expansion along a single-axis or by expansion along a plurality of axes. The bonding may be directly by at least a portion of the electronic circuit or device The covalent bond or van der Waals force between the surface and the pre-strained elastic substrate is achieved, or by using an adhesive or an intermediate bonding layer. The pre-strained elastic substrate is combined with the electronic circuit or device. Thereafter, the elastic substrate is allowed to at least partially relax to a bran-reinforcing relaxation, which causes the inner surface of the semiconductor structure to bend. The curvature of the inner surface of the electronic circuit or device produces a curved inner surface, which is Useful embodiments have a periodic or pro-cycle configuration. The invention includes a plurality of embodiments in which all components of the electronic device or circuit are present in a periodic or non-periodic wave group. The period of the device, the device, and the array of devices or the absence of a wave group that obeys the extension or the help of the configuration without creating large strains on the individual components of the circuits or devices. This aspect of the invention The electronic properties of the extendable electronic circuit, device and device array when in a bent, extended or deformed state. The period of the periodic wave configuration formed by the method can be varied as follows: (1) comprising the circuit or device The net thickness of the integrator of the integrated component and (9) the material including the material of the integrated device component such as Young's Money 150175.doc • 36 - 201042951 The mechanical properties of the flexural rigidity. Figure 9A shows the manufacture of the extensible thin film transistor. A flow chart of an exemplary method of arrays. As shown in Figure 9A, an array of free-formable thin film transistors is provided using the techniques of the present invention. An array of thin film transistors is exposed to the same by a dry transfer contact printing method. The inner surface of the crystal is transferred to a PDMS substrate. The exposed inner surface is then contacted with a room temperature cured pre-strained PDMS layer in an expanded state. The pre-strain 1 > 〇 1 ^ 3 layer

之隨後π全固化使該等電晶體之内表面與該預應變pDMS 〇 層結合。允許該預應變PDMS層冷卻且呈現一至少部分鬆 弛狀態。PDMS層之鬆弛將一週期波結構引入該陣列中之 電晶體,進而使得其變為可延伸的。圖9八中之插圖提供藉 由本方法製造之可延伸薄膜電晶體陣列之原子力顯微圖。 該原子力顯微圖展示了在延伸或變形狀態中提供良好電子 效能之週期波結構。 圖9B提供處於鬆弛及延伸組態之可延伸薄膜電晶體陣列 Q 《光學顯微圖。以在該陣列上產生-約2G%之淨應變而不 使該等溥膜電晶體破裂或損傷之方式延伸該陣列。經觀察 自一鬆弛組態至一應變組態之轉換為一可逆過程。圖叩亦 提供針對施加至閘極之若干電位的汲極電流對汲極電壓的 圖,其展示1玄等可延伸薄膜電晶體在拳!弛及延伸組態皆展 示良好效能。 實例1.用於橡膠基板上的高效能電子組件之可延伸形 式之單晶矽 吾人已製造由構造為具有微尺度週期波狀幾何形狀之次 150175.doc -37- 201042951 微米單晶元件組成之可延伸形式㈣。當由—彈性體基板 支樓時’此”波狀,·石夕能可逆地延伸及壓縮至大應變二損 傷石夕。該等波之振幅及週期進行變化以適應此等變形,進 而避免矽自身之顯著應變。與石夕直接整合之介電質、摻雜 劑之圖案、電極及其他元件產生完全形成的、高效能"波 狀”金屬氧化物半導體場效應電晶體、Pn二極體及其他裝 其用於可延4申或壓縮至類似大之應變水準之電子電 電子學之進步主要由為增加電路運算速度及積體密度、 為減少其功率消耗及(對於顯示系統)為使大面積覆蓋成為 可=做出之努力驅使。近來之一方向尋求發展能在具有 哥常外φ尺寸之非習知基板上形成高效能電路的方法及 材料·紙狀顯示器及φ譽搞 及光學知“儀之可撓性塑膠基板、隹平 :陣:之球狀曲線支擇及整合之機器人感測器的保形、皮 …專膜形式製備且放置在薄基板薄片上或基板層積 2中,中性機械平面附近時,許多電子材料能提供良好彎 變二下’該等作用材料在彎曲期間經受之應 變了保持在引發破裂所需之典型位準(約 操作時可撓曲、μ > + 土 田 _或達到極端的彎曲水準之裝置或對於 要灰-Α形包覆於具有複雜、曲線形狀之支撺物的裝置, 統中延伸性’它是一更具挑戰性之特性。在此等系 尤其=路位準之應變可超過幾乎所有已知電子材料, 尤其疋彼等用於p古庙β Α 極限。在某種程声上發展的電子材料,之破裂 ^ ’此問題能以使用可延伸導線來互連 I50175.doc -38- 201042951 由剛性隔離島(isolated island)支撐之電子組件(例如電g 體)之電路來避開。可以此策略獲取有價值之結果,儘: 其最適合可以相對低覆蓋面積之主動電子元件來達成的: 用。吾人報告-不同方法’丨中可延伸性直接以具有微米 級週期、"波"狀幾何形狀之高品質單晶矽薄膜來達成。此 等結構經由波振幅及波長之變化而非經由該等材料自身中 之潛在破壞性應變來適應大壓縮及拉伸應變。將此等可延 ΟSubsequent π full cure combines the inner surface of the transistors with the pre-strained pDMS layer. The pre-strained PDMS layer is allowed to cool and exhibit an at least partially relaxed state. Relaxation of the PDMS layer introduces a periodic wave structure into the transistor in the array, thereby making it extendable. The illustration in Figure 9 provides an atomic force micrograph of an extensible thin film transistor array fabricated by the method. The atomic force micrograph shows a periodic wave structure that provides good electronic performance in an extended or deformed state. Figure 9B provides an extensible thin film transistor array Q in an relaxed and extended configuration. The array is extended in such a manner that a net strain of -2 G% is produced on the array without rupturing or damaging the tantalum film. It is observed that the conversion from a relaxed configuration to a strain configuration is a reversible process. Figure 叩 also provides a plot of the drain current versus the gate voltage for several potentials applied to the gate, which shows a mysterious stretchable thin film transistor in the punch! Both the relaxation and extension configurations show good performance. Example 1. A single crystal of an extensible form of a high performance electronic component for use on a rubber substrate has been fabricated from a sub-150175.doc-37-201042951 micron single crystal element configured to have a micro-scale periodic wavy geometry. Extensible form (4). When it is branched by the elastic substrate, the stone can reversibly extend and compress to the large strain and damage. The amplitude and period of the waves are changed to adapt to the deformation, thereby avoiding the flaw. Significant strain of itself. The dielectric, dopant pattern, electrode and other components directly integrated with Shi Xi produce a fully formed, high-efficiency "wave-like metal oxide semiconductor field effect transistor, Pn diode And other advances in electronic electronics that can be used to extend or compress to a similar strain level are mainly due to increased circuit operation speed and integrated density, to reduce its power consumption and (for display systems) Large-area coverage is driven by the efforts that can be made. Recently, it has been seeking to develop a method and material for forming a high-performance circuit on a non-conventional substrate having a size of φ, a paper-like display, and a flexible plastic substrate, and a flat plastic optical device. : Array: The spherical shape of the spherical sensor and the integrated shape of the robot sensor are prepared and placed on a thin substrate sheet or in the substrate layer 2, near the neutral mechanical plane, many electronic materials Can provide good bending twice. 'The strains experienced by these materials during bending are maintained at the typical level required to initiate cracking (about flexing during operation, μ > + soil field _ or reaching extreme bending levels) The device or the device that is to be covered with a complex, curved shape of the support, is a more challenging feature. In this case, especially the strain of the road can be More than almost all known electronic materials, especially those used in the p-ancient temple β Α limit. The electronic material developed on a certain sound, the cracking ^ 'This problem can be interconnected using an extendable wire I50175.doc -38- 201042951 The circuit of the electronic components (such as the electro-g-body) supported by the isolated island is avoided. This strategy can be used to obtain valuable results: it is best suited for active electronic components with relatively low coverage: We report - different methods 'The extensibility in 丨 is directly achieved with a high quality single crystal germanium film with micron-scale, "wave" geometry. These structures are not affected by wave amplitude and wavelength changes. Adapt to large compression and tensile strains through potentially damaging strains in the materials themselves.

伸"波狀"石夕元件與介電質、摻雜劑之圖案及薄金屬膜整合 可導致高效能、可延伸電子裝置。 圖10表示在彈性體(意即橡膠)基板上波狀單晶矽帶之製 造序列。第一步(頂部框)涉及用以在一絕緣物上矽(s〇i)晶 圓上界定一抗蝕層之光微影術,接著是用以移除頂部矽之 曝露部分的蝕刻。用丙酮移除該抗蝕層且然後以濃縮氫氟 酸蝕刻内埋的Si〇2層使該等帶自下層矽基板釋放。該等帶 之末端連接至該晶圓以防止其在蝕刻劑中被洗離。該等抗 姓線之寬度(5-5 0 μηι)及長度(約15 mm)界定該等帶之尺 寸。SOI晶圓上的頂部矽之厚度(2〇_32〇 ηιη)界定該等帶厚 度。在下一步驟(中間框)中,彈性地延伸一平坦彈性體基 板(聚(二曱基矽氧烷),PDMS ; 1-3 mm厚)且然後使其與該 等帶等形接觸。將該PDMS剝離會使該等帶離開該晶圓且 使該等帶黏結至該PDMS表面。釋放該PDMS中之應變(意 即預應變)導致會引起在該矽及該PDMS表面形成良好界定 之波紋的表面變形。(圖UA及11B)該等起伏輪廓係週期在 5與50 μηι之間且振幅在1〇〇 nm及1.5 μπι之間(視矽之厚度 150175.doc -39- 201042951 及該PDMS中預應變之大小而定)的正弦曲線(頂部框,圖 11C)。對於一給定系統,該等波之週期及振幅在大面積 (若干cm )上均在約5%内。該等帶之間之pDMs的平滑形態 及鄰近帶之波形中不存在相關相表明了該等帶未強力地機 械耦接。圖11C(底部框)展示作為沿該等波狀帶之一者之 距離的函數而量測之81尖峰之微拉曼量測結果。該等結果 提供了對應力分佈之瞭解。 此靜態波狀組態之性質與在一半無限低模數支撐物上之 一均勻、薄高模數層中的起始翹棱幾何形狀之非線性分析 一致: —7th A0=hpil-1 (i) 其中 0.52The extension of the wavy "Shixi component with dielectric, dopant pattern and thin metal film integration results in high performance, extendable electronics. Fig. 10 shows a manufacturing sequence of a corrugated single crystal ruthenium tape on an elastomer (i.e., rubber) substrate. The first step (top box) involves photolithography to define a resist layer on a germanium (s〇i) crystal circle, followed by etching to remove the exposed portion of the top germanium. The resist layer was removed with acetone and then the buried Si 2 layer was etched with concentrated hydrofluoric acid to release the strips from the underlying germanium substrate. The ends of the strips are attached to the wafer to prevent it from being washed away in the etchant. The width of the anti-surname lines (5-5 0 μηι) and the length (about 15 mm) define the dimensions of the bands. The thickness of the top crucible (2〇_32〇 ηιη) on the SOI wafer defines the strip thickness. In the next step (middle frame), a flat elastomeric substrate (poly(dimercaptodecane), PDMS; 1-3 mm thick) is elastically stretched and then brought into contact with the ribbon. Peeling the PDMS causes the strips to leave the wafer and bond the strips to the PDMS surface. Releasing the strain in the PDMS (i.e., pre-strain) results in surface deformation that causes well-defined corrugations on the surface of the crucible and the PDMS. (Figs. UA and 11B) These undulating contour periods are between 5 and 50 μηι and have amplitudes between 1 〇〇 nm and 1.5 μπι (depending on the thickness of 150175.doc -39- 201042951 and pre-straining in the PDMS) The sinusoid of the size (top box, Figure 11C). For a given system, the period and amplitude of the waves are within about 5% over a large area (several cm). The smooth morphology of the pDMs between the bands and the absence of correlation in the waveforms of the adjacent bands indicate that the bands are not strongly mechanically coupled. Figure 11C (bottom frame) shows the micro-Raman measurement of the 81 spikes measured as a function of the distance along one of the undulating bands. These results provide an understanding of the stress distribution. The nature of this static wavy configuration is consistent with the non-linear analysis of the initial warp geometry in a uniform, thin, high modulus layer on a half infinitely low modulus support: —7th A0=hpil-1 (i) 0.52

E 2/3E 2/3

PDMS PDMS, 係翹棱之臨界應變,ε 係預應 變之位準,係波長且&係振幅。柏松比係ν,揚氏模數係 Ε,且該等下標指si或pDMS之性質。矽之厚度係h。此處 理涵蓋了製造成之波狀結構之許多特徵。舉例而言,圖 ΠΕ)展示當該預應變值固定時(約為此等資料之〇 9%),波 長及振幅皆線性地視Si厚度而定。波長不取決於預應變之 位準(圖12)。此外,使用Si&PDMS之機械性質之文獻值 (ESi-13〇Gpa、EPDMS=2MPa、vsi=0.27、vPDMS=〇.48)之計算 產生在量測得的值的約1〇%(最大偏差)範圍内之振幅及波 長 可應變"由該等帶之有效長度(由波長確定)與其實際 150175.doc •40- 201042951 長度(由透過AFM量測之表面距離確定)的比例來計算,且 產生近似等於該PDMS中預應變之值(對於高達約3 5%之預 應變)。石夕自身中之應變峰值(意即最大值)(吾人稱為石夕應 變)係由帶厚度及在應變區中根據M/2(K係曲率)的在該等 波之極限處之曲率半徑估算得,在該等應變區中該等波存 在且臨界應變(對於此處之情況,約為0.03%)與跟彎曲相 關的應變峰值相比較小。對於圖u之資料,該等石夕應變峰 值為約〇.36(±0.08)% ’其比帶應變小兩倍以上。此矽應變 〇 對於給定預應變下的所有帶厚度為相㈣⑷3)。所得機 械優勢(其中該石夕應變峰值大大小力帶應變)對於達成可延 伸性至關重要。吾人注意到在蒸鍍或旋塗至pDMs上之金 屬及介電質中亦已觀察到翹棱薄膜(與如本文所述之預成 型、經轉移之單晶元件及裝置形成對比)。 在製造之後該等波狀結構對施加至彈性體基板之壓縮及 拉伸應變的動態回應對可延伸電子裝置最重要。為揭示此 〇 過程之機理,當力被施加至PDMS以在與該等帶的長維平 行的方向上壓縮或延伸1>]0“8時,吾人藉由AFM量測波狀 Si帶之幾何形狀。歸因於柏松效應,此力產生沿該等帶及 與其垂直方向上之應變。該等垂直應變主要導致該等帶之 間之區域中的PDMS的變形。另一方面,沿該等帶之應變 是由該等波之結構的變化來適應。圖14A中之三維高度影 像及表面輪廓呈現代表性的壓縮、未受力及延伸狀態(自 該樣品上輕微不同之位置處收集)。在此等及其他情況 下,該等帶在變形期間保持其正弦(圖14A之右邊框中的 I50175.doc •41 - 201042951 線)形狀,其中波結構的大約一半位於如由該等帶之間的 區域界定之PDMS表面的未受力位置之下(圖15)。圖14B展 示相對於該未受力狀態(零)之壓縮(負)及拉伸(正)施加之應 變的波長及振幅。該等資料對應於自每點處大量(>5〇)帶 收集之平均的AFM量測結果。所施加的應變由該Pdms基 板之所量測的末端間尺寸變化確定。藉由AFm之直接表面 量測連同由該等正弦波形估算得之圍線積分展示了所施加 的應變等於此處檢查之情況之帶應變(圖16)。(在比該預應 變減去該臨界應變更大之拉伸應變處持續之小振幅(<5 〇 nm)波可由在該初始翹棱過程期間Si之輕微滑動而導致。 在此小(或零)振幅區中計算得之矽應變峰值及帶應變低於 實際值。)有趣地是,該等結果指示了該等波狀帶對於所 施加應變有兩種不同實體回應。處於緊張狀態時,該等波 以一非直觀方式演變:波長不隨所施加應變而明顯變化, 從而與翹棱後機理一致。相反,振幅之變化適應該應變。 在此狀態中,矽應變隨著延伸該pDMS而變小;當所施加 應變等於該預應變時其達到〜〇%。相反’在壓縮時,隨著 ◎ 增加所施加應變,該等波長減少且振幅增加。此機械回應 與一手風琴風箱之機械回應類似,其與拉緊時之特性有本 質的不同。在壓縮期間,歸因於波峰及波谷處之曲率半徑 之減】石夕應變隨著所施加應變增加而增加。然而,石夕應 變之增加速率及大小皆遠低於帶應變,如圖14B所示。此 機理使可延伸性成為可能。 與波狀幾何形狀一致之應變範圍中的完全回應可藉由給 150175.doc -42· 201042951 出波長λ對其在初始翹棱狀態中之值λ0,及所施加應變 〜的相依性之方程式來定性地描述: λ={^ 對於拉伸 _U(1+。㈣)對於壓縮 舉例而言,此拉緊/壓縮不對稱可由在壓縮期間形成之 該PDMS及Si之上升區域之間的輕微可逆間隔所產生。對 於此情況,連同對於未呈現此不對稱性質之系統,拉緊及 壓縮之波振幅A皆由對於適度應變(<1〇-15%)有效的單一陳 述式給出:PDMS PDMS, the critical strain of the ridge, the level of the ε system pre-deformation, the wavelength and the amplitude of the system. The cypress ratio is ν, the Young's modulus is Ε, and the subscripts refer to the properties of si or pDMS. The thickness of 矽 is h. Here are a number of features that are fabricated into wavy structures. For example, Figure 展示 shows that when the pre-strain value is fixed (about 9% of this data), the wavelength and amplitude are linearly dependent on the Si thickness. The wavelength does not depend on the level of the pre-strain (Figure 12). In addition, the calculation of the literature values (ESi-13〇Gpa, EPDMS=2MPa, vsi=0.27, vPDMS=〇.48) using the mechanical properties of Si&PDMS yields approximately 1% of the measured value (maximum deviation) The amplitude and wavelength of the range can be calculated from the ratio of the effective length of the bands (determined by the wavelength) to the actual length of 150175.doc •40- 201042951 (determined by the surface distance measured by AFM), and A value approximately equal to the pre-strain in the PDMS is generated (for pre-strain up to about 35%). The peak of the strain in Shi Xi itself (meaning the maximum value) (I call it Shi Xi strain) is the radius of curvature of the band at the limit of the wave according to M/2 (K-curvature) in the strain zone. It is estimated that the equipotential presence and critical strain (about 0.03% for the case herein) in these strain zones is small compared to the strain peak associated with bending. For the data of Fig. u, the peak value of these Shishi strains is about 〇.36 (±0.08)%' which is more than twice the strain of the belt. This strain 〇 is the phase (4) (4) 3 for all strip thicknesses given a pre-strain. The resulting mechanical advantage (where the Shishi strain peak is large and the force is strained) is critical to achieving stretchability. We have observed that warped films have also been observed in metals and dielectrics that are either evaporated or spin-coated onto pDMs (as opposed to preformed, transferred single crystal elements and devices as described herein). The dynamic response of the wavy structures to compression and tensile strain applied to the elastomeric substrate after manufacture is of the utmost importance to the extendable electronics. To reveal the mechanism of this enthalpy process, when force is applied to the PDMS to compress or extend 1>]0"8 in a direction parallel to the long dimension of the bands, we measure the geometry of the wavy Si band by AFM. Shape. Due to the cypress effect, this force produces strain along the zones and perpendicular thereto. These vertical strains primarily cause deformation of the PDMS in the region between the zones. The strain of the strip is adapted by the change in the structure of the waves. The three-dimensional height image and surface profile in Figure 14A exhibit representative compression, unstressed, and extended states (collected from slightly different locations on the sample). In these and other instances, the strips maintain their sinusoidal shape (I50175.doc • 41 - 201042951 lines in the right frame of Figure 14A) during deformation, wherein approximately half of the wave structure is located between the bands The area defines the unstressed position of the PDMS surface (Fig. 15). Fig. 14B shows the wavelength and amplitude of the strain applied to the compression (negative) and tensile (positive) of the unstressed state (zero). This information corresponds to every point A large number (>5〇) with the collected average AFM measurement results. The applied strain is determined by the measured end-to-end dimensional change of the Pdms substrate. Direct surface measurement by AFm along with the sinusoidal waveform The estimated perimeter integral shows the strain applied equal to the strain measured here (Figure 16). (Small amplitude sustained at the tensile strain greater than the pre-strain minus the critical strain (&lt The ;5 〇nm) wave can be caused by a slight slip of Si during the initial warping process. The peak strain and band strain calculated in this small (or zero) amplitude region are lower than the actual value.) Interestingly, The results indicate that the undulations have two different physical responses to the applied strain. In a state of tension, the waves evolve in a non-intuitive manner: the wavelength does not change significantly with the applied strain, and thus The post-mechanism is consistent. Conversely, the change in amplitude adapts to the strain. In this state, the 矽 strain becomes smaller as the pDMS is extended; when the applied strain is equal to the pre-strain it reaches ~〇%. Conversely, when compressed, along with ◎ Increase the applied strain, the wavelength decreases and the amplitude increases. This mechanical response is similar to the mechanical response of an accordion bellows, which is essentially different from the characteristics of the tension. During compression, due to peaks and troughs The radius of curvature is reduced. The Shishi strain increases with the strain applied. However, the rate and magnitude of the increase of the Shishi strain are much lower than the strain, as shown in Fig. 14B. This mechanism makes the extensibility possible. The complete response in the strain range consistent with the wavy geometry can be obtained by giving the equation 150517.doc -42· 201042951 the value of the wavelength λ in the initial ridge state λ0 and the dependence of the strain applied. Qualitative description: λ={^ For stretching _U(1+. (d)) For compression, for example, this tension/compression asymmetry can be produced by a slight reversible interval between the PDMS and the rising region of Si formed during compression. For this case, as well as for systems that do not exhibit this asymmetrical nature, the wave amplitude A of the tension and compression is given by a single statement valid for moderate strain (<1〇-15%):

S appliedS applied

(3) 其中係對應於該初始翹棱狀態之值。如圖丨4A所示, 此等陳述式獲得與實驗的數量一致,而無任何參數擬合。 當適應該拉伸/壓縮應變之波狀起伏保持時,矽應變峰值 由該彎曲條件控制且由(33)給出(3) Where is the value corresponding to the initial ridge state. As shown in Figure 4A, these statements are obtained consistent with the number of experiments without any parameter fit. When the undulation of the tensile/compressive strain is maintained, the 矽 strain peak is controlled by the bending condition and is given by (33)

= 2sc= 2sc

* applied (4) 其與圖14B中由曲率量測之應變十分一致。(亦參看圖 18)。此分析陳述式有助於界定該系統能承受而不使矽破 裂之所施加應變之範圍。對於〇,9%之預應變,若假設碎失 效應變為約2%(對於壓縮或者拉伸),則此範圍為_27% t〇 2.9%。控制預應變之位準允許將此應變範圍(意即接近 3 0%)用以平衡壓縮與拉伸變形的所要程度。舉例而言,一 3.5%之預應變(所檢查之最大值)產生_24%仂55%的範 150175.doc -43- 201042951 圍。吾人注意到此等計算假設甚至在極端的變形水準下所 施加應變也等於帶應變。在實驗上,吾人發現歸因於在該 等帶之末端料及該等帶之間用以適應應變以使得所施加 應變不被完全轉移至該等帶的PDMS之能力,此等估算結 果通常被超過。* applied (4) This is in good agreement with the strain measured by curvature in Figure 14B. (See also Figure 18). This analytical statement helps define the range of strains that the system can withstand without breaking the raft. For helium, a pre-strain of 9%, if the shatter-loss effect is assumed to be about 2% (for compression or stretching), the range is -27% t〇 2.9%. Controlling the level of pre-strain allows this strain range (ie close to 30%) to balance the desired degree of compression and tensile deformation. For example, a 3.5% pre-strain (the maximum value checked) yields a range of _24% 仂 55% of the range 150175.doc -43- 201042951. We have noticed that these calculations assume that the strain applied even at extreme deformation levels is equal to the strain. Experimentally, we have found that these estimates are often exceeded due to the ability to adapt the strain between the end materials of the belts and the belts so that the applied strain is not completely transferred to the PDMS of the belts. .

吾人已藉由在製造序列(圖10,頂部框)之開始包括額外 之步驟來使用習知處理技術界定矽中摻雜劑的圖案、薄金 屬觸點及介電層而建立功能性、可延伸裝置。以此方式製 造之兩個及三個端子裝置、二極體及電晶體分別提供具有We have established functionality and extendability by including additional steps in the fabrication sequence (Fig. 10, top box) to define patterns, thin metal contacts and dielectric layers of dopants in germanium using conventional processing techniques. Device. The two and three terminal devices, the diodes and the transistors fabricated in this manner are respectively provided with

進階功能性之電路的基礎建構區塊。#中整合之帶裝置首 先被自SOI起離至一未變形醜8板上且然後至一預應變 PDMS基板之雙重轉移過程可建立波狀裝置,其具有經曝 露以用於探測的金屬觸點。圖17A及nB展示針對施加至 PDMS之各種位準之應變的_可延伸pn接面二極體之光學 〜像及電回應。吾人發現在具有延伸或壓縮之裝置的電性 質中沒有在資料之散佈範圍中的系統變化。該等曲線中之 偏差主要歸因於探針觸點之品質之變化。此等卯接面二極 體除作為普通整流裝置之外可用作測器(處於相反 偏壓狀態)或用作光伏打裝置。光電流密度在約]V之反向 偏壓夺為35 mA/em。在正向偏壓’短路電流密度及開 路電麗分別為約17 mA/em2及Q 2 v,其產生㈢之填充因 子。回應之形狀與模型化(圖17B中之實線)一致。裝置性 質即使在約_個壓縮、延伸及釋放週期之後亦未顯著變 化19) _ 17C展不—可延伸、波狀石夕肖特基障壁金屬 150175.doc -44 - 201042951 氧化物半導體場效應電晶體(M〇SFET)之電流-電壓特性, 該MOSFET是藉由與用於pn二極體之程序類似的程序且藉 由作為閘極介電質(33)之熱Si〇2之整合薄層(4〇 nm)形成。 由對此波狀電晶體之電學量測而擷取之裝置參數(線形範 圍遷移率約100 cm2/Vs(可能限於觸點)、臨限電壓約_3 v) 可與使用相同處理條件在SOI晶圓上形成的裝置之裝置參 數相比較。(圖20及21)。如在pn二極體中,此等波狀電晶 體能可逆地延伸及壓縮至大應變位準而不損傷該等裝置或 〇 顯著改變電性質。在二極體及電晶體中,在該等裝置之末 端以外的PDMS之變形導致比所施加應變更小的裝置(帶) 應變。總體可延伸性由裝置可延伸性及此等類型之pDMs 變开> 之組合效應導致。在比此處檢查之壓縮應變更大之壓 縮應變下,PDMS傾向於以一使得探測變得困難的方式彎 曲。在更大之拉緊應變下,視矽厚度、帶長度及石夕與 PDMS之間結合的強度而定,該等帶破裂、抑或滑動且保 持完整。 〇 此等可延伸矽MOSFET及pn二極體僅表示可形成之許多 類型"波狀"電子裝置中之兩種。完整電路薄片或薄矽板亦 可被結構化為單轴或雙軸可延伸波狀幾何形狀。除了波狀 裝置之惟一機械特性以外’會在許多半導體中產生的應變 與電子特性的叙合亦提供了設計可利用應變中之機械可調 節、週期性變化以達成不同尋常之電子回應之裝置結構的 機會。 材料及方法 150175.doc • 45- 201042951 樣品製備:由Si基板(Soitec公司)上的Si02(145 nm、145 nm、200 nm、400 nm、400 nm或 1 μιη之厚度)上的 Si(20、 50、100、205、290或320 nm之厚度)組成之絕緣物上石夕 (SOI)晶圓。在一種狀況下,吾人使用Si(Shin-Etsu)上的 Si(約2.5 μιη之厚度)及Si02(約1.5 μιη之厚度)之SOI晶圓。 在所有狀況下,摻雜硼(p型)或磷(η型)之頂部Si層具有在5 至20 Hem之間的電阻率。此等SOI晶圓之頂部Si以光阻劑 (AZ 52 14光阻劑,Karl Suss MJB-3接觸遮罩對準器)圖案 化且經反應性離子蝕刻(RIE)以界定Si帶(5〜50 μπι寬,15 mm長)(PlasmaTherm RIE,SF6 40sccm,50mTorr,100W)。 藉由在HF(49%)中底切蝕刻來移除該8丨〇2層,該蝕刻時間 主要視Si帶之寬度而定。橫向蝕刻速率通常為2至3 μιη/min。藉由將基底與固化劑以丨〇 : 1之重量比例混合且 在70°C下固化>2小時或在室溫下固化> 12小時來準備聚(二 甲基矽氧烷)(PDMS)彈性體(Sylgard 184, Dow Corning)之 板。 將此等PDMS平板(1至3 mm之厚度)與已蝕刻SOI晶圓上 之Si共形接觸以產生該等波狀結構。可使用在此接觸之前 建立该PDMS之受控膨脹、繼之以在自晶圓移除後收縮的 任何方法。吾人檢查三種不同技術。在第一種技術中,在 接觸该SOI基板之後對PDMS2機械輥軋建立該等預應變。 儘管波狀結構可以此方式形成’但是其傾向於具有非均勻 的波週期及振幅。在第二種技術中,在接觸之前將該 PDMS(熱膨脹係數=3 1χ1〇_4 K-I}加熱至3(Γ(:與18〇艽之間 150175.doc -46 - 201042951 的溫度且然後在自該SOI移除後將其冷卻,其以一高度可 重現的方式在大面積上產生具有良好均勻性之波狀Si結 構。以此方法,吾人藉由改變溫度來準確地控制PDMS中 預應變位準(圖12)。第三種方法使用在與SOI接觸之前用 機械台延伸且接著在移除之後實體地釋放之PDMS。與熱 學方法類似,此方法允許有良好均勻性及重現性,但與該 熱學方法相比更難以精細地調節預應變位準。 對於諸如pn接面二極體及電晶體之裝置,電子束蒸鍍 〇 (Temescal BJD1800)且光微影圖案化(經由蝕刻或起離)的 金屬層(Al、Cr、Au)充當觸點及閘極。將旋塗摻雜劑 (SOD)(對於 p型,B-75X,Honeywell,USA ;對於 η型, Ρ509,Filmtronics,USA)用於摻雜矽帶。首先將該等SOD 材料旋塗(4000 rpm,20 s)至預圖案化SOI晶圓上。藉由電 漿增強化學氣相沈積(PECVD)(PlasmaTherm)製備之二氧化 矽層(3 00 nm)用作該SOD之遮罩。在950°C加熱10秒之後, 使用6:1之缓衝氧化物蝕刻劑(BOE)蝕刻掉SOI晶圓上之 ❹ SOD與遮罩層。對於電晶體裝置,熱生長(藉由爐中之高 純度氧氣流乾式氧化至25 nm與45 nm之間的厚度, 1100°C,10〜20分鐘)之二氧化矽提供閘極介電質。在完成 該SOI基板上的所有裝置處理步驟之後,藉由光阻(AZ52 14 或Shipley S181 8)來覆蓋具有整合之裝置結構之Si帶(通常 50 μιη寬,15 mm長)以在下層Si02之HF蝕刻期間保護該裝 置層。在藉由氧電漿移除該光阻層之後,將無任何預應變 之平坦PDMS(70°C,>4小時)板用於自處於平坦幾何形狀 150175.doc -47- 201042951 的SOI基板移除該等帶裝置。然後將部份固化的pDMS(在 將基底與固化劑混合之後在室溫下>12小時)板與該完全固 化PDMS板上的该荨si帶裝置接觸。完成該部份固化pDMs 之固化(藉由在70°C加熱),接著移除此板,將該等裝置自 該第一 PDMS板轉移至該新pdmS基板。與冷卻至室溫相關 聯之收縮會建立一預應變,使得移除及釋放建立波狀裝 置,同時電極被曝露以用於探測。 量測:將原子力顯微圖(AFM)(DI_31〇〇,Veec〇)用以精 確地量測該等波性質(波長、振幅)。自所獲得之影像,量 測且統计地分析沿该波狀S i之截面輪廓。使用一自製延伸 台、以及AFM及半導體參數分析器(Agiient,5155c)來量 測波狀Si/PDMS之機械及電回應。藉由J〇bin γν〇η HR 8〇〇 光譜分析器使用來自He-Ne雷射之632.8 nm的光執行拉曼 量測。沿該波狀Si以1 μηι間隔量測該拉曼光譜,其中在沿 該等結構之長度的每一位置處調整焦點以最大化訊號。所 量測光譜藉由洛仁子函數來擬合以定位尖峰波數。歸因於 尖峰波數對顯微鏡之聚焦位置之輕微依賴,拉曼結果僅提 供對應力分佈的定性瞭解。 圍線長度、帶應變及矽應變之計算:該等實驗結果展 不,對於此處探究之材料及幾何形狀範圍,波狀si的形狀 可準確地用簡單正弦函數(意即,y=Asin(kx)(k=27l/?i))來表 示。然後來計算該圍線長度。 |λ—l| 卜 使用ε_ λ來汁算波狀Si之帶應變。石夕應變峰值在該等 波之波峰及波谷處產生,且使用來計算,其中h為 150175.doc -48· 201042951The basic building block of the advanced functional circuit. The #integrated tape device is first separated from the SOI to an undeformed ugly 8 plate and then to a pre-strained PDMS substrate for a dual transfer process to create a wavy device with exposed metal contacts for probing . Figures 17A and nB show the optical ~ image and electrical response of the _ extensible pn junction diode applied to various levels of PDMS. We have found no systematic changes in the spread of data in the electrical properties of devices with extension or compression. The deviations in these curves are primarily due to changes in the quality of the probe contacts. These splicing diodes can be used as detectors (in opposite bias states) or as photovoltaic devices in addition to conventional rectifying devices. The photocurrent density is about 35 mA/em in the reverse bias of about [V]. The forward biased 'short current density and open circuit current are about 17 mA/em2 and Q 2 v, respectively, which produces a fill factor of (3). The shape of the response is consistent with the modeling (solid line in Figure 17B). The nature of the device does not change significantly even after about _ compression, extension and release cycles. 19) _ 17C exhibits no-extensible, wavy Schottky barrier metal 150175.doc -44 - 201042951 Oxide semiconductor field effect electricity Current-voltage characteristics of a crystal (M〇SFET), which is a thin layer of thermal Si〇2 by a procedure similar to that used for a pn diode and by a gate dielectric (33) (4〇nm) formation. The device parameters extracted from the electrical measurements of this wavy transistor (linear range mobility of approximately 100 cm2/Vs (possibly limited to contacts), threshold voltage approx. _3 v) can be used with the same processing conditions in SOI The device parameters of the devices formed on the wafer are compared. (Figures 20 and 21). As in pn diodes, such wavy electromorphs can reversibly extend and compress to large strain levels without damaging the devices or 显 significantly altering electrical properties. In the diode and the transistor, the deformation of the PDMS other than the end of the devices causes strain (device) strain that is less than the applied change. The overall extensibility is caused by the combined effect of device extensibility and the opening of these types of pDMs. At compressive strains greater than the compressive strain examined here, PDMS tends to bend in a manner that makes detection difficult. At greater tensile strains, depending on the thickness of the crucible, the length of the strip, and the strength of the bond between the stone and the PDMS, the strips are broken, or slipped and remain intact. 〇 These extendable MOSFETs and pn diodes represent only two of the many types of "waves" electronic devices that can be formed. The complete circuit sheet or web can also be structured into a uniaxial or biaxial extendable wavy geometry. In addition to the unique mechanical properties of the wavy device, the combination of strain and electronic properties that can occur in many semiconductors also provides a device structure that can be designed to take advantage of mechanically adjustable, periodic variations in strain to achieve an unusual electronic response. chance. Materials and Methods 150175.doc • 45- 201042951 Sample Preparation: Si (20, SiO 2 (145 nm, 145 nm, 200 nm, 400 nm, 400 nm, or 1 μηη thickness) on a Si substrate (Soitec) On-insulator (SOI) wafers consisting of 50, 100, 205, 290 or 320 nm thickness. In one case, we used an SOI wafer of Si (about 2.5 μm thick) and SiO 2 (about 1.5 μm thick) on Si (Shin-Etsu). In all cases, the top Si layer doped with boron (p-type) or phosphorous (n-type) has a resistivity between 5 and 20 Hem. The top Si of these SOI wafers is patterned with a photoresist (AZ 52 14 photoresist, Karl Suss MJB-3 contact mask aligner) and reactive ion etching (RIE) to define the Si band (5~ 50 μπι wide, 15 mm long) (PlasmaTherm RIE, SF6 40 sccm, 50 mTorr, 100 W). The 8 丨〇 2 layer was removed by undercut etching in HF (49%), which was mainly determined by the width of the Si band. The lateral etch rate is typically 2 to 3 μηη/min. Preparation of poly(dimethyloxane) by mixing the substrate with a curing agent in a weight ratio of 丨〇: 1 and curing at 70 ° C for > 2 hours or at room temperature for > 12 hours (PDMS) ) A board of elastomer (Sylgard 184, Dow Corning). These PDMS plates (thickness of 1 to 3 mm) are conformally contacted with Si on the etched SOI wafer to create the wavy structures. Any method of establishing controlled expansion of the PDMS prior to this contact, followed by shrinkage after removal from the wafer, can be used. We check three different technologies. In the first technique, the pre-strain is established for mechanical rolling of PDMS2 after contacting the SOI substrate. Although the wavy structure can be formed in this manner', it tends to have a non-uniform wave period and amplitude. In the second technique, the PDMS (thermal expansion coefficient = 3 1χ1〇_4 KI} is heated to 3 (Γ with a temperature of 150175.doc -46 - 201042951 and then between 18〇艽 and then at 18自) The SOI is cooled after it is removed, which produces a wavy Si structure with good uniformity over a large area in a highly reproducible manner. In this way, we accurately control the pre-strain in PDMS by changing the temperature. Level (Figure 12). The third method uses PDMS that is extended with a mechanical table prior to contact with the SOI and then physically released after removal. Similar to thermal methods, this method allows for good uniformity and reproducibility. However, it is more difficult to finely adjust the pre-strain level than the thermal method. For devices such as pn junction diodes and transistors, electron beam evaporation Te (Temescal BJD1800) and photolithographic patterning (via etching or The metal layer (Al, Cr, Au) acts as a contact and a gate. Spin-on dopant (SOD) will be applied (for p-type, B-75X, Honeywell, USA; for n-type, Ρ509, Filmtronics, USA) for doping the anthracene tape. First, the SOD material is spin coated (4000 Rpm, 20 s) onto the pre-patterned SOI wafer. A cerium oxide layer (300 nm) prepared by plasma enhanced chemical vapor deposition (PECVD) (PlasmaTherm) was used as the mask for the SOD. After heating for 10 seconds at °C, a 6:1 buffered oxide etchant (BOE) is used to etch away the SOD and mask layers on the SOI wafer. For the transistor device, thermal growth (by high purity in the furnace) Oxygen is dry-oxidized to a thickness between 25 nm and 45 nm, and 1100 ° C, 10 to 20 minutes) of erbium oxide provides a gate dielectric. After all device processing steps on the SOI substrate are completed, A photoresist (AZ52 14 or Shipley S181 8) is used to cover the Si tape (usually 50 μm wide, 15 mm long) with an integrated device structure to protect the device layer during HF etching of the underlying SiO 2 . After the photoresist layer, a flat PDMS (70 ° C, > 4 hour) plate without any pre-strain was used to remove the tape device from the SOI substrate in the flat geometry 150175.doc -47 - 201042951. The partially cured pDMS (at room temperature > 12 hours after mixing the substrate with the curing agent) is then used. Contacting the 荨si tape device on the fully cured PDMS board. Finishing the curing of the partially cured pDMs (by heating at 70 ° C), then removing the plate, transferring the devices from the first PDMS plate to The new pdmS substrate. The shrinkage associated with cooling to room temperature establishes a pre-strain that causes the removal and release to establish a wavy device while the electrodes are exposed for detection. Measurement: An atomic force micrograph (AFM) (DI_31〇〇, Veec〇) was used to accurately measure the properties of the waves (wavelength, amplitude). From the acquired image, the cross-sectional profile along the undulating S i is measured and statistically analyzed. The mechanical and electrical response of the wavy Si/PDMS was measured using a self-contained extension station and AFM and a semiconductor parameter analyzer (Agiient, 5155c). Raman measurements were performed using a J〇bin γν〇η HR 8〇〇 spectral analyzer using 632.8 nm light from a He-Ne laser. The Raman spectrum is measured along the wavy Si at intervals of 1 μm, wherein the focus is adjusted at each position along the length of the structures to maximize the signal. The measured spectrum is fitted by the Loren subfunction to locate the peak wavenumber. Due to the slight dependence of the peak wavenumber on the focus position of the microscope, the Raman results only provide a qualitative understanding of the stress distribution. Calculation of the length of the line, the strain of the belt and the strain of the enthalpy: The results of these experiments are not shown. For the range of materials and geometric shapes explored here, the shape of the wavy si can be accurately approximated by a simple sine function (ie, y=Asin( Kx) (k=27l/?i)) is expressed. Then calculate the length of the fence. |λ—l| 卜 Use ε_ λ to calculate the strain of the wavy Si. The peak value of the Shixi strain is generated at the peaks and troughs of the equal waves and is used to calculate, where h is 150175.doc -48· 201042951

Si厚度,且义係波峰或波谷處之曲率半徑,其由 y' 給出,其中η係一整數且丫”係丫關於χ的 導 數H亥實際形狀之正弦函數近❿,石夕應'變峰值由 epeak __ AilThe thickness of Si, and the radius of curvature at the peak or trough of the singularity, which is given by y', where η is an integer and 丫" 丫 丫 丫 丫 导 导 导 H H H H H 石 石 石 石 石 石 石 石 石Peak by epeak __ Ail

Si = —p—給出。圖12展示作為用以建立該預應變之溫度 之函數的波長。如圖13展示,歸因於波振幅及波長對厚度 之線形相依性〜/2 , λ~;〇,該應變峰值獨立於Si厚度。圖 15展示了波狀結構包含相對於該等帶之間之pDMs表面的Si = —p—is given. Figure 12 shows the wavelength as a function of the temperature at which the pre-strain is established. As shown in Fig. 13, the strain peak is independent of the Si thickness due to the wave amplitude and the linear dependence of the wavelength on the thickness /2, λ~; Figure 15 shows that the wavy structure contains the surface of the pDMs relative to the bands

水平面的幾乎相向上及向下移位。石夕帶應變等於此處 檢查之系統之所施加應變(圖16)。 一手風琴風箱模型:當在壓縮時矽可與PDMS分離時, 系統由手風琴風箱機理而非翹棱機理支配。在該風箱狀況 下’所施加之壓縮應變(sapplied)之波長為、(1,其 中λ為無應變組態中的波長,如方程式所描述。因為矽 帶之圍線長度在壓縮應變之前及之後近似相同,吾人可使 用以下關係式來確定波振幅Α。The horizontal plane is displaced almost upwards and downwards. The Shixi belt strain is equal to the strain applied by the system examined here (Figure 16). One accordion bellows model: When 矽 can be separated from PDMS during compression, the system is dominated by the accordion bellows mechanism rather than the ribbing mechanism. The wavelength of the applied compressive strain (sapplied) in the case of the bellows is (1, where λ is the wavelength in the unstrained configuration, as described by the equation. Because the length of the encircling line is before the compressive strain and After approximately the same, we can use the following relationship to determine the wave amplitude Α.

A0sin~x . λΛ 1 + A sin 2π λ〇(1 + εφ_) x dx 此方程式對於具有漸近解α = 7ϊ^^|α#-Ιι2^ι。 在小壓縮應變下,此方程式簡化為方程式(3),其亦適用於 Si與POMS之分離係不可能的情況,且該體系遵循翹棱機 理。矽應變峰值由 2ε, —c pre applied ^applied 7 給出。對於中 度壓縮應變’此陳述式近似與方程式(4)相同。在施加中度 150175.doc •49- 201042951 應變的界限内,與波振幅類似,矽應變峰值對於該風箱模 型及該翹棱模型具有類似函數形式。圖18展示根據以上陳 述式及根據方程式(4)計算之應變峰值。 裝置特徵化··將半導體參數分析器(Agilent,5155〇及 習知探測台用於該等波狀pn接面二極體及電晶體之電學特 徵化Pn—極體之光回應在約1 W/cm2之照度下量測,如 藉由一光學功率計(〇phir 〇ptr〇nics公司,Laser p〇werA0sin~x . λΛ 1 + A sin 2π λ〇(1 + εφ_) x dx This equation has an asymptotic solution α = 7ϊ^^|α#-Ιι2^ι. At small compressive strains, this equation is reduced to equation (3), which is also applicable to the case where the separation of Si and POMS is not possible, and the system follows the warping mechanism. The 矽 strain peak is given by 2ε, —c pre applied ^applied 7 . For the medium compressive strain, this statement is approximately the same as equation (4). Within the limits of the applied medium 150175.doc •49- 201042951 strain, similar to the wave amplitude, the 矽 strain peak has a similar functional form for the bellows model and the warping model. Figure 18 shows the strain peaks calculated according to the above formula and according to equation (4). Characterization of the device · A semiconductor parameter analyzer (Agilent, 5155 〇 and a conventional probe station for the undulating pn junction diode and the electrical characteristic of the transistor Pn-pole body light response at about 1 W Measurement under illumination of /cm2, such as by an optical power meter (〇phir 〇ptr〇nics, Laser p〇wer

Meter AN/2)來量測。吾人使用機械台在延伸及壓縮期間及 之後來量測該等裝置。作為探究該過程之可逆性的方法, 吾人在約100個壓縮(至約5%應變)、延伸(至約丨5%應變)及 釋放週期之前及之後在環境光下量測三個不同pn二極體。 圖19展不結果。圖2G及21展示來自波狀電晶體之影像、示 意性說明及裝置量測結果。 實例2:用於彈性體基板上的高效能電子電路之翹棱及 波狀GaAs帶 製造厚度在次微米範圍内且具有良好界定的、"波狀"及/ 或翹棱幾何形狀之單晶GaAs帶。位於一彈性體基板之表 面上或嵌入一彈性體基板中之所得結構展示達到>1〇%之 應變的可逆延伸性及壓縮性,比GaAs自身的可逆延伸及壓 縮應變大十倍以上。藉由在此等結構之恤帶上整合歐姆 及肖特基觸點’可達成高效能可延伸電子裝置(例如金屬 半導體場效應電晶體)。此類電子系統可單獨使用或與類 似設計之⑦、介電質及/或金屬材料組合使用,以形成用 於要求高頻率運作以及可延伸性、極端可撓性或鮮有複 150175.doc -50- 201042951 雜曲線形狀之表面相符的能力之應用的電路。 在傳統微電子學中,主要根據速度、功率效率及整合層 級^量測效能能力。而在其他更新的電子裝置形態_的^ 步是由在非習知基板(例如低成本塑膠、箱、紙)上達成整 合或覆蓋大面積之能力所驅動的。舉例而言,藉由等形地 包裹身體以數位地將所要組織成像之大面積成像器可達成 新形式的X射線醫療診斷。可在多種表面及表面形狀上展 肖之輕重!、牆壁尺寸之顯示器或感測器提供了用於建築 S計之新技術。已探究包括小有機分子、聚合物、非晶系 石夕、多晶石夕、單晶石夕奈米線及微結構帶之各種材料,以充 當可支援此等及其他應用之類型的薄膜電子裝置的半導體 通f。此等材料使具有跨越一廣泛範圍(意即自10_5至500 cm /V’s)之遷移率及在可撓性基板上呈可機械彎曲薄膜形 態之電晶體成為可能。諸如大孔徑干涉合成孔徑雷達 (InSAR)及射頻(RF)監視系統之要求高速運作之應用要求 〇 具有很高遷移率的半導體,諸如GaAs,或InP等等。單晶 複合物半導體之脆弱性產生若干必須克服之製造挑戰以便 製造具有該等半導體的高速、可撓性電晶體。吾人藉由使 用自同。口質塊晶圓建立之印刷GaAs線陣列來於塑膠基板上 建構金屬半導體場效應電晶體(MESFET)而建立一實際方 法。此等裝置即使在中等規模裝置(例如微米閘長度)中亦 展示良好機械可撓性及接近2 GHz之fT.。此實例展示基於 GaAs v之MESFET(與線裝置相反),其經設計具有特殊幾 何形狀,不僅提供可彎曲性而且提供顯著超過該GaAs自身 150175.doc 51 201042951 的本質屈服點(約2%)之應變水準(約1〇%)之機械可延伸 性。所得之類型的可延伸高效能電子系統可提供極高水準 的可彎曲性及與曲線表面等形整合之能力。此QaAs系㈣ 例以四種重要方式擴展吾人所描述之,,波狀”石夕:⑴其展示 GaAs(GaAs在實際條件下是比Si更機械脆弱之材料可延 伸性’(ii)其引入一新"麵棱,,幾何形狀,其可連同先前描述 之"波狀"組態或獨立於先前描述之”波狀"組態而用於實現 可延伸性,(m)其達成一新類型可延伸裝置(意即 MESFET) ’及(iv)其展* 了與石夕相比可延伸於更大範圍中 且在壓縮/拉緊中具有更大對稱性的延伸。 圖22說明用於在一由聚(二甲基矽氧烷)(pDMs)製造之彈 性體基板上製造可延伸GaAs帶之步驟。該等帶由具有多個 磊晶層之高品質GaAs塊晶圓產生。該晶圓是藉由在一 (100)半絕緣GaAs(Si-GaAS)晶圓上生長一 200聰厚A1As 層,接著順序沈積一具有150 nm厚度之以七3八3層及具有 120 nm厚度及4xl0i7 cm-3載體濃度之&摻雜n型層來 製備。與(0 Π)結晶方向平行而界定之光阻線之圖案充當 磊晶層(包括GaAs及AlAs)的化學蝕刻之遮罩。使用H3p〇4 及H2〇2之含水蝕刻劑之各向異性蝕刻將此等頂部層隔離為 具有由光阻界定的長度及取向,且具有相對於晶圓表面成 銳角之側壁的個別條塊。在該各向異性触刻之後移除該光 阻且接著將該晶圓浸泡於HF之乙醇溶液(乙醇與49%含水 HF之間體積比為2:1)可移除該A1As層及釋放帶— GaAs/Sl-GaAs)。在此步驟中,使用乙醇取代水減少了歸 150175.doc '52· 201042951 因於乾燥期間之毛細營力 e力之作用而在該等易碎帶中可發生 的破裂。與水相比乙醇之更 又低之表面張力亦最小化了在該 等GaAs帶之空間布局中的出 的由乾燥引發之無序。在下一步驟 中’將具有釋放的GaAs帶·夕曰南 帶之日日®與一預延伸PDMS平板之 Ο Ο 表面接觸,使該等帶沿延伸方向對準。在此種狀況下,凡 得瓦爾力在聰S_GaAs之間之交互作用中占主要地位。 對於要求更強交互作用強度之狀況,將叫之—薄層沈積 至GaAs上,且在接觸之前不久將pDMs曝露於紫外線引發 之臭氧(思~,空4令氧氣之產物)。臭氧在pDMS之表面 上產生-Si-OH基團,其—經接觸就與Si〇2表面反應以形成 橋接矽氧烷-Si-O-Si-鍵。由於該等帶之側面之幾何形狀, 所沈積Si〇2在每一帶的邊緣處係非連續的。對於弱及強結 合程序兩者而言,將該PDMS自該母晶圓剝離就使所有帶 轉移至PDMS之表面。使該PDMS中預應變鬆弛會導致沿該 等帶之大尺度翹棱及/或正弦波狀結構之自發形成。該等 帶之幾何形狀極大地取決於施加至該印章之預應變(藉由 AZ/L界定)、PDMS與帶之間的交互作用、及該等帶之撓曲 剛性。對於此處研究之帶,小預應變(<2%)對於強及弱交 互作用之狀況皆產生具有相對小的波長及振幅之高度正弦 的”波"(圖22右邊框、中間框)。GaAs中此等幾何形狀與針 對Si報告之幾何形狀類似。可施加更高之預應變(例如高達 約15°/。)以建立類似類型的波,其中在該等帶與該基板之間 存在強結合。在弱交互作用強度及大預應變之狀況下形成 由具有相對大振幅及寬度之無週期,,翹棱”組成之不同類型 150175.doc -53- 201042951 的幾何形狀(圖22右邊框、頂部框)。另外,吾人之研究結 果展不兩種類型結構(翹棱及波)可在單一帶中共存,其撓 曲剛性沿其長度變化(例如歸因於與裝置結構相關聯之厚 度變化)。 圖23展示了藉由PDMS(約5 mm厚度)與帶之間的強結合 而形成之具有270 nm(包括《-GaAs及Si-GaAs層)厚度及丨〇〇 μηι(此實例中討論的所有帶皆具有1〇〇 μιη之寬度)寬度之波 狀GaAs帶的若干顯微圖。使用在仏^上的2_nm ^及以-nm Si〇2層,該製造遵循強結合之程序。在結合之前不久 或在結合期間藉由熱膨脹(在一烘箱中加熱至9〇t>c )而在 PDMS中建立約^%(自PDMSi熱回應計算得)的雙軸預應 變。此加熱亦加速界面矽氧烷鍵之形成。在將GaAs帶轉移 之後將該PDMS冷卻至室溫(約27。〇,從而釋放預應變。 圖23之框A、B&C分別展示用光學顯微鏡、電子掃描顯微 鏡(SEM)及原子力顯微鏡(AFM)自相同樣品收集之影像。 該等影像展示了該等GaAS帶中週期性、波狀結構之形成。 藉由自AFM影像(圖23D)估計切割線(圖23E及23〇來定量 地刀析6亥等波。與帶之縱向方向平行之圍線清楚地展示了 與正弦波(圖23E之虛線)的計算擬合一致的週期性、波狀 輪廓。此結果與對半無限低模數支撐物上的均勻的、薄 的、高模數層中之起始輕棱幾何形狀之非㈣分析達成一 致。與此函數關聯之峰_峰振幅及波長分別被確定為2 56及 35.0 μιη。自該印章上鄰近兩個尖峰之間水平距離(意即該 波長)與該等尖峰之間實際圍線長度(意即藉由AFM量測的 150175.doc •54- 201042951 表面距離)之間的比例計算之應變(吾人稱為帶應變)產生比 該PDMS中預應變更小的值(意即13%)。此差別可歸因於 PDMS之低剪力模數及與比PdmS基板之長度更短的GaAs 帶之長度相關之島效應。在波峰及波谷處之GaAs帶之表面 應變(吾人稱為最大GaAs應變)由帶厚度及根據!^/2(其中κ 為曲率)的該等波之波峰或波谷的曲率半徑求得。在此估 算中,因為該PDMS可被視為模數與(^入5之模數相比較低 之半無限支撐物(GaAs之楊氏模數:85.5 GPa對PDMS之楊 氏模數:2 MPa),所以可忽略該PDMS印章中應變對GaAs 的直接影響。對於圖23E之資料,最大GaAs應變為約 0.62%,其比帶應變(意即丨3%)小兩倍以上。此機械優勢 在GaAs帶中提供可延伸性,物理性質與波狀以相似。 如圖23F中所示,該等帶之波峰及波谷區域分別比原始 PDMS之表面(意即無帶的區域)之輪廓水平面(綠曲線之右 邊邛刀)更咼及更低。该結果暗示作為分別由波峰及波谷 中的GaAs帶施加至PDMS之向上及向下力之結果,〜舳下 的PDMS採取一波狀輪廓。靠近該等波之波峰的1>1)撾8之準 確幾何形狀難以直接估計。吾人懷疑除了向上變形外亦存 在由柏松效應引起之橫向頸縮。可藉由將應變施加至 PDMS來延伸及壓縮(所謂的所施加應變分別對延伸表示為 正而對壓縮表示為負)該?〇]^8印製器上的波狀帶。圖23a 及23B之插圖展示當施加一相對小延伸應變(意即約ι 5%) 時變形為其原始扁平幾何形狀之帶的影像。進一步的延伸 將更多張力應變轉移至該扁平GaAs帶,從而當此過量應變 150175.doc •55- 201042951 達到GaAs之失效應變時導致帶之破損。施加至基板之壓縮 應變減少該等波狀帶之波長且增加該等波狀帶之振幅。當 波峰(及波谷)處之彎曲應變超過該失效應變時就產生壓縮 失效。此隨著應變之波長變化與先前矽中的觀察結果一致 且與由理想模型推導出的波長不變性之預測不同。 可藉由經由使用一機械台(與熱膨脹相反)而增加施加至 PDMS的預應變來改良波狀GaAs帶之可延伸性。舉例而 言,將具有SiCh層之GaAs帶轉移至一具有7 8%預應變之 PDMS印章的表面上可產生GaAs中無任何可觀測破裂之波 狀帶(圖24A)。此種狀況下,波峰處的彎曲應變估算為約 12%,其比GaAs之失效應變(意即約2%)更低。與該低預 應變狀況類似,當延伸及壓縮該系統時該等波狀帶類似於 一手風琴般運作:波長及振幅變化以適應所施加應變。如 圖24A所示,該等波長隨著拉伸應變而增加,直至該等帶 變為扁平,且隨著壓縮應變減小,直至該等帶破裂。此等 變形為完全可逆的,且不包含PDMS上的GaAs之任何可量 測的滑動。與在具有弱結合及低得多的預應變之si帶中所 觀測到之略微不對稱性質相比,波長在壓縮及拉伸中隨著 所施加應變而線性地變化(見圖24B中黑色線及符號卜 在實際應用中,以一保持該等(^八3帶及裝置之可延伸性 之方式將其囊封可為有用的。作為一種可能性之簡單展 不,吾人在諸如圖24A中所示者的樣品上澆鑄且固化pDMs 預聚合物以將該等帶嵌入PDMS。經嵌入系統展示與未嵌 入之系統類似之機械性質,意即延伸該系統時增加波長^ 150175.doc .56· 201042951 壓縮該系統時減少波長(圖24B中紅色線及符號)。歸因於 固化第二PDMS層之收縮產生中等量的額外應變(約i%)。 此應變導致該等波狀帶之波長中的略微減少,進而略微擴 展了可延伸性之範圍。圖24B展示該差別。總的來說,以 約7.8°/。之預應變產生之系統可延伸或壓縮至高達約1〇%的 應變而不在GaAs中引致任何可觀測之破損。 PDMS基板上的波狀GaAs帶可用以製造高效能電子裝 置,諸如MESFET,該等電子裝置之電極是經由在轉移至 PDMS之前在晶圓上的金屬化及加工而形成。此等金屬層 以一空間相依之方式改變該等帶之撓曲剛性。圖25A展示 在轉移至一具有約1.9%之預應變之PDMS基板之後與歐姆 條(源極及汲極)及肖特基觸點(閘極)整合的^八8帶。該等 歐姆觸點由包括AuGe(70 nm)/Ni(10 nm)/Au(70 nm)之金屬 堆疊組成,該等金屬堆疊係經由微影界定之遮罩以及在一 具有流動的A之石英管中在高溫(意即45〇〇c持續1 下 將晶圓之順序退火而形成於初始晶圓上。此等歐姆區段具 有500 μιη之長度。兩個相鄰歐姆觸點之間之距離為5〇〇 μηι(意即通道長度)。具有240 μηι之長度(意即閘極長度)之 肖特基觸點係藉由根據光微影設計之遮罩經由電子束蒸鍍 直接沈積75-nm Cr層及75-nm Au層來產生。該等電極具有 等於該等GaAs帶之寬度,意即1〇〇 μηι ;其相對大尺寸便 利了探測。可顯著減小電極及半導體通道之尺寸以達成增 強之裝置效能。如圖25Α中所示,此等可延伸 MESFET僅在無電極之區域中展示短程週期波。在較厚區 150175.doc -57· 201042951 域中不存在波是由主要歸因於與該等金屬相關聯之額外厚 度的該等區域的增強的撓曲剛性所引起的。可藉由使用大 於約3。/。之預應變而在更厚區域中起始週期波。然而,在 此等狀況下,歸因於關鍵瑕疵及/或在該等金屬電極之邊 緣附近的高應變峰值,該等帶傾向於在該等金屬電極的邊 緣處破裂。此失效模式限制了可延伸性。 為克服此偈限性,吾人藉由消除矽氧烷鍵結來減小 MESFET與PDMS之間之交互作用的強度。對於此等實例, 歸因於該等帶自PDMS表面之實體脫離,>3%之預應變就 產生具有相對大寬度及振幅之大的、無週期翹棱。圖25β 呈現此類型系統(如以約7〇/〇之預應變製備),其中該等大的 龜棱形成於該等裝置的較薄之區域中。如該等垂直線所指 示’ s玄脫離似乎略微擴展至具有歐姆條之較厚區域。沿帶 之對比度變化係歸因於反射及與通過該曲線GaAs區段之光 相關的折射。該SEM影像(圖25C)清楚地展示弧形翹棱及 扁平、未受力PDMS之形成。此等翹棱顯示尾部延伸至具 有歐姆觸點之側邊的非對稱輪廓(如由紅色曲線指示)。此 不對稱可歸因於個別電晶體之歐姆條及肖特基觸點之不等 長度(500 μιη對240 μιη)。藉由約6%與約7%之間之所施加 延伸應變,此類翹棱MESFET可延伸至其原始扁平狀態(圖 25D)。然而,由於弱結合’壓縮圖25B中所示之系統導致 可自PDMS表面之連續脫離而形成更大的想棱。根據先前 描述之程序將此等裝置嵌入PDMS中消除了此類非受控之 性質。圖25B展示此系統’其中液態PDMS前驅物填充該等 I50175.doc -58- 201042951 翹棱之下之間隙。完全包圍之pdms限定了該等帶且防止 其滑動及脫離。截入裝置能可逆地延伸及壓縮至高達約 6〇/〇之應變而不損壞該等帶。值得注意的是,當將嵌入系 統壓縮-5.83%(圖25E之頂部框)時,在具有金屬電極之區域 中形成週期性的小的波狀以及在翹棱區域中形成新的波 紋。此等新的小波狀之形成(與該等大翹棱組合)增強了可 壓縮性。延伸該系統迫使該等翹棱區域以一使得此等翹棱 可變平之方式來壓縮及延伸該PDMS,進而伸長了該等帶 〇 的伸出長度(圖ME之底部框)。此等結果表明具有大翹棱 (幾何形狀與波狀截然不同)之嵌入裝置代表了一可與波狀 方法組合使用或獨立於該波狀方法使用的用以達成可延伸 性及可壓縮性之有希望的方法。 翹棱裝置之效能可藉由直接探測自源極至汲極之電流來 #估。圖26A展示在一晶圓上製造,使用一扁平pDMS印章 揀取且轉移印刷至一具有4 7%之預應變之pDMS基板上的 ^ GaAs帶褒置。在此組態中,金屬電極曝露至空氣以用於電Meter AN/2) to measure. We use mechanical tables to measure these devices during and after extension and compression. As a way to explore the reversibility of the process, we measured three different pns under ambient light before and after about 100 compressions (to about 5% strain), extensions (to about 5% strain), and after the release cycle. Polar body. Figure 19 shows no results. Figures 2G and 21 show images, schematic descriptions, and device measurements from a wavy transistor. Example 2: The ribbed and wavy GaAs strips used in high performance electronic circuits on elastomeric substrates are manufactured in a submicron range with well defined "wavy" and/or warp geometry Crystal GaAs tape. The resulting structure on the surface of an elastomeric substrate or embedded in an elastomeric substrate exhibits a reversible extensibility and compressibility of >1% strain, which is more than ten times greater than the reversible extension and compressive strain of GaAs itself. High performance extendable electronics (e.g., metal semiconductor field effect transistors) can be achieved by integrating ohmic and Schottky contacts on the straps of such structures. Such electronic systems can be used alone or in combination with similar designs, dielectrics, and/or metallic materials to form for high frequency operation and extensibility, extreme flexibility, or seldom. 150175.doc - 50- 201042951 The circuit of the application of the ability of the surface of the miscellaneous curve shape to match. In traditional microelectronics, performance capabilities are measured primarily based on speed, power efficiency, and integration levels. The other steps in the electronic device form are driven by the ability to integrate or cover a large area on a non-conventional substrate (e.g., low cost plastic, box, paper). For example, a new form of X-ray medical diagnosis can be achieved by a large area imager that isomorphously wraps the body to digitally image the desired tissue. It can be displayed on a variety of surfaces and surface shapes! Wall-sized displays or sensors provide new technologies for building S-meters. Various materials including small organic molecules, polymers, amorphous slabs, polycrystalline slabs, single crystal sillimanite wires, and microstructured bands have been explored to serve as thin film electrons that can support these and other applications. The semiconductor of the device is f. These materials make it possible to have a mobility that spans a wide range (i.e., from 10_5 to 500 cm /V's) and a mechanically bendable film shape on a flexible substrate. Applications requiring high speed operation such as Large Aperture Interferometric Synthetic Aperture Radar (InSAR) and Radio Frequency (RF) monitoring systems require semiconductors with very high mobility, such as GaAs, or InP. The fragility of single crystal composite semiconductors creates a number of manufacturing challenges that must be overcome in order to produce high speed, flexible transistors having such semiconductors. I use self-identity. A practical method is to create a printed GaAs line array on a die wafer to construct a metal semiconductor field effect transistor (MESFET) on a plastic substrate. These devices exhibit good mechanical flexibility and fT. near 2 GHz even in medium scale devices (e.g., micro-gate lengths). This example shows a GaAs v based MESFET (as opposed to a wire arrangement) designed to have a special geometry that not only provides bendability but also provides a substantial yield point (about 2%) that significantly exceeds the GaAs itself 150175.doc 51 201042951 Mechanical extensibility of strain level (about 1%). The resulting type of extensible high-performance electronic system provides extremely high levels of flexibility and the ability to integrate contours with curved surfaces. This QaAs system (IV) expands what we have described in four important ways, wavy "Shi Xi: (1) it shows GaAs (GaAs is more mechanically weaker than Si under practical conditions) (ii) its introduction a new "face, geometry, which can be used to achieve extensibility in conjunction with the previously described "wave" configuration or independent of the previously described "wavy" configuration, (m) A new type of extendable device (meaning MESFET) is achieved, and (iv) exhibits an extension that extends over a larger range and has greater symmetry in compression/tensioning than the stone eve. Description of the steps for fabricating an extensible GaAs ribbon on an elastomeric substrate made of poly(dimethyloxane) (pDMs) produced by a high quality GaAs bulk wafer having a plurality of epitaxial layers The wafer is grown by growing a 200 thick A1As layer on a (100) semi-insulating GaAs (Si-GaAS) wafer, followed by sequentially depositing a thickness of 150 nm with a thickness of 783 and a thickness of 120 nm. The thickness and the concentration of 4xl0i7 cm-3 carrier are prepared by doping the n-type layer, which is defined by parallel to the (0 Π) crystal direction. The pattern of the resist line acts as a mask for the chemical etching of the epitaxial layer (including GaAs and AlAs). The anisotropic etch of H3p〇4 and H2〇2 is used to isolate the top layer to have a photoresist defined by the photoresist. Length and orientation, and individual strips having sidewalls at an acute angle relative to the surface of the wafer. After the anisotropic etch, the photoresist is removed and the wafer is then immersed in an ethanol solution of HF (ethanol and 49 The volume ratio of % aqueous HF is 2:1) The A1As layer and the release band - GaAs/Sl-GaAs can be removed. In this step, the use of ethanol instead of water reduces the rupture that can occur in such fragile zones due to the effect of the capillary force during drying. The lower surface tension of ethanol compared to water also minimizes the dry-induced disorder in the spatial layout of the GaAs ribbons. In the next step, the day-to-day® with the released GaAs tape, the 曰 曰 South belt, is brought into contact with the surface of the 延伸 一 of a pre-stretched PDMS plate, so that the bands are aligned in the extending direction. In this situation, Van Valli dominates the interaction between Sonic S_GaAs. For conditions requiring stronger interaction strength, a thin layer will be deposited onto the GaAs and the pDMs will be exposed to UV-induced ozone shortly before contact (think, air 4 products). Ozone produces a -Si-OH group on the surface of the pDMS which, upon contact, reacts with the surface of the Si?2 to form a bridged alkane-Si-O-Si- linkage. Due to the geometry of the sides of the strips, the deposited Si〇2 is discontinuous at the edges of each strip. For both weak and strong bonding procedures, stripping the PDMS from the mother wafer transfers all of the tape to the surface of the PDMS. Prestrain relaxation in the PDMS results in spontaneous formation of large scale ridges and/or sinusoidal structures along the zones. The geometry of the bands greatly depends on the pre-strain applied to the seal (defined by AZ/L), the interaction between the PDMS and the belt, and the flexural rigidity of the belts. For the band studied here, the small pre-strain (<2%) produces a highly sinusoidal "wave" with relatively small wavelengths and amplitudes for both strong and weak interactions (Figure 22 right border, middle frame) These geometries in GaAs are similar to those reported for Si. Higher pre-strains (e.g., up to about 15°/.) can be applied to create similar types of waves where there is a presence between the strips and the substrate. Strong combination. Under the condition of weak interaction intensity and large pre-strain, the geometry of different types 150175.doc -53- 201042951 composed of non-period with relatively large amplitude and width is formed (the right border of Fig. 22) , the top box). In addition, our research results show that neither type of structure (warping and wave) can coexist in a single band, and its flexural rigidity varies along its length (eg, due to thickness variations associated with device structure). Figure 23 shows a 270 nm (including "-GaAs and Si-GaAs layer" thickness and 丨〇〇μηι formed by a strong bond between PDMS (about 5 mm thickness) and the strip (all discussed in this example) Several micrographs of a wavy GaAs strip having a width of 1 〇〇 μηη width. Using 2_nm^ and -nm Si〇2 layers on 仏^, the fabrication follows a strong binding procedure. A biaxial pre-expansion of about 5% (calculated from the PDMSi thermal response) was established in the PDMS by thermal expansion (heating to 9 〇t > c in an oven) shortly before or during the bonding. This heating also accelerates the formation of interfacial aerobic bonds. After transferring the GaAs tape, the PDMS was cooled to room temperature (about 27. 〇, thereby releasing the pre-strain. Box A, B & C of Figure 23 shows optical microscopy, electron scanning microscopy (SEM), and atomic force microscopy (AFM, respectively). Images collected from the same sample. These images show the formation of periodic, wavy structures in these GaAS bands. Estimate the cutting line from the AFM image (Fig. 23D) (Figures 23E and 23〇 for quantitative analysis) 6 Hz equal wave. The line parallel to the longitudinal direction of the band clearly shows the periodic, wavy contour consistent with the computational fit of the sine wave (dashed line in Figure 23E). This result is in contrast to the semi-infinite low modulus support. The non-fourth analysis of the initial light-edge geometry in the uniform, thin, high-modulus layer on the object was agreed. The peak-to-peak amplitude and wavelength associated with this function were determined to be 2 56 and 35.0 μηη, respectively. The ratio between the horizontal distance between the two peaks on the stamp (ie the wavelength) and the actual line length between the peaks (ie 150175.doc • 54- 201042951 surface distance measured by AFM) Calculated strain (I call it Strain) produces a smaller value (ie, 13%) than the pre-modification change in the PDMS. This difference can be attributed to the low shear modulus of PDMS and the island associated with the length of the GaAs strip that is shorter than the length of the PdmS substrate. The surface strain of the GaAs strip at the peaks and troughs (which I call the maximum GaAs strain) is obtained from the thickness of the strip and the radius of curvature of the peaks or troughs of the waves according to !^/2 (where κ is the curvature). In this estimation, because the PDMS can be regarded as a modulus and a lower half-infinite support compared to the modulus of 5 (Young's modulus of GaAs: 85.5 GPa to Young's modulus of PDMS: 2 MPa ), so the direct effect of strain on GaAs in the PDMS stamp can be ignored. For the data in Figure 23E, the maximum GaAs strain is about 0.62%, which is more than twice the band strain (meaning 丨3%). The GaAs tape provides extensibility, and the physical properties are similar to those of the wavy. As shown in Fig. 23F, the peaks and trough regions of the bands are respectively higher than the contour of the surface of the original PDMS (ie, the unbanded region) (green) The right side of the curve is more sturdy and lower. The result is implied as a separate wave As a result of the upward and downward forces applied to the PDMS by the GaAs strips in the troughs, the PDMS under the armpits adopts a wavy profile. The 1>1 near the peaks of the waves is difficult to estimate directly. It is suspected that in addition to the upward deformation, there is also lateral necking caused by the cypress effect. It can be extended and compressed by applying strain to the PDMS (so-called applied strain is expressed as positive for extension and negative for compression) The undulations on the printer. The illustrations of Figures 23a and 23B show an image of the strip deformed to its original flat geometry when a relatively small extension strain (i.e., about 5% 5%) is applied. Further extensions transfer more tension strain to the flat GaAs strip, causing damage to the strip when the excess strain 150175.doc • 55- 201042951 reaches the strain strain of GaAs. The compressive strain applied to the substrate reduces the wavelength of the undulating bands and increases the amplitude of the undulating bands. Compression failure occurs when the bending strain at the peak (and trough) exceeds the failure strain. This varies with the wavelength of the strain as observed in previous observations and is different from the prediction of wavelength invariance derived from the ideal model. The extensibility of the wavy GaAs ribbon can be improved by increasing the pre-strain applied to the PDMS by using a mechanical stage (as opposed to thermal expansion). For example, transferring a GaAs band with a SiCh layer onto a surface of a PDMS stamp with a 78% pre-strain produces a wavy band without any observable rupture in GaAs (Fig. 24A). In this case, the bending strain at the peak is estimated to be about 12%, which is lower than the failure strain of GaAs (that is, about 2%). Similar to this low pre-strain condition, the undulating bands operate like an accordion when extending and compressing the system: wavelength and amplitude changes to accommodate the applied strain. As shown in Fig. 24A, the wavelengths increase with tensile strain until the bands become flat and decrease as the compressive strain decreases until the bands are broken. These deformations are fully reversible and do not include any measurable slip of GaAs on the PDMS. Compared to the slightly asymmetrical nature observed in the si band with weak bond and much lower pre-strain, the wavelength varies linearly with compression applied in compression and stretching (see black line in Figure 24B). And in the practical application, it may be useful to encapsulate the same in such a way as to maintain the extensibility of the device. As a simple possibility, we are in, for example, Figure 24A. The pDMs prepolymer is cast and cured on the sample shown to embed the ribbons into the PDMS. The embedded system exhibits mechanical properties similar to those of the unembedded system, meaning that the wavelength is extended when the system is extended ^ 150175.doc .56· 201042951 Reduces the wavelength when compressing the system (red line and symbol in Figure 24B). Due to the shrinkage of the cured second PDMS layer, a moderate amount of additional strain (about i%) is produced. This strain results in the wavelength of the wavy bands. A slight reduction, and thus a slight extension of the range of extensibility. Figure 24B shows this difference. In general, a system produced with a pre-strain of about 7.8 ° / can be extended or compressed to a strain of up to about 1% Not in GaAs The damage can be observed. The corrugated GaAs strip on the PDMS substrate can be used to fabricate high performance electronic devices, such as MESFETs, whose electrodes are formed via metallization and processing on the wafer prior to transfer to PDMS. The metal layers change the flexural rigidity of the strips in a spatially dependent manner. Figure 25A shows the ohmic strips (source and drain) and Schott after transfer to a PDMS substrate having a pre-strain of about 1.9%. The base contact (gate) is integrated with the 8 8 band. The ohmic contacts are composed of a metal stack including AuGe (70 nm) / Ni (10 nm) / Au (70 nm), the metal stack is via micro The shadow-defining mask and the quartz wafer in a flowing A are sequentially annealed at a high temperature (that is, 45 〇〇c for 1) on the initial wafer. These ohmic sections have 500 μm The length between two adjacent ohmic contacts is 5〇〇μηι (meaning channel length). The Schottky contact with a length of 240 μη (meaning the gate length) is based on light micro The mask of the shadow design directly deposits the 75-nm Cr layer and 7 via electron beam evaporation. The 5-nm Au layer is produced. The electrodes have a width equal to the width of the GaAs strips, that is, 1 〇〇μηι; its relatively large size facilitates detection. The device can be significantly reduced in size to achieve enhanced device Performance. As shown in Figure 25, these extendable MESFETs exhibit short-range periodic waves only in the area without electrodes. The absence of waves in the thicker region 150175.doc -57· 201042951 is mainly attributed to The increased flexural rigidity of the regions of the additional thickness associated with the metal may be greater than about 3 by use. /. The pre-strain starts the periodic wave in a thicker region. However, under such conditions, the bands tend to rupture at the edges of the metal electrodes due to critical enthalpy and/or high strain peaks near the edges of the metal electrodes. This failure mode limits extensibility. To overcome this limitation, we have reduced the strength of the interaction between the MESFET and the PDMS by eliminating the siloxane coupling. For these examples, the pre-strain of > 3% produces a large, non-periodic ridge with a relatively large width and amplitude due to the detachment of the elements from the PDMS surface. Figure 25 is a system of this type (e.g., prepared with a pre-strain of about 7 〇/〇) in which the large ridges are formed in the thinner regions of the devices. As indicated by the vertical lines, the s-segmental detachment appears to extend slightly to a thicker region with ohmic stripes. The change in contrast along the band is due to reflection and refraction associated with light passing through the GaAs segment of the curve. The SEM image (Fig. 25C) clearly shows the formation of curved ridges and flat, unstressed PDMS. These ridges show an asymmetrical profile with the tail extending to the side with ohmic contacts (as indicated by the red curve). This asymmetry can be attributed to the unequal lengths of the ohmic strips and Schottky contacts of the individual transistors (500 μηη vs. 240 μηη). Such a warped MESFET can be extended to its original flat state by an applied strain between about 6% and about 7% (Fig. 25D). However, the system shown in Figure 25B due to weak bond' compression results in a greater detachment from the PDMS surface. Embedding these devices into PDMS according to the previously described procedures eliminates such uncontrolled nature. Figure 25B shows the system 'where the liquid PDMS precursor fills the gap below the ridges of the I50175.doc -58- 201042951. The fully enclosed pdms define the bands and prevent them from slipping and escaping. The intercepting device can reversibly extend and compress to strains of up to about 6 〇/〇 without damaging the belts. It is worth noting that when the embedded system is compressed by -5.83% (the top frame of Fig. 25E), a periodic small wavy shape is formed in the region having the metal electrode and a new wavy is formed in the ridge region. The formation of these new wavelets (in combination with these large ridges) enhances compressibility. Extending the system forces the slanted regions to compress and extend the PDMS in such a manner that the ridges are flattened, thereby elongating the extent of the ridges (the bottom frame of Figure ME). These results indicate that an embedded device with large ridges (distinct geometry and wavy) represents a combination of wavy methods or independent of the wavy method for achieving extensibility and compressibility. Promising approach. The performance of the warp device can be estimated by directly detecting the current from the source to the drain. Figure 26A shows a GaAs tape device fabricated on a wafer, picked up using a flat pDMS stamp and transferred to a pre-strained pDMS substrate with 47%. In this configuration, the metal electrode is exposed to air for electricity

探測。在將預延伸之PDMS鬆弛至3.4%之應變之後,週期 性的小波狀形成於MESFET之薄區域中(圖26A :自頂部第 一個框)。當將該預延伸PDMS印章完全鬆弛時,在純GaAs 之母一區段中的小波狀合併為個別的大輕棱(圖26A :自頂 部第三個框)。藉由施加4.7%的延伸應變,該等翹棱裝置 可延伸至其扁平狀態(圖26A :底部框)。具有〇.〇%(圖 26A :自頂部第三個框)及47%(圖26A :底部框)之所施加 應變之相同裝置的IV曲線分別以紅色及黑色繪製於圖26B 150175.doc •59· 201042951 中°該等結果指示PDMS基板上翹棱MESFET之自源極至汲 極之電流可以施加至閘極之電壓來良好地調節,且所施加 延伸應變對裝置效能僅產生微小影響。 概括而言’此實例揭示了一用以在PDMS彈性體基板上 形成"勉棱"及"波狀"GaAs帶及形成喪入PDMS彈性體基板 中之”龜棱’’及”波狀”GaAs帶之方法。此等帶之幾何組態視 製造中所使用之預應變位準、PDMS與帶之間交互作用強 度、及所使用材料的厚度及類型而定。歸因於麵棱及波狀 帶之幾何形狀的以一能適應所施加應變而不將彼等應變轉 移至材料自身的方式來進行調節之能力,GaAs多層堆疊及 το全形成之MESFET裝置之翹棱及波狀帶展示了較高水準 的可壓縮性/可延伸性。在一類似GaAs之本質脆弱之材料 中成功實現局水準的機械可延伸性(且作為結果,諸如極 端可彎曲性的其他具有吸引力之機械特性)提供了可適用 於寬廣範圍的其他材料類型的類似策略。 熱誘發之預應變係歸因於PDMS印章之熱膨脹,其具有 〜=3.1Χ1(Γ4 μηι/μΓηΛ:的本體線性熱膨脹係數。另一方 面,GaAs之熱膨脹係數僅為5 73χ1〇-6μιη/μπιΓ(:。因此, 對於在90 C製備且冷卻至27°C之樣品,PDMS上的預應變 (相對 GaAs 帶)根據 Δα/:χΔΓ=(3 1χ1〇.4_5 73χ1〇-6)χ(9〇_ 2 7) = 1 · 9 %來測定。 方法··自IQE公司(伯利恆,ΡΑ)購買具有用戶設計之磊 晶層之GaAs晶圓。微影製程使用八2光阻劑(即ΑΖ 5214及 AZ nLOF 2020分別用於正及負成像)。在以冰水浴冷卻之 150175.doc -60- 201042951 蝕刻劑(4 mL H3P04(85 重量 %)、52 mL H2〇2(3〇 重量 %), 及48 mL去離子水)中各向異性地蝕刻具有光阻遮罩圖案之 GaAS晶圓。用乙醇的稀HF溶液(體積比l:2)(Fisher® . Chemica⑷將AIAs層溶解。將在母體晶圓上具有釋放的帶 之樣品在一通風櫥中乾燥。將經乾燥之樣品置於電子束蒸 鍍器(TeinescalFC-1800)之腔室中,且鑛覆2_nmTi^8. si〇2之順序的層。在A1As層之移除之前藉由電子束蒸鍵而 沈積用於廳FET裝置之金屬。藉由將低模數PDMS之混合 物(Α.Β 1·1〇,Sylgard 184,Dow Corning)倒至以(三癸氟 基-1,I’2,2-四氫辛基)_卜三氯矽烷之單層預改質的一片矽晶 圓上,接著在65t下烘焙4小時來製備具有約5咖厚度之 PDMS印製器。為了產生強結合,將該等印章曝露至μ光 5分鐘。在該轉移過程中,、經由熱膨脹(在供箱巾)及/或機 械力來延伸該等印章。然後將具有釋放的帶之晶圓層壓至 紅延伸之PDMS印章的表面上,且使其在高溫(視所需預應 〇 變而保持接觸5分鐘。將母體晶圓自該等印章剝離且將probe. After relaxing the pre-stretched PDMS to a strain of 3.4%, a periodic wavelet is formed in the thin region of the MESFET (Fig. 26A: first frame from the top). When the pre-stretched PDMS stamp is completely relaxed, the wavelets in a section of pure GaAs are merged into individual large ridges (Fig. 26A: third frame from the top). By applying an elongation strain of 4.7%, the warp devices can be extended to their flat state (Fig. 26A: bottom frame). The IV curves of the same device with the applied strain of 〇.〇% (Fig. 26A: third box from the top) and 47% (Fig. 26A: bottom frame) are plotted in red and black, respectively, in Fig. 26B 150175.doc • 59 · 201042951 Medium These results indicate that the current from the source to the drain of the warped MESFET on the PDMS substrate can be well regulated by the voltage applied to the gate, and the applied extension strain has only a minor effect on device performance. In summary, this example reveals a "turtle" used to form "勉" and "wavelike" GaAs ribbons on PDMS elastomer substrates and to form funnel-in PDMS elastomer substrates. The method of wavy "GaAs strips. The geometric configuration of these strips depends on the pre-strain level used in the manufacturing, the strength of the interaction between the PDMS and the strip, and the thickness and type of material used. The geometry of the rib and wavy band is adjusted in a manner that accommodates the applied strain without transferring the strain to the material itself, the rib multilayer and the wavy and wavy shape of the fully formed MESFET device The tape exhibits a high level of compressibility/extensibility. Successfully achieves a level of mechanical extensibility in a material that is inherently weak in GaAs (and as a result, other attractive features such as extreme bendability) Mechanical properties) provide a similar strategy for a wide range of other material types. Thermally induced pre-strain is attributed to the thermal expansion of the PDMS stamp, which has a body line of ~=3.1Χ1(Γ4 μηι/μΓηΛ: Thermal expansion coefficient. On the other hand, the thermal expansion coefficient of GaAs is only 5 73χ1〇-6μιη/μπιΓ (: Therefore, for samples prepared at 90 C and cooled to 27 ° C, the pre-strain on the PDMS (relative GaAs band) is based on Δα/: χΔΓ=(3 1χ1〇.4_5 73χ1〇-6)χ(9〇_ 2 7) = 1 · 9 % to measure. Method · Purchase user-designed epitaxial from IQE (Bethleon, ΡΑ) Layer GaAs wafer. The lithography process uses eight 2 photoresists (ie ΑΖ 5214 and AZ nLOF 2020 for positive and negative imaging respectively). 150175.doc -60- 201042951 etchant (4 mL) cooled in ice water bath Anisotropically etched a GaAS wafer with a photoresist mask pattern in H3P04 (85 wt%), 52 mL H2〇2 (3 wt%), and 48 mL deionized water. Dilute HF solution with ethanol ( Volume ratio 1:2) (Fisher®. Chemica (4) dissolves the AIAs layer. The sample with the released tape on the parent wafer is dried in a fume hood. The dried sample is placed in an electron beam vaporizer (TeinescalFC- a layer in the chamber of 1800) and covering the order of 2_nmTi^8. si〇2. Before the removal of the A1As layer by electrons The metal used for the FET device is deposited by steaming the bond. By mixing a mixture of low modulus PDMS (Α.Β1·1〇, Sylgard 184, Dow Corning) to (tris-fluorenyl-1, I'2 A single layer pre-modified piece of tantalum wafer of 2-tetrahydrooctyl)-trichlorodecane was then baked at 65 t for 4 hours to prepare a PDMS printer having a thickness of about 5 coffee. In order to create a strong bond, the stamps were exposed to μ light for 5 minutes. During the transfer, the seals are extended via thermal expansion (in the case of a towel) and/or mechanical force. The wafer with the released tape is then laminated to the surface of the red-extended PDMS stamp and allowed to remain exposed for 5 minutes at the desired temperature. The parent wafer is peeled from the stamps and will

所有▼轉移至印章。經由冷卻至室溫及/或移除該等機械 將施加至印早之預應變釋放,從而導致沿該等帶之波 狀輪廊的形成。在該等機械評估中,使用一特殊設計之A 來延伸以及壓縮具有"波狀"及"龜棱"GaAS帶之PDMS= 章。 實例3 :二維可延伸半導體 本發明提供能在多個方向(包括彼此正交定向之方向)上 I伸、壓縮及/或撓曲的可延伸半導體及可延伸電子裝 150175.doc •61 - 201042951 置。本發明之此態樣之可延伸半導體及可延伸電子裝置當 在多個方向上延伸及/或壓縮時展示良好的機械及電子性 質及/或裝置效能。 圖27A-C提供本發明之展示二維可延伸性之可延伸矽半 導體在不同放大程度的影像。圖27A-B中展示之可延伸半 導體係藉由透過熱膨脹而預應變一彈性基板來製備。 圖28A-C提供本發明之展示二維可延伸性之可延伸半導 體的三個不同結構構形之影像。如圖所示,圖28八中的半 導體結構展示一邊緣線波狀構形,圖28B中的半導體結構 展示一人字形波狀構形,且圖28C中的半導體結構展示一 隨機波狀構形。 圖29A-D提供透過熱膨脹而預應變一彈性基板來製造之 本發明之可延伸半導體的影像。 圖30展示透過熱膨脹而預應變一彈性基板來製備之展示 二維可延伸性之可延伸半導體的光學影像。圖3〇展示對應 於多種延伸及壓縮條件之影像。 圖31A展示透過熱膨脹而預應變一彈性基板來製造之展 示二維可延伸性之可延伸半導體的一光學影像。圖3ib及 31C提供關於圖31A中展示之可延伸半導體之機械性質的 實驗結果。 文獻 1. S. R. Forrest, Nature 428, 911 (2004). 2. 對於近來進步及回顧,見尸r〇c仏五五%,Iss 7及8 (2005). 150175.doc -62- 201042951 3. J.A. Rogers等人,Proc. Α/αί. dcac?. Scz·· t/iSJ 98,4835 (2001). 4. H.O. Jacobs, A.R. Tao, A. Schwartz, D.H. Gracias, G.M. Whitesides, 隱e 296, 323 (2002). 5. H.E.A. Huitema等人,iVaiwre 414, 599 (2001). 6. C.D. Sheraw^ A > Appl. Phys. Lett. 80, 1088 (2002) 7. Y. Chen# A > Nature 423, 136 (2003). 8. H.C. Jin, J.R. Abelson, M.K. Erhardt, R.G. Nuzzo, J. 〇 Vac. Sci. Techn. B 22, 2548 (2004). 9. P.H.I. Hsu等人,/五五£ Dev· 51,371 (2004). 10. T. Someya^ A * Proc. Nat. Acad. Sci. USA 101, 9966 (2004) . 11. H.C. Lim等人,Jc,. J 119, 2005, 332 (2005). 12· J. Vandeputte 事乂 ^ US Patent 6,580,151 (2003). 13. T. Sekitani^-A > Appl. Phys. Lett. 86, 2005, 073511 o (2005) . 14. E. Menard, R.G. Nuzzo, J.A. Rogers, Appl. Phys. Lett. 86, 2005, 093507 (2005). 15. H. Gleskova^ A 5 J. Noncryst. Sol. 338, 732 (2004). 16. S.-H. Hur, O.O. Park, J.A. Rogers, Appl. Phys. Lett. 86, 243502 (2005). 17. X_F_ Duan等人,iVaiwre 425, 274 (2003). 18. Z. Suo, E.Y. Ma, H. Gleskova, S. Wagner, Appl. Phys. 150175.doc -63- 201042951All ▼ is transferred to the stamp. The pre-strain release to the early impression is applied via cooling to room temperature and/or removal of the machine, resulting in the formation of a corrugated rim along the zones. In these mechanical evaluations, a specially designed A is used to extend and compress the PDMS= chapters with "waves" and "turtle" Example 3: Two-Dimensional Extensible Semiconductor The present invention provides an extensible semiconductor and an extendable electronic device that can be stretched, compressed, and/or flexed in multiple directions, including directions oriented orthogonally to one another, 150175.doc • 61 - 201042951 set. The extendable semiconductor and extendable electronic device of this aspect of the invention exhibit good mechanical and electronic properties and/or device performance when extended and/or compressed in multiple directions. Figures 27A-C provide images of the present invention showing extensible germanium semiconductors of two dimensional extensibility at different levels of magnification. The extensible semiconductor system shown in Figures 27A-B is prepared by pre-straining an elastic substrate by thermal expansion. Figures 28A-C provide images of three different structural configurations of the present invention showing two-dimensional extensible extendable semiconductors. As shown, the semiconductor structure of Figure 28 shows an edgeline wavy configuration, the semiconductor structure of Figure 28B exhibits a herringbone wavy configuration, and the semiconductor structure of Figure 28C exhibits a random wavy configuration. Figures 29A-D provide an image of an extensible semiconductor of the present invention fabricated by pre-straining an elastic substrate by thermal expansion. Figure 30 shows an optical image of an extensible semiconductor exhibiting two-dimensional extensibility prepared by pre-straining an elastic substrate by thermal expansion. Figure 3 shows an image corresponding to a variety of extension and compression conditions. Figure 31A shows an optical image of an extensible semiconductor exhibiting two-dimensional extensibility fabricated by pre-straining an elastic substrate by thermal expansion. Figures 3ib and 31C provide experimental results regarding the mechanical properties of the extensible semiconductor shown in Figure 31A. Literature 1. SR Forrest, Nature 428, 911 (2004). 2. For recent advances and reviews, see corpse r〇c仏 five or five percent, Iss 7 and 8 (2005). 150175.doc -62- 201042951 3. JA Rogers et al., Proc. Α/αί. dcac?. Scz·· t/iSJ 98,4835 (2001). 4. HO Jacobs, AR Tao, A. Schwartz, DH Gracias, GM Whitesides, Hidden e 296, 323 ( 2002). 5. HEA Huitema et al., iVaiwre 414, 599 (2001). 6. CD Sheraw^ A > Appl. Phys. Lett. 80, 1088 (2002) 7. Y. Chen# A > Nature 423, 136 (2003). 8. HC Jin, JR Abelson, MK Erhardt, RG Nuzzo, J. 〇Vac. Sci. Techn. B 22, 2548 (2004). 9. PHI Hsu et al., / 5:5 Dev· 51 , 371 (2004). 10. T. Someya^ A * Proc. Nat. Acad. Sci. USA 101, 9966 (2004) . 11. HC Lim et al., Jc, J 119, 2005, 332 (2005). 12· J. Vandeputte 事^ US Patent 6,580,151 (2003). 13. T. Sekitani^-A > Appl. Phys. Lett. 86, 2005, 073511 o (2005) . 14. E. Menard, RG Nuzzo, JA Rogers, Appl. Phys. Lett. 86, 2005, 093507 (2005). 15. H. Gleskova^ A 5 J. Noncryst. Sol. 338, 732 (20 04). 16. S.-H. Hur, OO Park, JA Rogers, Appl. Phys. Lett. 86, 243502 (2005). 17. X_F_ Duan et al., iVaiwre 425, 274 (2003). 18. Z. Suo, EY Ma, H. Gleskova, S. Wagner, Appl. Phys. 150175.doc -63- 201042951

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Nanowire Arrays for Integrated Nanosystems", Whang, D.; Jin, S.; Wu, Y.; Lieber, C. M. Nano Lett. (2003) 3(9), 1255-1259; (3) "Directed Assembly of One-DimensionalNanowire Arrays for Integrated Nanosystems", Whang, D.; Jin, S.; Wu, Y.; Lieber, CM Nano Lett. (2003) 3(9), 1255-1259; (3) "Directed Assembly of One- Dimensional

Nanostructures into Functional Networks", Yu Huang, Xiangfeng Duan, Qingqiao Wei, and Charles M. Lieber, (2001) 291, 630-633 ;及(4)"Electric-:field assisted assembly and alignment of metallic nanowires", Peter A. Smith等人,乂pp/.尸/2少5. Ze". (2000) 77(9),1399-1401。 貫穿本申請案之所有參考,例如包括已頒予或准予之專 利或其等效物之專利文獻;專利申請案公開案;未公開專 利申請案;及非專利文獻或其他資訊來源材料,以全文引 用的方式併入本文,該引用的程度就如同以引用的方式個 別併入該等文獻直至每一文獻至少部分與本申請案之揭示 内容不一致之範圍(例如,部分不一致的文獻的除了該部 分不一致部分外皆被以引用之方式併入本文)。 本文之任何附錄以引用之方式併入本文作為本說明書及 /或圖式之部分。 在本文中使用術語"包含(comprise)"、"包含了 (comprises)"、” 所包含(comprised)"、"正包含(comprising)" 處,應將這些表達理解為規定所說明特徵、整數、步驟, 或組件之存在,但不排除一或多個其他特徵、整數、步 驟、組件,或其群組之存在或添加。在術語"正包含 (comprising)"或"包含(了)(comprise(s))"或"所包含(comprised)" 視情況可由語法上類似之術語,例如"由…組成"或••實質上 150175.doc -70- 201042951 由.·.組成”來替代時,亦希望涵蓋本發明之單獨實施例, 從而描述不一定同延的另外的實施例。 . 已參考各種特定及較佳實施例及技術描述本發明。然 . m應瞭解到可進行各種變化及修改而同時保持在本發明 ,精砷及範内。對於—般熟習此項技術者顯而易見的 是不同於本文中特定描述者之組合物、方法、裝置、裝 置=件、材料、程序及技術可應用於如本文廣泛揭示之本 ❹=明之實踐而無須訴諸於不適當的實驗。本文所描述之組 合物、方法'裝置、裝置元件、材料、程序及技術之所有 2項技#中已知之功能等效物皆希望包含於本發明令。無 :::蛉揭不—範圍,皆希望包含所有子範圍及個別值,就 ”被獨立提出—樣。本發明並非由所揭示之實施例(包 括在圖式中展千今、+ /、或在本說明書中例示者)來限制,該 施例以實例## ^ 次說月之方式給出(不具限制性)。本發明之範 可應僅由申請專利範圍來限制。 ❹ 【圖式簡單說明】 圖1提_令£ _ jg — t 一 '、展不本發明之一可延伸半導體結構之原 顯微圖。 丹 < 项于刀 圖2展示—R5 ^ . 導趙結構之二視:顯微圖’其提供具有…表… 微Γ。展不本發明之可延伸半導體結構之陣列的原子力顯 Z展二本發明之可延伸半導體結構之光學顯微圖。 '一、本發明之具有一半導體結構之可延伸半導體矣士 150175.doc 71 201042951 構的原子力顯微圖,該半導體結構與一具有三維起伏圖案 之可撓性基板結合,該三維起伏圖案位於該基板之支樓表 面上。 圖6展示一說明製造本發明之可延伸半導體元件之例示 性方法的流程圖。 圖7展示具有由一可撓性橡膠基板支撐之波形曲線内表 面之縱向對準的可延伸半導體結構之陣列的圖像。 圖8展示本發明之一可延伸半導體結構之載面影像,其 中s亥可印刷半導體結構776由可撓性基板777來支撐。如圖 8所示,可印刷半導體結構776具有内表面,該等内表面具 有呈一週期波之輪廓形狀。 圖9A展示一說明製造可延伸薄膜電晶體之陣列的例示性 方法之流程圖。圖9B展示處於鬆弛及延伸組態中之可延伸 薄膜電晶體之陣列的光學顯微圖。 圖10 :在彈性體基板上建構可延伸單晶矽裝置之製程之 不意性說明。第一步(頂部框)涉及單晶矽薄(厚度在2〇與 320 nm之間)元件或完整的積體裝置(意即電晶體、二極體 等等)之製造,其藉由習知微影處理過程繼之以對絕緣物 上矽(SOI)晶圓的頂部矽及81〇2層之蝕刻來完成。在此等程 序之後,f結構由下層的晶圓支撑但不與其結合(頂部 框)。使一預應變彈性體基板(聚(二甲基矽氧烷)pDMS,藉 由dL延伸)與該等帶之引線接觸以導致此等材料之間的結 合(中部框)。剝離該PDMS,使該等帶結合於其表面上, 且接著釋放該預應變使得該PDMS鬆弛回到其不受約東之 150175.doc -72- 201042951 狀態(無應力長度L)。該鬆弛導致在該等帶中自發性形成 受到良好控帝j、極㈣期十生、可延伸之"波形"結構(底部 框)。 固 (八)在PDMS上波狀單晶石夕帶(寬度=2〇 ;間距 20 μηι,厚度=1〇〇 nm)之一大規模對準陣列的光學影像。 (B)自(A)中展示之陣列中取得的四個波狀矽帶之有角度掃 描電子‘、、'員微圖。该等波結構之波長及振幅在該陣列中極為 致(C)作為沿PDMS上一波狀Si帶之位置的函數的表面 间度(頂部框)及Si拉曼峰之波數(底部框),分別藉由原子 力及拉曼顯微法量測。該等線表示資料之正弦擬合。(D) 作為矽之厚度的函數的波狀矽帶之振幅(頂部框)及波長(底 邛框),白針對PDMS中給定位準之預應變。該等線對應於 计异’無任何擬合參數。 圖12:作為溫度之函數的翹棱波長。波長隨溫度增加之 略微降低歸因於PDMS的熱收縮,其導致在愈高溫度下製 0 備之樣品的波長愈短。 圖13 :作為矽厚度之函數的矽應變峰值,針對約ο』%之 預應變值。紅色符號對應於使用波長及振幅計算得的彎曲 應變,該等波長及振幅是基於描述該翹棱過程之方程式而 擷取的。黑色符號對應於類似的計算,但使用了藉由AFM 量測之波長及振幅。 圖14 : (A)PDMS基板上波狀單晶矽帶(寬度=2〇 μιη ;厚 度= 100 nm)之原子力顯微圖(AFM ;左邊框)及起伏輪廓(右 邊框;該等線係實驗資料之正弦擬合)。頂部、中部,及 150175.doc •73· 201042951 底部部分分別對應於當PDMS沿帶長度受到_7%(壓縮)、 〇%(未受力)及4.7%(延伸)的應變時之組態。(B)作為施加至 PDMS基板之應變(頂部框)的函數的波狀矽帶之平均振幅 (黑色)及波長變化(紅色)。為了波長量測,將不同的基板 用於拉緊(圓周)及壓縮(方塊)。矽應變峰值為所施加應變 (底部框)之函數。此等圖中之線表示計算,無任何自由擬 合參數。 圖15 : PDMS上波狀矽帶之AFM俯視影像,及在相對於 該等帶之長維的一角度處估算出之切割線。 圖16 :作為所施加應變之函數的矽帶應變。紅色符號對 應於使用波長及振幅藉由輪廓長度之數值積分而計算之應 變,該等波長及振幅是使用描述該翹棱過程的方程式擷 取。黑色付號對應於沿波狀Si帶在AFM表面輪廓中自表面 與水平距離之比例量測得的應變。 圖17 · (A)處於所施加的_11%(頂部)、〇%(中部)及 11%(底部)應變下之PDMS基板上的可延伸單晶碎叩二極體 的光學影像。鋁區域對應於薄(2〇nm)A1電極;粉色及綠區 域對應於矽之η(硼)及p(磷)摻雜區域。(B)作為可延伸矽卯 二T體之偏壓的函數的電流密度,在各種所施加應變位準 下量測。標:t TO”之曲線分別對應於曝露於環境光 或遮蔽於環境光之裝置。實線展示模型化結果。在所 施加的·9·9%、〇%及9.9%應變下量測之可延伸肖特基障壁 石夕m〇SFET之電流-電壓特性(閘極電壓以i ν步長自〇 ^ 化至-5 V)。 150175.doc -74· 201042951 圖18 :作為所施加應變之函數的矽應變峰值。藍色線基 於一手風琴風箱(accordi〇n bell〇ws)模型且黑色線係小 應變之一近似,其亦與翹棱機構一致。 圖19 :波狀pn二極體之電學量測值,在三個不同裝置 W、#2及#3)之麼縮(約5%所施加應變)、延伸(約i外所、施 加應變)及釋放之約100個週期之前(週期之前)及之後(週期 之後)在三個不同裝置中估算得出。該資料指示裝置性質 n统變化。所觀測到的變化之位準與反覆探測不改變所 施加應變的單-裝置所得的變化位準相當,且可能歸因於 探針觸點之輕微不同。 圖20 :處於未受力狀態(中部)及壓縮(頂部)及拉緊(底部) 狀態時之波狀矽肖特基障壁M〇SFET的光學影像(頂部 框)。S亥裝置之示意性說明(底部框)。 圖21 :處於不同所施加應變下時"波狀,,石夕肖特基障壁 MOSFET中量測得之轉移曲線。 〇 圖22.用於在PDMS基板上產生”輕棱,,及"波狀”仏^帶 之步驟之*意性說明。左邊底部框展示用以促進與該 PDMS之強結合的在該等帶之表面上的薄㈣2之沈積。此 結合導致在右邊中部框中展示之波狀幾何形狀之形成。弱 的凡得瓦爾力結合(及中等至高位準預應變)導致如右上部 框中所展示之翹棱幾何形狀。 圖23 :以經由熱膨脹產生之約19%之預應變形成之在 PDMS基板上的波狀GaAs;f的影像。相同樣品之光學⑷、 SEM(B)—維AFM(C)及俯視圖AFM(D)影像。該SEM影像 150175.doc -75· 201042951 係藉由在樣品表面與偵測方向之間將該樣品台傾斜45°角 來獲取。(該等帶上的點可為該等犧牲AlAs層之殘餘物。) 分別沿(D)中所示藍色及綠色線繪製之表面高度分佈(E、 F)。 圖24 : (A)在不同所施加應變下採集的、以7.8%預應變 形成、與該PDMS強結合之波狀GaAs帶之光學顯微圖。左 邊及右邊的藍色條加亮顯示了該結構中之某些峰值;此等 條之間距離之變化指示波長對所施加應變之相依性。(B) 作為(A)中所示波狀GaAs帶之所施加應變之函數的波長變 化,以黑色繪製;在嵌入PDMS之後之樣品(A)的系統之類 似資料,以紅色繪製。 圖25 :與歐姆(源極及汲極)及肖特基(閘極)觸點整合以 形成完整MESFET之GaAs帶之影像。(A)使用1.9%之預應 變及與該PDMS之強結合而形成之波狀帶之光學顯微圖, 其展示僅在無電極的區域(灰色)中週期波之形成。以約7% 之預應變及與該PDMS之弱結合形成之翹棱帶的(B)光學影 像及(C)SEM影像。(D),在(B)中所示之兩個翹棱裝置在其 被延伸至平坦之後的光學影像。(E),在(B)中所示之具有 不同外部施加應變(意即自頂部至底部,5.83%之壓縮應 變、無施加應變,及5.83%之延伸應變)的個別帶裝置在其 被嵌入PDMS之後的一組光學影像。 圖26 : (A),在PDMS基板中建構之一 PDMS印章上具有 不同應變之GaAs帶MESFET的光學影像。在該等裝置被轉 移至該PDMS印章之表面上之前施加至該PDMS印章的預應 150175.doc -76- 201042951 變為4.7%。(b)在該系統被施加4.7%之延伸應變之前及之 後(A)中所示的裝置之I-V曲線之比較。 圖27A-C提供展示二維可延伸性之本發明之可延伸半導 體在不同放大程度的影像。 圖28A-C提供展示二維可延伸性之本發明之可延伸半導 體的三個不同結構構形之影像。 圖29A-D提供藉由通過熱膨脹預應變該彈性基板而製備 之本發明之可延伸半導體的影像。Nanostructures into Functional Networks", Yu Huang, Xiangfeng Duan, Qingqiao Wei, and Charles M. Lieber, (2001) 291, 630-633; and (4)"Electric-:field assisted assembly and alignment of metallic nanowires", Peter A. Smith et al., 乂pp/. corpse/2 less 5. Ze". (2000) 77(9), 1399-1401. All references throughout this application, such as patent documents including patents granted or granted, or equivalents thereof; patent application publications; unpublished patent applications; and non-patent literature or other information source materials, full text The manner in which they are incorporated is incorporated by reference to the extent of the extent of the extent of the disclosure of the disclosure of the disclosure of each of the of Inconsistent parts are incorporated herein by reference. Any of the appendices herein are hereby incorporated by reference in their entirety as the extent of the present disclosure. In this article, the terms "comprises", "comprises", "comprised" ","comprising" The existence of the described features, integers, steps, or components, but does not exclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. In the term "comprising" Or "comprise(s))" or "comprised" may be grammatically similar terms, such as "consisting of" or •• substantially 150175.doc It is also intended to cover the individual embodiments of the invention, and thus, the embodiments of the invention are not necessarily the same. The invention has been described with reference to various specific and preferred embodiments and techniques. However, it should be understood that various changes and modifications can be made while remaining within the scope of the present invention. It will be apparent to those skilled in the art that the compositions, methods, devices, devices, materials, procedures, and techniques that are different from those specifically described herein can be applied to the practice of the present disclosure as broadly disclosed herein without Recourse to inappropriate experimentation. The functional equivalents of all of the compositions, methods, devices, materials, procedures, and techniques described herein are intended to be included in the present invention. None::: 蛉 不 — 范围 范围 范围 范围 范围 范围 范围 范围 范围 范围 范围 范围 范围 范围 范围 范围 范围 范围 范围 范围 范围Or, as exemplified in the present specification, the embodiment is given by way of example ## ^次月月(not limited). The scope of the invention should be limited only by the scope of the patent application. ❹ [Simple diagram Explanation] Figure 1 shows the original micrograph of the semiconductor structure of one of the inventions. Dan < Item is shown in Figure 2 - R5 ^ . : Micrograph 'which provides a microscopic view of an array of extensible semiconductor structures of the present invention. An optical micrograph of the extensible semiconductor structure of the present invention. An atomic force micrograph of an extensible semiconductor gentleman having a semiconductor structure 150175.doc 71 201042951, the semiconductor structure being combined with a flexible substrate having a three-dimensional relief pattern on a surface of the substrate of the substrate Figure 6 shows a description A flow chart of an exemplary method of forming an extensible semiconductor device of the present invention. Figure 7 shows an image of an array of extensible semiconductor structures having longitudinal alignment of the inner surface of a curved curve supported by a flexible rubber substrate. A carrier image of an extendable semiconductor structure of the present invention is shown, wherein the s-printable semiconductor structure 776 is supported by a flexible substrate 777. As shown in Figure 8, the printable semiconductor structure 776 has an inner surface, the inner surfaces Having a contour shape in the form of a periodic wave. Figure 9A shows a flow chart illustrating an exemplary method of fabricating an array of extensible thin film transistors. Figure 9B shows the optical array of an array of extensible thin film transistors in a relaxed and extended configuration. Micrograph. Figure 10: Unintentional description of the process of constructing an extensible single crystal germanium device on an elastomer substrate. The first step (top frame) involves a single crystal thin (between 2 and 320 nm thickness) components. Or the fabrication of a complete integrated device (ie, a transistor, a diode, etc.), which is followed by a conventional lithography process followed by a top 矽 and 8 on a silicon-on-insulator (SOI) wafer. After 1 〇 2 layers of etching, the f structure is supported by the underlying wafer but not bonded to it (top frame). A pre-strained elastomeric substrate (poly(dimethyl methoxy oxane) pDMS Contacting the leads of the strips by dL to cause bonding between the materials (middle frame). Peeling the PDMS, bonding the strips to its surface, and then releasing the pre-strain to the PDMS Relaxed back to its unaffected 150175.doc -72- 201042951 state (no stress length L). This relaxation leads to spontaneous formation in these zones, which is well controlled, and is extremely prolonged. "waveform" structure (bottom box). Solid (8) An optical image of a large-scale array of wavy single crystal slabs (width = 2 〇; pitch 20 μηι, thickness = 1 〇〇 nm) on PDMS. (B) An angled scan of the electronic ‘,, 、's micrographs of the four wavy bands obtained from the array shown in (A). The wavelength and amplitude of the equal-wave structure are extremely high in the array (C) as the inter-surface degree (top frame) as a function of the position of a wavy Si band on the PDMS and the wave number of the Raman peak (bottom frame). They were measured by atomic force and Raman microscopy, respectively. These lines represent the sinusoidal fit of the data. (D) The amplitude (top frame) and wavelength (bottom frame) of the wavy band as a function of the thickness of the crucible, white for the pre-strain of the positioning in the PDMS. These lines correspond to the difference' without any fitting parameters. Figure 12: Warping wavelength as a function of temperature. The slight decrease in wavelength with temperature is attributed to the thermal shrinkage of the PDMS, which results in a shorter wavelength of the sample prepared at the higher temperature. Figure 13: Peak strain of 矽 as a function of 矽 thickness, for a pre-strain value of approximately ο”%. The red symbol corresponds to the bending strain calculated using the wavelength and amplitude, which are based on the equation describing the warping process. The black symbol corresponds to a similar calculation, but uses the wavelength and amplitude measured by AFM. Figure 14: (A) Atomic force micrograph (AFM; left border) and undulating contour (right border; wavy experiment) of a wavy single crystal 矽 tape (width = 2 〇 μιη; thickness = 100 nm) on a PDMS substrate Sinusoidal fitting of the data). Top, middle, and 150175.doc •73· 201042951 The bottom portion corresponds to the configuration when PDMS is subjected to strains of _7% (compression), 〇% (unstressed), and 4.7% (extension) along the length of the belt. (B) Average amplitude (black) and wavelength change (red) of the wavy band as a function of the strain applied to the PDMS substrate (top frame). For wavelength measurement, different substrates are used for tensioning (circumference) and compression (squares). The 矽 strain peak is a function of the applied strain (bottom box). The lines in these figures represent calculations without any freely fitting parameters. Figure 15: AFM top view image of the corrugated ankle band on the PDMS, and the cut line estimated at an angle relative to the long dimension of the bands. Figure 16: Shear strain as a function of applied strain. The red symbol corresponds to the response calculated by integrating the wavelength and amplitude by numerical integration of the length of the profile, which is obtained using the equation describing the warping process. The black pay sign corresponds to the strain measured along the wavy Si strip in the AFM surface profile in proportion to the surface to horizontal distance. Figure 17 (A) Optical image of an extensible single crystal ruthenium dipole on a PDMS substrate with _11% (top), 〇% (middle) and 11% (bottom) strain applied. The aluminum region corresponds to a thin (2 〇 nm) A1 electrode; the pink and green regions correspond to the y (boron) and p (phosphorus) doped regions of germanium. (B) The current density as a function of the bias of the extendable TT body is measured at various applied strain levels. The curve of t: t TO corresponds to the device exposed to ambient light or shaded to ambient light. The solid line shows the modeled result. It can be measured under the applied 9.9%, 〇% and 9.9% strain. Extend the current-voltage characteristics of the Schottky barrier 石 〇 〇 FET FET FET FET FET FET FET FET 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 The 矽 strain peak. The blue line is based on an accordion bellows (accordi〇n bell〇ws) model and one of the small strains of the black line is similar, which is also consistent with the rib mechanism. Figure 19: Wave pn diode Electrical measurements, before the three different devices W, #2, and #3) (about 5% of the applied strain), extension (about i, applied strain) and release about 100 cycles (cycle Estimated from three different devices before and after (after the cycle). This data indicates the change in device properties. The observed level of change and the change in the single-device change that does not change the applied strain. The level is comparable and may be due to a slight difference in probe contacts. Figure 20: At Optical image (top frame) of the undulating Schottky barrier M〇SFET in the stressed (middle) and compressed (top) and tensioned (bottom) states. Schematic description of the S-device (bottom frame). Figure 21: Transfer curve measured in a wavy, wavy Schottky barrier MOSFET at different applied strains. Figure 22. Used to create a "light edge" on a PDMS substrate, and " The elaboration of the steps of the wavy "band" is shown. The left bottom frame shows the deposition of thin (4) 2 on the surface of the strips to promote strong bonding with the PDMS. This combination results in a box in the right middle box. The formation of a wavy geometry. The weak van der Waals force combination (and medium to high level pre-strain) results in a warp geometry as shown in the upper right frame. Figure 23: approximately 19% of the heat expansion The pre-strained image of the wavy GaAs;f on the PDMS substrate. The optical (4), SEM (B)-dimensional AFM (C) and topographic AFM (D) images of the same sample. The SEM image 150175.doc -75· 201042951 by tilting the sample stage between the surface of the sample and the direction of detection Obtained at an oblique angle of 45°. (The points on the strips may be the residues of the sacrificial AlAs layers.) Surface height distributions (E, F) plotted along the blue and green lines shown in (D), respectively. Figure 24: (A) Optical micrograph of a wavy GaAs ribbon formed at 7.8% pre-strain, strongly bonded to the PDMS, collected under different applied strains. The blue bars on the left and right highlight this Some peaks in the structure; the change in distance between the bars indicates the dependence of the wavelength on the applied strain. (B) The change in wavelength as a function of the applied strain of the wavy GaAs band shown in (A), Black drawing; similar data for the system of sample (A) after embedding PDMS, drawn in red. Figure 25: Image of a GaAs strip integrated with ohmic (source and drain) and Schottky (gate) contacts to form a complete MESFET. (A) An optical micrograph of a wavy band formed using a 1.9% pre-deformation and a strong bond with the PDMS, which shows the formation of periodic waves only in the electrodeless region (gray). (B) Optical image and (C) SEM image of the warp band formed by pre-strain of about 7% and weak combination with the PDMS. (D), the optical image of the two ribs shown in (B) after it is extended to flat. (E), the individual tape devices shown in (B) have different externally applied strains (ie, from top to bottom, 5.83% compressive strain, no applied strain, and 5.83% extended strain) are embedded in A set of optical images after PDMS. Figure 26: (A) Optical image of a GaAs-band MESFET with different strains on a PDMS stamp constructed in a PDMS substrate. The pre-application 150175.doc -76 - 201042951 applied to the PDMS seal before the devices were transferred to the surface of the PDMS stamp became 4.7%. (b) A comparison of the I-V curves of the apparatus shown before and after the system was applied with a 4.7% extension strain (A). Figures 27A-C provide images of the extendable semiconductor of the present invention exhibiting two-dimensional extensibility at different levels of magnification. Figures 28A-C provide images of three different structural configurations of the extendable semiconductor of the present invention showing two-dimensional extensibility. 29A-D provide images of the extensible semiconductor of the present invention prepared by pre-straining the elastic substrate by thermal expansion.

圖30展示在變化之延伸及壓縮狀態下展示二維可延伸性 之可延伸半導體的光學影像。 圖31A展示藉由熱膨脹來預應變彈性基板而製造之展示 二維可延伸性之可延伸半導體的光學影像。 圖3 1B及3 1C提供關於圖3 1A中展示之可延伸半導體之機 械性質的實驗結果。 【主要元件符號說明】 700 半導體元件 705 可撓性基板 710 支揮表面 715 彎曲半導體結構 720 曲線内表面 730 變形軸 750 凹入區域 760 起伏特徵 776 可印刷半導體結構 777 可撓性基板Figure 30 shows an optical image of an extensible semiconductor exhibiting two-dimensional extensibility in a varying extended and compressed state. Figure 31A shows an optical image of an extensible semiconductor exhibiting two-dimensional extensibility fabricated by pre-straining an elastic substrate by thermal expansion. Figures 3B and 3C provide experimental results regarding the mechanical properties of the extensible semiconductor shown in Figure 31A. [Main component symbol description] 700 Semiconductor component 705 Flexible substrate 710 Wrapping surface 715 Curved semiconductor structure 720 Curved inner surface 730 Deformation axis 750 Recessed area 760 Fluctuation characteristics 776 Printable semiconductor structure 777 Flexible substrate

G 150175.doc -77-G 150175.doc -77-

Claims (1)

201042951 七、申請專利範圍: 1. 一種可延伸半導體元件,其包含: 一具有一支撐表面之彈性基板;及 一具有一曲線内表面之半導體結構,其中該曲線内表 面之多個離散點係結合至該彈性基板的該支撐表面,且 結合之該等離散點藉由一沒有直接黏合至該彈性基板之 輕曲區域而彼此分開,其中該翹曲區域沒有與該基板實 體接觸。 ° 2·如請求項1之可延伸半導體元件,其中該翹曲區域係處 於應變下。 3·如請求項2之可延伸半導體元件,其中該應變係選 至30%之範圍。 4·如請求们之可延伸半導體元件,其中該曲線内表面具 有至少-凸起區域、至少一凹入區域或至少一凸起區域 與至少一凹入區域之一組合。 〇 5‘如請求項i之可延伸半導體元件,其中該曲線内表面具 有一包含一週期波或一無週期波之輪摩形狀。 6·::求項1之可延伸半導體元件,其中該想曲半導體結 形’該_波延伸該結構之長度的 至少一部分。 7.如請求項6之可延伸半導體 椹且士 千其中該翹曲半導體結 、有—正弦波構形’該正弦波構形具有一選自5微米 至50微米之範圍的週期及一 、 ’、 圍的振幅。 選自1〇〇奈米至微米之範 150175.doc 201042951 8. 如請求項1之可延伸半導體元件,其中該翹曲半導體結 構具有-包含沿該結構&lt;長度延伸的複數個勉曲之構 形。 9. 如凊求項!之可延伸半導體元件,其中該半導體結構包 含一帶。 10. 如請求们之可延伸半導體元件,其中該翹曲半導體結 構具有—在一維或二維中空間變化之構形,其中該内表 面具有一在一維或二維中空間變化之輪廓形狀。 Π.如請求項!之可延伸半導體元件,其中該半導體結構具 有一選自20奈米至320奈米之範圍的厚度。 12.如請求項丨之可延伸半導體元件,其中該彈性基板包含 一聚合物。 13_如請求項丨之可延伸半導體元件,其中該半導體結構係 一單晶無機半導體材料。 14.如請求項1之可延伸半導體元件,其中該半導體結構包 含一材料’該材料選自以下所組成之群組:矽,鍺,碳 化矽’磷化鋁,砷化鋁’銻化鋁,氮化鎵,磷化鎵,珅 化鎵’銻化鎵,磷化銦,砷化銦,銻化銦,氧化辞,硒 化鋅’碲化鋅’硫化鎘,硒化鎘,碲化鎘,硫化銀,硫 化鉛,硒化鉛’碲化鉛’鋁砷化鎵,鋁砷化銦,鋁碟化 銦,磷砷化鎵’砷化鎵銦’磷化鎵銦,砷碲化鋁鎵,磷 化紹鎵銦,神鱗化鎵銦,奈米碳管及石墨片。 1 5.如請求項1之可延伸半導體元件,其中該半導體結構包 含一可印刷半導體元件。 150175. doc 201042951 16. 如請求項1之可延伸半導體元件,進一步包含一與該具 有一曲線内表面之半導體結構接觸的囊封層。 17. 如請求項丨之可延伸半導體元件,其中該半導體結構經 由一定位於該半導體結構與該彈性基板之間的黏接層' 塗層或薄膜而結合至該彈性基板。 18. 如請求項1之可延伸半導體元件,其中該半導體結構經 由位於該半導體結構與該彈性基板之間的氫鍵、凡得瓦 爾力父互作用或偶極對偶極交互作用而結合至該性其 〇 板。 19. 如請求項1之可延伸半導體元件,包含複數個半導體結 構ΤΤΓ,每一帶具有一曲線内表面,其中該基板在該等帶 之間為平坦。 20·如請求項7之可延伸半導體元件,其中該週期及該振幅 在一 1平方公分之基板表面上的5%内係一致。 21. 如請求項2之可延伸半導體元件,其中該應變大於 0.5%。 Q 22. 如請求項2之可延伸半導體元件,其中該應變大於1%。 23·如請求項2之可延伸半導體元件,其中該應變大於2%。 24. 如請求項2之可延伸半導體元件,其中該應變小於3〇%。 25. 如請求項2之可延伸半導體元件,其中該應變小於1〇%。 26. 如請求項2之可延伸半導體元件,其中該應變小於1〇/〇。 27. —種可延伸電子電路,其包含: 一具有一支撐表面之彈性基板;及 一具有一曲線内表面之電子電路,其中該曲線内表面 150175.doc 201042951 之多個離散點係結合至該彈性基板的該支撐表面,且結 合之該等離散點藉由-沒有直接黏合至該彈性基板之勉 曲區域而彼此分開’其中該勉曲區域沒有與該基板實體 接觸。 28.如請求項27之可延伸電子電路,其中該電子電路係一可 印刷電子電路。 29·如請求項27之可延伸電子電路,其中該電子電路包含複 數個積體裝置組件’該複數個積體裝置組件選自由以下 所組成之群組半導體元件,—介電㈣,—電極, 一導電元件,及一摻雜半導體元件。 30.如請求項27之可延伸電子電路,其中該龜曲區域係處於 應變下。 3!•如請求項30之可延伸半導體元件,其中該應變料自ι% 至30%之範圍。 32·如請求項27之可延伸電子電路,其中該曲線内表面具有 -以-週期波或一無週期波為特徵之輪廓形狀。’、 33. 如請求項27之可延伸電子電路,其中該翹曲區域具有一 包含-週期波之構形’該週期波延伸該電子之 的至少一部分。 贫度 34. 如請求項27之可延伸電子電路,其中該翹曲區域且有— 正弦波構形,該正弦波構形具有—選自5微米至顺 之範圍的週期及-選自⑽奈米至1.5微米之範圍之# 其中該翹曲區域具有一 35.如請求項27之可延伸電子電路, 150I75.doc 201042951 包&quot;。該電子電路之長度延伸的複數個翹曲之構形。 36·如請求項27之可延伸電子電路,其中純曲區域具有一 在一維或二維中空間變化之構形,纟中該内表面具有一 在一維或二維中空間變化的輪廓形狀。 37.如δ月求項27之可延伸電子電路,其中該電子電路具有一 選自20奈米至320奈米之範圍的厚度。 38·如請求項27之可延伸電子電路,其中該電子電路經由一 :位於該電子電路與該彈性基板之間的黏接層、塗層或 薄膜而結合至該彈性基板。 39·如請求項27之可延伸電子電路,進一步包含一與該具有 一曲線内表面之電子電路接觸的囊封層。 40. -種用於製造-可延伸半導體元件之方法,該方法包含 以下步驟: 提供連接至一晶圓之複數個矽帶; 將5亥等矽Τ之一頂表面與一平坦預應變彈性基板保形 地接觸; 以一退離該晶圓之方向剝離該彈性基板以提升該等帶 與該晶圓分開,而黏接至該彈性基板; 在該彈性基板上釋放該預應變以產生在該等石夕帶中之 多個勉曲, 其中該等石夕帶具有—曲線内表面,其中該曲線内表面 之多個離散點係結合至該彈性基板的—切表面,且結 σ之該等離政點藉由—沒有直接黏合至該彈性基板之勉 曲區域而彼此分開。 150175.doc 201042951 41. 如請求項40用於製造一可延伸半導體元件之方法其中 該彈性基板在該等帶之間為平坦。 42. 如請求項40用於製造一可延伸半導體元件之方法其中 該可延伸半導體元件包含一 pn接面二極體。 43. 如請求項42用於製造一可延伸半導體元件之方法,其中 該pn接面二極體係一光伏打裝置之—部分。 44. 如請求項40用於製造一可延伸半導體元件之方法,其中 該可延伸半導體元件包含一場效電晶體。 45·如請求項4〇用於製造一可延伸半導體元件之方法,其中 該複數個石夕帶係藉由以下而提供: 在一絕緣體上石夕之晶圓上界定一光阻層,藉此界定該 複數個帶之尺寸; 移除該光阻層;及 藉由#刻將該等帶之一中央部公 了犬。丨刀從下面的該晶圓釋 放,而保持該帶的多個端部之連接至該晶圓。 46. —種用於製造一可延伸半導 心it干等镀兀件之雙重轉移方法,該 方法包含以下步驟: 提供連接至一晶圓之複數個矽帶; 將該等石夕帶之-頂表面與一平坦未應變彈性基板保形 地接觸; 以一遠離該晶圓之方向剝離該彈性基板以提升該等帶 與該晶圓分開,而黏接該等帶至該未應變彈性基板; 將點接至該未應變彈性基板之該等石夕帶之一頂表面與 一預應變彈性基板保形地接觸; 〃 150175.doc 201042951 以一遠離該未應變彈性基板之方向剝離該預應變彈性 基板以提升該等帶與該未應變彈性基板分開’而黏接該 等帶至該預應變彈性基板;及 在该彈性基板上釋放該預應變以產生在該等砂帶中之 多個勉曲, 其中該等石夕帶具有一曲線内表面,其中該曲線内表面 之多個離散點係結合至料性基板的—支揮表面,且結 合之該等離散點藉由—沒有直接黏合至該彈性基板之翹 曲區域而彼此分開。 150175.doc201042951 VII. Patent application scope: 1. An extendable semiconductor component comprising: an elastic substrate having a support surface; and a semiconductor structure having a curved inner surface, wherein a plurality of discrete points of the curved inner surface are combined To the support surface of the elastic substrate, and the discrete points combined are separated from each other by a soft curved region that is not directly bonded to the elastic substrate, wherein the warped region is not in physical contact with the substrate. The extensible semiconductor component of claim 1, wherein the warpage region is under strain. 3. The extensible semiconductor component of claim 2, wherein the strain system is selected to be in the range of 30%. 4. An extendable semiconductor component as claimed, wherein the inner surface of the curve has at least a raised region, at least one recessed region or at least one raised region combined with one of the at least one recessed region. 〇 5 'extensible semiconductor component of claim i, wherein the inner surface of the curve has a wheel shape comprising a periodic wave or a periodic wave. 6:: The extendable semiconductor component of claim 1, wherein the thinned semiconductor junction 'the wave extends at least a portion of the length of the structure. 7. The extensible semiconductor of claim 6 wherein the warped semiconductor junction has a sinusoidal configuration. The sinusoidal configuration has a period selected from the range of 5 microns to 50 microns and a ' , the amplitude of the circumference. The invention is the extensible semiconductor component of claim 1, wherein the warped semiconductor structure has a plurality of distorted structures extending along the length of the structure &lt; shape. 9. If you are asking for it! The extendable semiconductor component, wherein the semiconductor structure comprises a strip. 10. An extendable semiconductor component as claimed, wherein the warped semiconductor structure has a spatially varying configuration in one or two dimensions, wherein the inner surface has a contoured shape that varies spatially in one or two dimensions . Π. As requested! The extendable semiconductor component, wherein the semiconductor structure has a thickness selected from the range of 20 nm to 320 nm. 12. The extensible semiconductor component of claim 1, wherein the elastomeric substrate comprises a polymer. An extensible semiconductor device as claimed in claim 1, wherein the semiconductor structure is a single crystal inorganic semiconductor material. 14. The extensible semiconductor component of claim 1, wherein the semiconductor structure comprises a material selected from the group consisting of: tantalum, niobium, tantalum carbide 'aluminum phosphide, aluminum arsenide' aluminum telluride, Gallium nitride, gallium phosphide, gallium antimonide, gallium antimonide, indium phosphide, indium arsenide, indium antimonide, oxidation, zinc selenide, zinc telluride, cadmium sulfide, cadmium selenide, cadmium telluride, Silver sulfide, lead sulfide, lead selenide 'lead lead' aluminum gallium arsenide, aluminum indium arsenide, aluminum dish indium, phosphorus gallium arsenide ' gallium indium arsenide' gallium indium phosphide, arsenide aluminum gallium, Phosphine and gallium indium, squamous gallium indium, carbon nanotubes and graphite sheets. The extensible semiconductor component of claim 1, wherein the semiconductor structure comprises a printable semiconductor component. 150175. doc 201042951 16. The extendable semiconductor component of claim 1, further comprising an encapsulation layer in contact with the semiconductor structure having a curved inner surface. 17. The extensible semiconductor component of claim 1, wherein the semiconductor structure is bonded to the elastomeric substrate via an adhesive layer coating or film that is located between the semiconductor structure and the elastomeric substrate. 18. The extensible semiconductor component of claim 1, wherein the semiconductor structure is bonded to the property via a hydrogen bond, a van der Waals interaction, or a dipole-to-dipole interaction between the semiconductor structure and the elastic substrate. Its seesaw. 19. The extensible semiconductor component of claim 1 comprising a plurality of semiconductor structures, each strip having a curved inner surface, wherein the substrate is flat between the strips. 20. The extendable semiconductor component of claim 7, wherein the period and the amplitude are within 5% of a surface of the substrate of one square centimeter. 21. The extensible semiconductor component of claim 2, wherein the strain is greater than 0.5%. Q 22. The extensible semiconductor component of claim 2, wherein the strain is greater than 1%. 23. The extendable semiconductor component of claim 2, wherein the strain is greater than 2%. 24. The extensible semiconductor component of claim 2, wherein the strain is less than 3%. 25. The extensible semiconductor component of claim 2, wherein the strain is less than 1%. 26. The extensible semiconductor component of claim 2, wherein the strain is less than 1 〇/〇. 27. An extendable electronic circuit comprising: an elastic substrate having a support surface; and an electronic circuit having a curved inner surface, wherein a plurality of discrete points of the curved inner surface 150175.doc 201042951 are coupled to the The support surface of the elastic substrate, in combination with the discrete points, is separated from each other by - not directly bonded to the tortuous region of the elastic substrate, wherein the tortuous region is not in physical contact with the substrate. 28. The extendable electronic circuit of claim 27, wherein the electronic circuit is a printable electronic circuit. 29. The extendable electronic circuit of claim 27, wherein the electronic circuit comprises a plurality of integrated device components. The plurality of integrated device components are selected from the group consisting of: a group of semiconductor components, a dielectric (four), an electrode, a conductive element, and a doped semiconductor element. 30. The extendable electronic circuit of claim 27, wherein the tortuous zone is under strain. 3!• An extendable semiconductor component according to claim 30, wherein the strainer is in the range of from 1% to 30%. 32. The extendable electronic circuit of claim 27, wherein the inner surface of the curve has a contour shape characterized by a -periodic wave or a periodic wave. The extendable electronic circuit of claim 27, wherein the warped region has a configuration comprising a -periodic wave, the periodic wave extending at least a portion of the electron. </ RTI> 34. The extendable electronic circuit of claim 27, wherein the warped region has a sinusoidal configuration having a period selected from the range of 5 microns to cis and - selected from (10) m to the range of 1.5 μm where the warped region has a 35. The extendable electronic circuit of claim 27, 150I75.doc 201042951 package &quot;. A plurality of warped configurations in which the length of the electronic circuit extends. 36. The extendable electronic circuit of claim 27, wherein the pure curved region has a spatially varying configuration in one or two dimensions, wherein the inner surface has a contour shape that varies spatially in one or two dimensions. . 37. An extendable electronic circuit as in δ ig. 27, wherein the electronic circuit has a thickness selected from the range of from 20 nanometers to 320 nanometers. 38. The extendable electronic circuit of claim 27, wherein the electronic circuit is bonded to the elastic substrate via an adhesive layer, coating or film between the electronic circuit and the elastic substrate. 39. The extendable electronic circuit of claim 27, further comprising an encapsulation layer in contact with the electronic circuit having a curved inner surface. 40. A method for fabricating an extensible semiconductor device, the method comprising the steps of: providing a plurality of ribbons connected to a wafer; and top surface of a 5 Hz equivalent flat surface and a flat pre-strained elastic substrate Conformally contacting; stripping the elastic substrate in a direction away from the wafer to lift the strips apart from the wafer, and bonding to the elastic substrate; releasing the pre-strain on the elastic substrate to generate a plurality of distortions in the stone ribbon, wherein the stone ribbons have a curved inner surface, wherein a plurality of discrete points of the inner surface of the curve are bonded to the tangent surface of the elastic substrate, and the knots σ The detachment points are separated from each other by not directly bonding to the tortuous region of the elastic substrate. 150175.doc 201042951 41. The method of claim 40 for fabricating an extendable semiconductor component, wherein the flexible substrate is planar between the strips. 42. The method of claim 40, wherein the extensible semiconductor device comprises a pn junction diode. 43. A method as claimed in claim 42 for the manufacture of an extendable semiconductor component, wherein the pn junction diode system is a portion of a photovoltaic device. 44. The method of claim 40 for fabricating an extensible semiconductor device, wherein the extensible semiconductor device comprises a field effect transistor. 45. The method of claim 4, wherein the plurality of strips are provided by: defining a photoresist layer on a wafer on an insulator Defining the size of the plurality of strips; removing the photoresist layer; and engraving the central portion of the strip by #刻. The file is released from the underlying wafer while maintaining the connection of the ends of the strip to the wafer. 46. A dual transfer method for fabricating an extensible semi-conductive core, such as a rhodium-plated member, the method comprising the steps of: providing a plurality of ribbons connected to a wafer; The top surface is in conformal contact with a flat unstrained elastic substrate; the elastic substrate is peeled away from the wafer to lift the strips apart from the wafer, and the strips are bonded to the unstrained elastic substrate; The top surface of one of the strips of the strips that are connected to the unstrained elastic substrate is in conformal contact with a pre-strained elastic substrate; 〃 150175.doc 201042951 stripping the pre-strain elasticity in a direction away from the unstrained elastic substrate Substrate bonding the strips to the pre-strained elastic substrate by lifting the strips apart from the unstrained elastic substrate; and releasing the pre-strain on the elastic substrate to create a plurality of distortions in the abrasive strips Wherein the stone ribbon has a curved inner surface, wherein a plurality of discrete points of the inner surface of the curve are bonded to the surface of the material substrate, and the discrete points are combined by - no direct adhesion To warp the elastic region of the substrate separated from each other. 150175.doc
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