WO2012091498A1 - Flexible/stretchable semiconductor device comprising a graphene electrode, method for reducing contact resistance between a semiconductor layer and a graphene electrode, and graphene interconnector - Google Patents

Flexible/stretchable semiconductor device comprising a graphene electrode, method for reducing contact resistance between a semiconductor layer and a graphene electrode, and graphene interconnector Download PDF

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WO2012091498A1
WO2012091498A1 PCT/KR2011/010326 KR2011010326W WO2012091498A1 WO 2012091498 A1 WO2012091498 A1 WO 2012091498A1 KR 2011010326 W KR2011010326 W KR 2011010326W WO 2012091498 A1 WO2012091498 A1 WO 2012091498A1
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graphene
semiconductor layer
layer
electrode
contact resistance
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French (fr)
Korean (ko)
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안종현
홍병희
장석재
장호욱
이원호
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성균관대학교산학협력단
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Definitions

  • the present application relates to a flexible / stretchable semiconductor device comprising a graphene electrode, a method of reducing contact resistance between a semiconductor layer and a graphene electrode in the device, and a graphene interconnector.
  • TFTs Transparent and flexible thin-film transistors
  • Semiconducting materials such as organics, conductive oxides and carbon nanotubes are expected to be good candidates for potential applications [Ref .: Cao, Q; Zhu, ZT; Lemaitre, MG; Xia, MG; Shim, M .; Rogers, JA Appl. Phys. Lett. 2006, 88 , 113511.
  • ITO Indium Tin Oxide
  • the present inventors easily manufacture a graphene film having excellent electrical, optical, and mechanical properties to a large area, thereby easily manufacturing a large area graphene transparent electrode using a process such as transfer, patterning, and etching of the graphene film. And using such graphene, a flexible / stretchable substrate comprising a flexible and stretchable substrate, a semiconductor layer formed on the substrate, and a stretchable graphene electrode formed on the semiconductor layer. In the chuble semiconductor device and the device, a method of reducing contact resistance between the graphene electrode and the semiconductor layer is provided.
  • an object of the present invention is to provide a graphene interconnector and an electronic device having flexibility, flexibility, and transparency using the same.
  • a flexible (flexible) stretchable (stretchable) substrate a semiconductor layer formed on the substrate, and a stretchable graphene electrode formed on the semiconductor layer
  • a flexible / stretchable semiconductor device can be provided.
  • a method of reducing contact resistance between a semiconductor layer and a graphene electrode formed thereon (1) removing a native oxide film between the semiconductor layers before forming the graphene electrode, (2) the Forming a contact area between the graphene electrode and the semiconductor layer as wide as possible, (3) forming a buffer layer between the graphene electrode and the semiconductor layer, and (4) contact resistance on the graphene electrode
  • a method for reducing contact resistance between a semiconductor layer and a graphene electrode including one or more selected from the group consisting of forming a reduction layer.
  • a third aspect of the present application the elastic substrate; A plurality of elements formed on the elastic substrate; And a graphene interconnector interconnecting the plurality of devices.
  • the present application it is possible to provide a flexible / stretchable semiconductor device using a flexible and stretchable substrate and a stretchable graphene electrode, and in the above device, the semiconductor layer and the graphene formed thereon
  • the stretchable graphene electrode can be used to further improve the electrical characteristics of the flexible / stretchable semiconductor device.
  • the present invention can provide an electronic device having a graphene interconnect and stretch, flexibility and transparency using the same.
  • a flexible / stretchable semiconductor device having excellent flexibility in electrical and optical properties may be manufactured.
  • a large-area flexible silicon thin film semiconductor device can be easily manufactured, and in particular, the device can be easily manufactured in a flexible semi-transparent large area, and can be applied to various electric and electronic devices.
  • the flexible silicon thin film semiconductor device may be used as a thin film transistor, and thus may be applied to a liquid crystal display (LCD), a photovoltaic device, an organic light emitting device (OLED), a sensor, a memory, or an integrated circuit.
  • FIG. 1 is a schematic diagram illustrating a manufacturing process of a flexible / stretchable semiconductor device manufactured according to an exemplary embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram illustrating a manufacturing process of a flexible / stretchable semiconductor device manufactured according to an exemplary embodiment of the present disclosure.
  • FIG 3 is a cross-sectional view of a flexible / stretchable semiconductor device according to an embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view of a flexible / stretchable semiconductor device according to an embodiment of the present disclosure.
  • 5A and 5B are cross-sectional views of a flexible / stretchable semiconductor device according to one embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram illustrating a manufacturing process of a graphene electrode in a Si FET according to an embodiment of the present application.
  • 7A is an optical image of an array of hybrid TFTs manufactured according to one embodiment of the present application.
  • 7B is a graph showing optical light transmissivity of each portion of a device made according to one embodiment of the present disclosure.
  • FIG. 8A is a graph illustrating the performance of a device before and after BOE treatment under a 0.1 V drain voltage in a flexible / stretchable semiconductor device according to an embodiment of the present disclosure.
  • FIG. 8B is a graph showing resistance in the on- state (R on ) as a function of channel length at different gate voltages for a flexible / stretchable semiconductor device according to one embodiment of the present disclosure.
  • 9A is a graph illustrating transfer characteristics of a single crystal Si TFT using various electrodes including Cr / Au, graphene, and ITO according to an embodiment of the present disclosure.
  • FIG. 9B is a graph showing current-voltage characteristics of a device having a graphene electrode showing ohmic contact and resistance-independent current-voltage characteristics according to an embodiment of the present disclosure.
  • FIG. 10A illustrates sheet resistance before and after ITO annealing in a flexible / stretchable semiconductor device according to an exemplary embodiment of the present disclosure.
  • 10B is a graph of a probe measurement of a graphene electrode after transferring onto a SiO 2 wafer according to an embodiment of the present disclosure.
  • FIG. 11 is a graph showing on / off ratios of 10 4 , 10 5, and 10 2 in the flexible / stretchable semiconductor device manufactured in accordance with the example embodiment.
  • FIG. 11 is a graph showing on / off ratios of 10 4 , 10 5, and 10 2 in the flexible / stretchable semiconductor device manufactured in accordance with the example embodiment.
  • FIG. 12A illustrates a device before and during a bending test in a flexible / stretchable semiconductor device in accordance with one embodiment of the present application.
  • FIG. 12B illustrates a change in the performance of a transistor before bending, during bending, and after bending in a 20 mm radius corresponding to 0.4% tensile and compressive strain in a flexible / stretchable semiconductor device according to one embodiment of the present disclosure.
  • FIG. 13 is a graph showing electron transfer characteristics of a FET having a large contact area manufactured according to an embodiment of the present disclosure.
  • FIG 14 is a graph showing the transfer characteristics of the FET having a graphene electrode before and after the formation of Au nanoparticles prepared according to an embodiment of the present application.
  • FIG. 15 is a graph illustrating a transfer characteristic of a FET having graphene electrodes before and after forming an Au contact layer on a graphene thin film manufactured according to an embodiment of the present disclosure.
  • 16 is a cross-sectional view of an electronic device including a graphene interconnect in accordance with an embodiment of the present disclosure.
  • 17 is a cross-sectional view of an electronic device including a graphene interconnect in accordance with an embodiment of the present disclosure.
  • FIG. 18 is a cross-sectional view of an electronic device including a graphene interconnect in accordance with an embodiment of the present disclosure.
  • FIG. 19 is a cross-sectional view of an electronic device including a graphene interconnect in accordance with an embodiment of the present disclosure.
  • 20 is a diagram illustrating an electronic device pattern including a graphene interconnector according to an embodiment of the present disclosure.
  • 21 is a schematic diagram illustrating a method of manufacturing an electronic device including a graphene interconnector according to an embodiment of the present disclosure.
  • 22 is an image of an electronic device including a graphene interconnect according to one embodiment of the present disclosure.
  • FIG. 23 is a stretch test image of an electronic device including a graphene interconnector according to an embodiment of the present disclosure.
  • 24 is a graph showing a transfer curve of an electronic device including a graphene interconnector and a logarithmic scale according to an embodiment of the present disclosure.
  • 25 is a current-voltage curve of an electronic device including a graphene interconnect according to one embodiment of the present disclosure.
  • 26 is a graph illustrating electrical characteristics according to strain of an electronic device including a graphene interconnector according to an exemplary embodiment of the present disclosure.
  • a first aspect of the present application is a flexible / stretchable semiconductor, comprising a flexible and stretchable substrate, a semiconductor layer formed on the substrate, and a stretchable graphene electrode formed on the semiconductor layer.
  • An element can be provided.
  • the flexible and stretchable substrate may be polydimethylsiloxane (PDMS), polymethylmethacrylate (PMMA), polycarbonate, polyethylene, polypropylene (polypropylene) It may be selected from the group consisting of polyprolylene, polystyrene, polyimide, cyclo olefin copolymer (COC), parylene and combinations thereof, but is not limited thereto. no.
  • PDMS polydimethylsiloxane
  • PMMA polymethylmethacrylate
  • COC cyclo olefin copolymer
  • the semiconductor layer may be an organic semiconductor or an inorganic semiconductor, but is not limited thereto.
  • the inorganic semiconductor may be selected from, for example, Si, carbon nanotubes, graphene, compound semiconductors, oxide semiconductors, and combinations thereof, but is not limited thereto.
  • the oxide semiconductor is, for example, InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 , TiO 2 , Ta 2 O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5 , TiSrO 3 and combinations thereof However, it is not limited thereto.
  • the organic semiconductor may be, for example, pentacene, alpha-6T (alpha-sexithiophene), F-CuPc (hexadecafluorcopper phthalocyanine), P3HT [poly (3-hexylthiophene)], and combinations thereof. It may include one selected from the group consisting of, but is not limited thereto.
  • the natural oxide film may be removed using a solution including one selected from the group consisting of HF, NH 4 F, standard chemical 1 (SC1), PAN, and combinations thereof, but is not limited thereto. It doesn't happen.
  • the graphene electrode may be provided as a stretchable and transparent electrode, the graphene electrode, for example, to be prepared using a large area graphene film prepared by chemical vapor deposition method May be, but is not limited thereto.
  • graphene is an excellent conducting material that can move electrons 100 times faster than silicon and carry about 100 times more current than copper.
  • graphene has the advantage that it is very easy to process one-dimensional or two-dimensional nanopattern consisting of only a relatively light element of carbon, by using this can not only control the semiconductor-conductor properties of graphene but also has a carbon
  • the variety of chemical bonds allows the manufacture of a wide range of functional devices, including sensors and memories.
  • the graphene electrode may be a transfer of a large-area graphene film synthesized by chemical vapor deposition, a large-area graphene using a process such as patterning and transfer of the large-area graphene film
  • a pin transparent electrode or a large area transparent electrode pattern can be easily manufactured, and a large area flexible, stretchable semiconductor device can be easily manufactured using such a large area graphene electrode or a transparent electrode pattern.
  • the device can be applied to various flexible, stretchable transparent electrical and electronic devices
  • the graphene electrode may be grown by chemical vapor deposition by providing a carbon source and heat to the metal catalyst layer for graphene growth, but is not limited thereto.
  • the metal catalyst layer is one selected from the group consisting of Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Rh, Si, Ta, Ti, W, U, V and Zr, and stainless steel It may be to include the above, but is not limited thereto.
  • the metal catalyst layer may be in the form of a thin film, for example, about 1 nm to about 1,000 nm, about 1 nm to about 500 nm, about 1 nm to about 400 nm, or about 100 nm to about 400 nm thick It may be, but is not limited thereto.
  • the graphene film may be grown using the patterned metal catalyst layer, but is not limited thereto.
  • the transparent electrode may be made flexible by transferring the graphene film onto a transparent and / or flexible substrate or another transparent and / or flexible thin film.
  • the graphene film may be a transparent thin film having a thickness of about 0.1 nm to about 10 nm, but is not limited thereto.
  • the sheet resistance of the transparent electrode may be about 1 kW / sq to about 1,000 kW / sq, but is not limited thereto.
  • the transmittance of the transparent electrode may be about 70% or more, for example, about 70% or more to about 98% or less, but is not limited thereto.
  • the contact resistance between the semiconductor layer and the stretchable graphene electrode formed thereon may be reduced, and such contact resistance reduction may include (1) the Removing the native oxide film between the graphene electrode and the semiconductor layer, (2) forming the contact area with the semiconductor layer as wide as possible by the graphene electrode, (3) the graphene electrode and the semiconductor Forming a buffer layer between the layers, and (4) may be performed by a method comprising at least one selected from the group consisting of forming a contact resistance reducing layer on the graphene electrode, but is not limited thereto. .
  • the natural oxide film may be removed using a solution including one selected from the group consisting of HF, NH 4 F, standard chemical 1 (SC1), PAN, and combinations thereof, but is not limited thereto. It doesn't happen.
  • a method of reducing contact resistance between a semiconductor layer and a graphene electrode formed thereon (1) removing a natural oxide film between the graphene electrode and the semiconductor layer, and (2) the graphene. Forming a contact area between the pin electrode and the semiconductor layer as wide as possible, (3) forming a buffer layer between the graphene electrode and the semiconductor layer, and (4) reducing the contact resistance on the graphene electrode. It is possible to provide a method of reducing contact resistance between a semiconductor layer and a graphene electrode, including one or more selected from the group consisting of forming a layer.
  • the semiconductor layer may include an organic semiconductor or an inorganic semiconductor, but is not limited thereto.
  • each of the buffer layer and the contact resistance reducing layer in (3) and (4) may be formed including a conductive material, but is not limited thereto.
  • the conductive material may include one selected from the group consisting of ITO, IZO, Ti, Cu, Au, Pt, Ir, Cr, Mg, Ag, Ni, Al, and combinations thereof, but It is not limited.
  • an oxide film naturally generated between the semiconductor layer and the graphene electrode of the manufactured flexible / stretchable semiconductor device may be removed by treatment with a chemical solution.
  • the chemical solution for example, HF, NH 4 F, SC1 (standard chemical 1), but may be to include those selected from the group consisting of the PAN and combinations thereof, but is not limited thereto.
  • HF is used as a buffered oxide etch solution (BOE)
  • the ratio of HF and water may be used in a mixture of about 1: 200.
  • SC1 solution which is a mixture of NH 4 OH, H 2 O 2 , H 2 O, the mixture is mixed at a ratio of about 1: about 4: about 20 to about 40 ° C.
  • a buffered oxidizing solution having a ratio of NH 4 F and HF of about 7: about 1 is mixed with H 2 O at a ratio of about 1: about 5 to about 1: about 30: Can also be used.
  • the step of removing the oxide film naturally generated between the semiconductor layer and the graphene electrode of the flexible / stretchable semiconductor element by treatment with a chemical solution is as described above, after forming the graphene electrode.
  • the oxide film removing process may be performed, the oxide film formed after the semiconductor layer is formed may be removed by performing the oxide film removing process.
  • the semiconductor oxide film formed between the graphene electrode and the semiconductor layer was not removed, thereby increasing the contact resistance.
  • the resistance increase factor is caused by the removal of the natural oxide film, which is an insulating material, by the treatment with the chemical solution according to the present application. This can be removed. Therefore, the contact resistance between the graphene electrode and the semiconductor layer is reduced to improve the reliability of the device.
  • the contact resistance between the semiconductor layer and the graphene electrode may be reduced by increasing the contact area between the semiconductor layer and the graphene electrode.
  • the increase in the contact area between the semiconductor layer and the graphene electrode may be to form contact with the semiconductor layer in the widest possible area when the graphene electrode is formed, but is not limited thereto. no.
  • the source electrode and the drain electrode are formed using the graphene in the flexible / stretchable semiconductor device, the source electrode and the drain electrode are formed to cover the semiconductor layer as wide as possible. can do.
  • a buffer layer may be formed between the graphene electrode and the semiconductor layer to reduce contact resistance between the semiconductor layer and the graphene electrode.
  • the buffer layer may include a conductive material, and in particular, the conductive material may be a conductive material that is resistant to various etchant used during the device manufacturing process.
  • the conductive material may be selected from the group consisting of ITO, IZO, Ti, Cu, Au, Pt, Ir, Cr, Mg, Ag, Ni, Al, and combinations thereof, but is not limited thereto. It doesn't happen.
  • the buffer layer may have a thickness of several tens of nm. When the buffer layer including the conductive material is formed, the conductive material diffuses and penetrates into a defect of the natural vapor film between the semiconductor layer and the graphene electrode, thereby reducing contact resistance.
  • a contact resistance reduction layer may be formed on the graphene electrode to reduce the contact resistance of the graphene electrode.
  • the contact resistance reducing layer may be formed of a conductive material, and in particular, the conductive material may be a conductive material that is resistant to various etching liquids used in the device manufacturing process.
  • the conductive material may be selected from the group consisting of ITO, IZO, Ti, Cu, Au, Pt, Ir, Cr, Mg, Ag, Ni, Al, and combinations thereof, but is not limited thereto. It doesn't happen.
  • the contact resistance reducing layer may have a thickness of several tens of nm.
  • the contact resistance reduction layer formed on the graphene electrode is formed by using a conductive material resistant to an etchant that can be used in manufacturing the device, thereby adversely affecting the exposed graphene electrode by wet etching, that is, graphene. It may serve to prevent the occurrence of disconnection of the electrode due to damage to the electrode. Therefore, it is possible to compensate for the disadvantage that the characteristics of the semiconductor device decreases with time.
  • FIGS. 1 and 2 are schematic views showing a manufacturing process of a flexible, stretchable semiconductor device manufactured according to an embodiment of the present application.
  • the flexible, stretchable semiconductor device has a lower graphene electrode 21, 22, an insulator layer 31, 32 on a flexible, stretchable substrate 11, 12. ), And may include semiconductor layers 41 and 42, and may include oxide layers 41 ′ and 42 ′ that are naturally generated on the semiconductor layer 41.
  • the flexible and stretchable substrates 11 and 12 may be suitably used by those skilled in the art using materials known in the art, and may include polydimethylsiloxane (PDMS) and polymethylmethacrylate.
  • PDMS polydimethylsiloxane
  • PMMA polymethylmethacrylate
  • PMMA polycarbonate
  • polyethylene polyethylene
  • polyprolylene polystyrene
  • polyimide polyimide
  • parylene parylene
  • the semiconductor layers 41 and 42 may be organic semiconductors or inorganic semiconductors, but are not limited thereto.
  • the inorganic semiconductor may be selected from the group consisting of Si, carbon nanotubes, graphene, compound semiconductors, oxide semiconductors, and combinations thereof, wherein the oxide semiconductor is, for example, InGaZnO, ZnO.
  • the organic semiconductor may be formed of, for example, pentacene, alpha-6T (alpha-sexithiophene), F-CuPc (hexadecafluorcopper phthalocyanine), P3HT (poly (3-hexylthiophene)), and combinations thereof. It may be selected from the group.
  • the stretchable graphene electrodes 51 and 52 may be grown by chemical vapor deposition by providing a carbon source and heat to the metal catalyst layer for graphene growth, but are not limited thereto. It is not.
  • the metal catalyst layer is Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Rh, Si, Ta, Ti, W, U, V and Zr, and stainless It may include one or more selected from the group consisting of steel, but is not limited thereto.
  • the metal catalyst layer may be in the form of a thin film, for example, about 1 nm to about 1,000 nm, about 1 nm to about 500 nm, about 1 nm to about 400 nm, or about 100 nm to about 400 nm thick It may be, but is not limited thereto.
  • the graphene film may be grown using the patterned metal catalyst layer, but is not limited thereto.
  • the transparent electrode may be made flexible by transferring the graphene film onto a transparent and / or flexible substrate or another transparent and / or flexible thin film.
  • the graphene film may be a transparent thin film having a thickness of about 0.1 nm to about 10 nm, but is not limited thereto.
  • the sheet resistance of the graphene electrode may be about 1 kW / sq to about 1,000 kW / sq, but is not limited thereto.
  • the permeability of the graphene electrode may be about 70% or more, for example, about 70% or more to about 98% or less, but is not limited thereto.
  • the oxide film 41 ′ naturally formed on the semiconductor layer 41 or the graphene electrode 52 of the manufactured flexible / stretchable semiconductor device is removed by a treatment using a chemical solution.
  • the chemical solution may be selected from the group consisting of HF, NH 4 F, standard chemical 1 (SC1), PAN, and combinations thereof.
  • SC1 buffered oxide etch solution
  • the ratio of HF and water may be used in a mixture of about 1: 200.
  • SC1 solution which is a mixture of NH 4 OH, H 2 O 2 , H 2 O
  • the mixture is mixed at a ratio of about 1: about 4: about 20 to about 40 ° C. to about 80 ° C.
  • H 2 O 2 is mixed at a ratio of about 19: 1 to about 65 ° C. It can be used by etching for about 30 minutes.
  • a buffered oxidizing solution (BOE) having a ratio of NH 4 F and HF of about 7: about 1 is mixed with H 2 O at a ratio of about 1: about 5 to about 1: about 30: Can also be used.
  • the process of removing the oxide film 41 ′ naturally generated on the semiconductor layer 41 of the flexible / stretchable semiconductor device by treatment with a chemical solution is shown in FIG. 1.
  • the oxide film 41 ′ formed after the formation of the 41 may be subjected to the oxide film removing process and the graphene electrode 52 may be formed, as shown in FIG. 2, the graphene electrode 52 is formed and patterned. After that, a process of removing the naturally occurring oxide film 42 'may be performed.
  • the semiconductor oxide film formed between the graphene electrode and the semiconductor layer was not removed and became a factor of increasing the contact resistance
  • the natural oxide films 41 'and 42' which are insulating films, were treated by the chemical solution according to the present application. As this is eliminated, the resistance increasing factor can be eliminated. Therefore, the contact resistance between the graphene electrodes 51 and 52 and the semiconductor layers 41 and 42 may be reduced, thereby improving reliability of the device.
  • the flexible / stretchable semiconductor device includes a lower graphene electrode 23, an insulator layer 33, a semiconductor layer 43, and an upper graphene on the flexible / stretchable substrate 13.
  • An electrode 53 may be included, and a contact area between the semiconductor layer 43 and the upper graphene electrode 53 may be increased.
  • the flexible, stretchable substrate 13 may comprise polydimethylsiloxane (PDMS), polymethylmethacrylate (PMMA), polycarbonate, polyethylene, poly It may be selected from the group consisting of propylene (polyprolylene), polystyrene, polyimide, cyclo olefin copolymer (COC), parylene and combinations thereof, but is not limited thereto. It doesn't happen.
  • PDMS polydimethylsiloxane
  • PMMA polymethylmethacrylate
  • COC cyclo olefin copolymer
  • the semiconductor layer 43 may be an organic semiconductor or an inorganic semiconductor, but is not limited thereto.
  • the contact area increase may be to form the graphene electrode in the semiconductor layer, but is not limited thereto.
  • the flexible / stretchable semiconductor device includes a lower graphene electrode 24, an insulator layer 34, a semiconductor layer 44, and an upper graphene on the flexible / stretchable substrate 14. It may include a pin electrode 54, and may include a buffer layer 44 ′ deposited between the semiconductor layer 44 and the upper graphene electrode 54.
  • the flexible / stretchable semiconductor device includes a lower graphene electrode 25, an insulator layer 35, a semiconductor layer 45, and an upper graphene on the flexible / stretchable substrate 15. It may include a pin electrode 55, it may include a contact resistance reduction layer 55 'deposited on the graphene electrode 55.
  • the lower graphene electrode 26 and the insulator layer 36 are included on the flexible / stretchable substrate 16, and the semiconductor layer 46, such as an oxide or silicon, is formed.
  • a structure in which the contact resistance reduction layer 56 ′ is deposited on the source-drain and the wiring lines may be formed to improve conductivity.
  • the contact resistance reduction layer 56 ′ may be manufactured using a metal, and the contact resistance reduction layer 56 ′ using the metal may be formed by vacuum deposition or electroplating using a solution, or a self-assembly method.
  • the advantage of this structure is that it can prevent the penetration of ions and gases into the semiconductor layer and improve the conductivity.
  • the flexible / stretchable substrates 14, 15, and 16 may be made of polydimethylsiloxane (PDMS), polymethylmethacrylate (PMMA), polycarbonate, polyethylene ( polyethylene, polyprolylene, polystyrene, polyimide, cyclo olefin copolymer (COC), parylene, and combinations thereof.
  • PDMS polydimethylsiloxane
  • PMMA polymethylmethacrylate
  • COC cyclo olefin copolymer
  • parylene parylene
  • the semiconductor layer 44, 45, 46 may be an organic semiconductor or an inorganic semiconductor, but is not limited thereto.
  • each of the buffer layer 44 ′ and the contact resistance reducing layer 55 ′ and 56 ′ may be a conductive material resistant to an etchant, but is not limited thereto.
  • the conductive material may be selected from, for example, ITO, IZO, Ti, Cu, Au, Pt, Ir, Cr, Mg, Ag, Ni, Al, and combinations thereof, but is not limited thereto. no.
  • each of the buffer layer 44 'and the contact resistance reducing layer 55', 56 ' is formed using a conductive material including a metal, between the graphene electrodes 54, 55, 56 or graphene electrode
  • the metal molecules or particles of the conductive material may be diffused on (54, 55, 56) so that metal atoms remain between the graphene electrodes or on the graphene electrodes, thereby reducing contact resistance.
  • each of the contact resistance reducing layers 55 'and 56' is formed using a conductive material resistant to an etchant, thereby adversely affecting the exposed graphene electrodes 55 and 56 by wet etching, that is, graphene. It may serve to prevent the disconnection of the electrode due to the damage of the electrodes (55, 56). Therefore, it is possible to compensate for the disadvantage that the characteristics of the semiconductor device decreases with time.
  • a third aspect of the present application the elastic substrate; A plurality of elements formed on the elastic substrate; And a graphene interconnector interconnecting the plurality of devices.
  • the plurality of elements formed on the elastic substrate of the electronic device according to the third aspect of the present application may include the flexible / stretchable semiconductor element according to the first aspect of the present application, and the flexible / stretchable
  • the semiconductor device may include, but is not limited to being formed by a method of reducing the contact resistance between the semiconductor layer and the graphene electrode according to the second aspect of the present application.
  • the graphene interconnector may be formed of a doped graphene layer, but is not limited thereto.
  • the graphene interconnector may be formed by stacking a plurality of graphene layers, but is not limited thereto.
  • the graphene interconnector may be formed including a graphene layer and metal nanoparticles deposited on the graphene layer, but is not limited thereto.
  • the metal nanoparticles are Ag, Au, Pt, Pd, Fe, Ni, Al, Sb, W, Tb, Dy, Gd, Eu, Nd, Pr, Sr, Mg, Cu, Zn, Co, Mn , Cr, V, Mo, Zr, Ba and combinations thereof may be selected from, but is not limited thereto.
  • the graphene interconnector may be formed by alternately stacking a plurality of metal nanoparticles and a graphene layer, but is not limited thereto.
  • the metal nanoparticles are Ag, Au, Pt, Pd, Fe, Ni, Al, Sb, W, Tb, Dy, Gd, Eu, Nd, Pr, Sr, Mg, Cu, Zn, Co, Mn , Cr, V, Mo, Zr, Ba and combinations thereof may be selected from, but is not limited thereto.
  • the elastomer substrate is a thermoplastic elastomer, styrenic materials, olefenic materials, polyolefins, polyurethane thermoplastic elastomers , Polyamides, synthetic rubbers, polydimethylsiloxane (PDMS), polybutadiene, polyisobutylene, poly (styrene-butadiene-styrene) (poly (styrene- butadiene-styrene)), polyurethane (polyurethanes), polychloroprene (polychloroprene), silicone and combinations thereof may be selected from the group consisting of, but is not limited thereto.
  • PDMS polydimethylsiloxane
  • PDMS polybutadiene
  • polyisobutylene poly (styrene-butadiene-styrene) (poly (styrene- butadiene-styrene)), polyurethan
  • the elastic substrate may be deformed at a strain of about 1% to about 30%, but is not limited thereto. Deforming the elastic substrate may apply an external force.
  • the elastic substrate can be deformed by bending, rolling, bending or expanding. Deformation of the elastomer substrate may also be achieved by thermal expansion caused by raising the temperature of the elastomer substrate through a thermal method.
  • the graphene interconnector connecting two devices may be formed of a doped graphene layer.
  • the dopant added to the graphene layer may be, for example, a P-type dopant or an N-type dopant, but is not limited thereto. Pure graphene does not have a bandgap, but dopant-added graphene has a bandgap, which makes it possible to control the electronic structure. Therefore, it is very useful for making devices such as field effect transistors.
  • the dopant is an ionic liquid, ionic base, and may be used at least one selected from acids compounds and the group consisting of an organic molecular compounds, the dopant may be, for example, NO 2 BF 4 , NOBF 4 , NO 2 SbF 6 , HCl, H 2 PO 4 , H 3 CCOOH, H 2 SO 4 , HNO 3 , AuCl 3, Nafion, SOCl 2 , Br 2 , polyvinylidene fluoride (PVDF), dichloro One or more selected from the group consisting of dicyanoquinone, oxone, dimyristoyl phosphatidylinositol and trifluoromethanesulfonimide may be used, but is not limited thereto.
  • PVDF polyvinylidene fluoride
  • the graphene interconnector connecting two devices may be formed by stacking graphene layers.
  • the graphene layer may be grown by chemical vapor deposition (CVD) by providing a carbon source and heat to the transition metal catalyst layer for graphene growth.
  • CVD chemical vapor deposition
  • the transition metal catalyst layer is Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Rh, Si, Ta, Ti, W, U, V, Zr, stainless steel and these May be selected from the group consisting of.
  • the number of layers of graphene may be controlled by repeating the transfer process.
  • the sheet resistance increases from about 500 mW / sq to about 50 mW / sq to about 300 mW / sq to about 10 mW / sq as the number of layers of graphene increases to one, two, and three layers.
  • the transmittance may decrease from about 97.1% to about 91.2% for light with a wavelength of about 550 nm.
  • the chemical vapor deposition method may include rapid thermal chemical vapor deposition (RTCVD), inductively coupled plasma-chemical vapor deposition (ICP-CVD), low pressure chemical vapor deposition; LPCVD), atmospheric pressure chemical vapor deposition (APCVD), metal organic chemical vapor deposition (MOCVD), and plasma-enhanced chemical vapor deposition (PECVD) methods. It may include, but is not limited to now.
  • RTCVD rapid thermal chemical vapor deposition
  • ICP-CVD inductively coupled plasma-chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • APCVD atmospheric pressure chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • PECVD plasma-enhanced chemical vapor deposition
  • the graphene may grow graphene by adding a gaseous carbon source and heat treating the metal catalyst layer.
  • a metal catalyst layer is placed in a chamber and a carbon source such as carbon monoxide, ethane, ethylene, ethanol, acetylene, propane, butane, butadiene, pentane, pentene, cyclopentadiene, hexane, cyclohexane, benzene, toluene, etc.
  • a carbon source such as carbon monoxide, ethane, ethylene, ethanol, acetylene, propane, butane, butadiene, pentane, pentene, cyclopentadiene, hexane, cyclohexane, benzene, toluene, etc.
  • heat treatment is performed at a temperature of about 300 ° C. to about 2000 ° C.
  • graphene is generated while the carbon components present in the carbon source combine to form a hexagon
  • the method of forming the graphene on the metal catalyst layer is not limited to the chemical vapor deposition method, and in the exemplary embodiment of the present application, any method of forming the graphene on the metal catalyst layer may be used, and the present application may be performed on the metal catalyst layer. It will be appreciated that it is not limited to any particular method of forming graphene in.
  • the graphene interconnector connecting two devices may be formed by depositing metal nanoparticles.
  • the metal nanoparticles are Ag, Au, Pt, Pd, Fe, Ni, Al, Sb, W, Tb, Dy, Gd, Eu, Nd, Pr, Sr, Mg, Cu, Zn, Co, Mn , Cr, V, Mo, Zr, Ba and combinations thereof may be selected.
  • the graphene interconnector connecting between two devices may be formed by alternately stacking a plurality of metal nanoparticles and a graphene layer.
  • the metal nanoparticles are Ag, Au, Pt, Pd, Fe, Ni, Al, Sb, W, Tb, Dy, Gd, Eu, Nd, Pr, Sr, Mg, Cu, Zn, Co, Mn , Cr, V, Mo, Zr, Ba and combinations thereof may be selected.
  • the graphene interconnector When the length of the graphene interconnector becomes longer, there may be a problem due to the resistance generated in the graphene interconnect.
  • a dopant is added to the graphene, the graphene layer is laminated in multiple layers, The metal nanoparticles may be deposited on the graphene layer, and the metal nanoparticles and the graphene layer may be stacked a plurality of times to form a sandwich structure to reduce resistance.
  • FIG. 20 is a diagram illustrating an electronic device pattern according to an embodiment of the present disclosure.
  • a white rectangular pattern is a portion into which one element enters, and each of these elements is connected by an intermediate interconnect.
  • a circular pattern can be formed to absorb stress at the part where the pad and interconnect are connected to prevent the stress from being concentrated and broken.
  • Electronic devices according to the present invention can effectively integrate numerous functional devices and device components such as transistors, diodes, lasers, MEMS, NEMS, LEDS and OELDS.
  • the electronic device according to the invention has certain functional advantages over conventional rigid inorganic semiconductors.
  • First, electronic devices can be flexible, so they accept less structural damage caused by bending, bending and / or deformation than conventional rigid inorganic semiconductors.
  • the electronic devices herein can provide excellent thermal properties because they can freely expand and contact with device temperature cycling.
  • FIG. 6 is a schematic diagram illustrating a manufacturing process of Si FET based graphene.
  • Fabrication of TFTs forms a Ni catalyst layer of about 500 nm thickness on a SiO 2 / Si substrate having a thickness of at least 300 nm on top, and a gas mixture (CH 4 : H 2 : Ar containing a carbon source on the Ni catalyst layer). 50: 65: 200 sccm)
  • the graphene film was grown on the Ni catalyst layer in a quartz tube of 4 inches in diameter at 950 ° C under a supply.
  • the grown graphene film was about six layers, measured by optical transparency.
  • the sheet resistance of the graphene thin film was measured by 370 ⁇ 10 ⁇ / sq by a four-point probe.
  • the graphene thin film on the Ni / SiO 2 / Si wafer was transferred to PET ( ⁇ 200 ⁇ m) as a lower gate electrode.
  • Preparation of the Si channel material began by designating doped contact regions on a silicon-on-insulator (SOI) wafer (SOITEC Unibond; 100 nm thick upper single crystal silicon thin film, resistivity of 13.5-22.5 cm 3).
  • SOI silicon-on-insulator
  • the region designated as the SiO 2 mask ( ⁇ 100 nm) was coated with a phosphorus dopant such as P509 (Filmtronics) via a spin-on-dopant (SOD) method and subsequently annealed at 950 ° C. for 5 seconds.
  • P509 Fintronics
  • Doping concentration was determined to be 2 x 10 18 cm -3 by a hole measuring system.
  • the upper Si layer ⁇ 100 nm was transferred to the photosensitive epoxy layer ( ⁇ 500 nm thickness as a role of the adhesive layer and the gate electrode using a transfer printing method using a polydimethylsiloxane (PDMS) stamp. Transfer to a PET coated graphene gate electrode with a dielectric constant of ⁇ 3.1).
  • PDMS polydimethylsiloxane
  • the silicon oxide layer under the single crystal silicon thin film is removed by etching using a BOE solution, and then the single crystal silicon layer is epoxy number of the PET / graphene / epoxy resin laminate through a stamping method using a photocurable polymer material. Transcribed onto strata.
  • the single crystal silicon pattern was formed as a channel layer by removing and patterning the single crystal silicon layer in the remaining regions except for the region where the semiconductor element is formed.
  • a separate transparent graphene film prepared by the same method as described above was contacted with the PDMS stamp, and then transferred onto the epoxy resin layer by a stamping method.
  • a transparent semi-transparent silicon thin film semiconductor device was completed by forming a transparent source / drain electrode pattern electrically contacting each silicon region on the single crystal silicon thin film pattern through photolithography and etching.
  • the graphene film having a region of 1 cm x 1 cm to move the Si It was used as a source-drain electrode using a dry printing method similar to the method used to.
  • the transfer yield of Si and graphene was at least 99%.
  • the source-drain pattern was formed to a thickness of 1.2 mu m by an oxygen plasmman reactive ion etching process using a photoresist (AZ5214) mask pattern.
  • the enlarged image in FIG. 6 shows a schematic view of the manufactured device.
  • 7A shows an optical image of an array of hybrid TFTs positioned over the SKKU logo to show the level of optical translucency and mechanical flexibility.
  • 7b shows the optical light transmissivity of each part of the device between wavelengths of 400 and 800 nm.
  • the light transmittances of the Si channel region (Si / epoxy / graphene) and source / drain region (graphene / Si / epoxy / graphene) at 550 nm excluding the PET substrate influence are 52% and 38%, respectively.
  • Light transmission through the Si layer exhibits a rational fringe pattern caused by interference between the top and bottom surfaces of the silicon.
  • the light transmittance of the source / drain at 550 nm is the light in the channel region due to the graphene film corresponding to the six layers of graphene, since a single graphene layer leads to a 2.3% reduction in optical light transmittance in the visible wavelength range. 14% lower than light transmittance.
  • the quality of the graphene film was confirmed by Raman spectroscopy. Raman spectra taken from graphene films on SiO 2 substrates, such as graphene films on epoxy / PET substrates, show weak bond related D-band peaks indicating good overall graphene film quality.
  • 8A shows the performance of the device before and after BOE treatment under 0.1 V drain voltage.
  • the device shows a big difference before and after BOE treatment due to contact resistance.
  • 8B shows the resistance in the on- state R on as a function of channel length at different gate voltages. As determined from the intercept of the linear fit of R on vs L c , the contact resistance measured before BOE treatment was about 300 k ⁇ , while 2.5 k ⁇ after BOE treatment.
  • a thin film of gold was deposited in the center of the graphene electrode to find out why native oxide induces huge contact resistance when graphene is used as an S / D electrode, and why not.
  • the drastically improved device performance is due to the reduction in contact resistance.
  • This phenomenon can be explained by the change in the amount and work function of the carrier. Since graphene is an ultra-thin material, its thickness is similar to that of natural oxide, and the amount of charge carriers in graphene is not sufficient to tunnel through the native oxide. In addition, the change of the work function of graphene was observed in the natural oxide film before and after the deposition of silicon and gold.
  • FIG. 9A shows the transfer of a single crystal Si TFT using various electrodes each including Cr / Au (1), graphene (2) and ITO (3) having a channel length of 20 ⁇ m and a width of 50 ⁇ m under a drain voltage of 0.1 V.
  • FIG. A graph showing the characteristics, and the inset of FIG. 9A shows an optical microscope image of a device using graphene electrodes.
  • Devices using ITO as electrodes show mobility of 2 cm 2 / Vs and threshold voltages of 0.5 V, while devices using Cr / Au and graphene as electrodes move 350 cm 2 / Vs and 320 cm 2 / Vs
  • the diagrams show the 1 V and 2.5 V threshold voltages, respectively.
  • 10A is a view showing sheet resistance before and after ITO annealing in the flexible / stretchable semiconductor device according to this embodiment
  • FIG. 10B is a graph of probe measurement of graphene electrodes after transferring onto a SiO 2 wafer according to this embodiment. to be.
  • the device using the ITO electrode showed very low characteristics compared with the device using Cr / Au and graphene, which shows a high sheet resistance compared to the graphene (FIGS.
  • FIG. 11 is a log scale transfer curve of a device using various electrodes including Cr / Au (1), ITO (2) and graphene (3) each having a channel length of 20 ⁇ m and a width of 50 ⁇ m. Each device exhibits an on / off ratio of 10 4 , 10 2, and 10 5 .
  • graphene-based Si TFTs have excellent mechanical flexibility due to the robust bending characteristics of graphene electrodes. Bending tests were performed to verify the mechanical properties of these devices. 12A shows the device before and during the bending test. FIG. 12B shows the change in transistor performance before, during and after bending to a 20 mm radius corresponding to 0.4% tensile and compressive strain. Effective device mobility in the linear fashion was normalized to the value observed in the unfolded state ⁇ 0off as a function of deformation and bending radius. For this range of modifications, the device exhibited stable operation without significant change in ⁇ off / ⁇ 0eff . This suggests that graphene-based silicon transistors exhibit stable operation under high strain.
  • a semiconductor device was fabricated in the same manner as in Example 1 except that the graphene thin film was deposited with a 450 ⁇ m area. 13 is a graph showing the transfer characteristics of a FET having a large contact area manufactured according to the present embodiment.
  • Example 14 is a graph showing the transfer characteristics of the FET having graphene electrodes before and after the formation of Au nanoparticles prepared according to the present embodiment.
  • the semiconductor device was fabricated in the same manner as in Example 1, but by depositing Au 40 nm as a contact resistance reducing material on the graphene thin film.
  • 15 is a graph showing the transfer characteristics of the FET having graphene electrodes before and after the formation of the Au contact layer on the graphene thin film prepared according to the present embodiment.
  • FIG. 21 is a schematic view showing a method of manufacturing an electronic device according to the present embodiment.
  • the silicon layer after the doping process high temperature process
  • the base substrate using germanium and silicon oxide as a sacrificial layer using Su-8 as an adhesive layer
  • graphene is deposited on the base substrate to form an electrode and an interconnect
  • SU-8 is applied and patterned on the device as a protective layer
  • germanium which is a sacrificial layer below, is added to and removed from the water to float the device, and then peeled off with a rubber stamp (FIG. 21 (c)).
  • FIG. 21 (d) An image of the completed electronic device is shown in FIG. 22.
  • FIG. 23 is a stretching test image of the electronic device according to the present embodiment.
  • FIG. 23A At 0% strain of the rubber substrate, since the elements have a compressive strain, wrinkles are formed and compressed in the interconnect portion (FIG. 23A).
  • FIG. 23 (b) When pulled up to 10%, the tensile strain is greater than the compressive strain, and the interconnect portion is pulled tight, and the Poisson effect causes the compressive stress to be applied in a direction perpendicular to the direction in which the tensile strain is applied to further crease the inside of the pad ( Figure 23 (c)).
  • FIG. 23C It can be seen from FIG. 23C that substantial strain is applied to the interconnect. It may be possible to withstand these substantial strains because of the graphene interconnect.
  • 24 is a graph showing a transmission curve 2 of the electronic device according to the present embodiment and a log scale 1.
  • 25 is a current-voltage curve of the electronic device according to the present embodiment.
  • 26 is a graph showing electrical characteristics according to strain of the electronic device according to the present embodiment. As shown in FIG. 26, even when the strain of the rubber substrate is applied up to 10% and again down to 0%, the electrical properties hardly change.

Abstract

The present invention relates to a flexible/stretchable semiconductor device comprising a graphene electrode, to a method for reducing contact resistance between a semiconductor layer and the graphene electrode in the semiconductor device, and to a graphene interconnector.

Description

그래핀 전극을 포함하는 플렉시블/스트레처블 반도체 소자, 반도체층과 그래핀 전극 사이의 접촉저항 감소 방법, 및 그래핀 인터커넥터Flexible / stretchable semiconductor device including graphene electrode, method of reducing contact resistance between semiconductor layer and graphene electrode, and graphene interconnector
본원은 그래핀 전극을 포함하는 플렉시블/스트레처블 반도체 소자, 상기 소자에 있어서 반도체층과 그래핀 전극 사이의 접촉저항을 감소시키는 방법, 및 그래핀 인터커넥터에 관한 것이다.The present application relates to a flexible / stretchable semiconductor device comprising a graphene electrode, a method of reducing contact resistance between a semiconductor layer and a graphene electrode in the device, and a graphene interconnector.
투명 및 플렉시블 박막트랜지스터(thin-film transistors; TFTs)는 인공 스킨 및 구부릴 수 있는 헤드 업 디스플레이 디바이스(bendable head-up display devices)와 같은 많은 응용 분야에서 높은 관심을 끌어왔다[참고문헌: Cao, Q.; Hur, S. H.; Zhu, Z. T.; Sun, Y.; Wang, C.; Meitl, M. A.; Shim, M.; Rogers, J. A. Adv. Mater. 2006, 18, 304-309]. 유기물, 전도성 산화물 및 탄소나노튜브와 같은 반도성 물질들이 잠재적인 응용을 위한 좋은 후보로 기대된다[참고문헌: Cao, Q; Zhu, Z. T.; Lemaitre, M. G.; Xia, M. G.; Shim, M.; Rogers, J. A. Appl. Phys. Lett. 2006, 88, 113511].Transparent and flexible thin-film transistors (TFTs) have attracted high interest in many applications such as artificial skins and bendable head-up display devices [Cao, Q] .; Hur, SH; Zhu, ZT; Sun, Y .; Wang, C .; Meitl, MA; Shim, M .; Rogers, JA Adv. Mater. 2006, 18, 304-309. Semiconducting materials such as organics, conductive oxides and carbon nanotubes are expected to be good candidates for potential applications [Ref .: Cao, Q; Zhu, ZT; Lemaitre, MG; Xia, MG; Shim, M .; Rogers, JA Appl. Phys. Lett. 2006, 88 , 113511.
그러나, 이러한 물질로 만든 디바이스에서 낮은 캐리어 이동도 및 상대적으로 낮은 신뢰성으로 인하여 고성능 투명 및 플렉시블 전자장치를 이루는데 어려움이 있었다. 최근에, 몇몇의 연구 그룹은 100 nm 이하의 초박막 두께로 반투명 특성을 가진 고성능 플렉시블 전자장치를 위한 독립 구조의 단결정 실리콘 리본/멤브레인을 개발했다[참고문헌: Menard, E.; Nuzzo, R. G.; Rogers J. A. Appl. Phys. Lett. 2005, 86, 093507]. 이러한 디바이스의 장점 중 하나는 디바이스의 전기적, 광학적 특성 및 기계적 유연성에 중요한 역할을 하는 소스/드레인 및 게이트 전극이다. 투명 전극용 재료로서 높은 전도도 및 우수한 광투과도를 지닌 ITO(Indium Tin Oxide)가 자주 응용된다. 그러나, ITO의 고유의 기계적인 결점 및 고온 공정은 플렉시블 전자장치 시스템에서 사용에 적합하지 않다[참고문헌: Bae, S.; Kim, H. K.; Lee, Y.; Xu, X.; Park, J. S.; Zheng, Y.; Balakrishnan, J.; Im, D.; Lei, T.; Song, Y. I.; Kim, Y. J.; Kim, K. S.; Ozyilmaz, B; Ahn, J. H.; Hong, B. H.; Iijima, S. Nat. Nanotechnol. 2010, online]. 또한, 금속 박막은 또 다른 후보이지만 금속 박막은 그들의 낮은 광투광성 때문에 투명 전극 응용에 제한적이다[참고문헌: Fan, Z.; Razavi, H.; Do, J. W.; Moriwaki, A.; Ergen, O.; Chueh, Y. L.; Leu, P. W.; Ho, J. C.; Takahashi, T.; Reichertz, L. A.; Neale, S.; Yu, K.; Wu, M.; Ager, J. W.; Javey, A. Nat. Mater, 2009, 8, 648-653]. However, low device mobility and relatively low reliability in devices made of these materials have made it difficult to achieve high performance transparent and flexible electronics. Recently, several research groups have developed free-standing single crystal silicon ribbons / membranes for high performance flexible electronics with translucent properties with ultra-thin thicknesses of less than 100 nm [Menard, E .; Nuzzo, RG; Rogers JA Appl. Phys. Lett. 2005, 86 , 093507]. One of the advantages of such devices is source / drain and gate electrodes that play an important role in the electrical, optical properties and mechanical flexibility of the device. Indium Tin Oxide (ITO), which has high conductivity and excellent light transmittance, is frequently used as a material for transparent electrodes. However, the inherent mechanical drawbacks and high temperature processes of ITO are not suitable for use in flexible electronic systems [Ref .: Bae, S .; Kim, HK; Lee, Y .; Xu, X .; Park, JS; Zheng, Y .; Balakrishnan, J .; Im, D .; Lei, T .; Song, YI; Kim, YJ; Kim, KS; Ozyilmaz, B; Ahn, JH; Hong, BH; Iijima, S. Nat. Nanotechnol. 2010 , online ]. In addition, metal thin films are another candidate, but metal thin films are limited to transparent electrode applications because of their low light transmission [Ref. Fan, Z .; Razavi, H .; Do, JW; Moriwaki, A .; Ergen, O .; Chueh, YL; Leu, PW; Ho, JC; Takahashi, T .; Reichertz, LA; Neale, S .; Yu, K .; Wu, M .; Ager, JW; Javey, A. Nat. Mater , 2009, 8 , 648-653.
한편, 그래핀/무기 하이브리드 시스템이 반도체, 디스플레이 및 에너지 디바이스와 같은, 실용적 전자장치 응용에 대한 관심이 증가하고 있으나, 그래핀 필름을 무기재료와 통합함에 있어서 여전히 중요한 과제이다.On the other hand, while graphene / inorganic hybrid systems have increased interest in practical electronics applications such as semiconductors, displays and energy devices, they are still an important challenge in integrating graphene films with inorganic materials.
본 발명자들은, 우수한 전기적, 광학적, 기계적 성질을 지닌 그래핀 필름을 대면적으로 용이하게 제조하여 이러한 그래핀 필름의 전사, 패터닝, 에칭 등의 공정을 이용하여 대면적 그래핀 투명 전극을 용이하게 제조하고, 이러한 그래핀을 이용하여, 플렉시블(flexible)하고 스트레처블(stretchable)한 기판, 상기 기판에 형성된 반도체층, 및 상기 반도체층에 형성된 스트레처블 그래핀 전극을 포함하는, 플렉시블/스트레처블 반도체 소자 및 상기 소자에 있어서, 상기 그래핀 전극과 상기 반도체층 사이의 접촉저항을 감소시키는 방법을 제공하고자 한다. 또한, 그래핀 인터커넥터 및 이를 이용한 신축성, 유연성 및 투명도를 가지는 전자 디바이스를 제공하고자 한다. The present inventors easily manufacture a graphene film having excellent electrical, optical, and mechanical properties to a large area, thereby easily manufacturing a large area graphene transparent electrode using a process such as transfer, patterning, and etching of the graphene film. And using such graphene, a flexible / stretchable substrate comprising a flexible and stretchable substrate, a semiconductor layer formed on the substrate, and a stretchable graphene electrode formed on the semiconductor layer. In the chuble semiconductor device and the device, a method of reducing contact resistance between the graphene electrode and the semiconductor layer is provided. In addition, an object of the present invention is to provide a graphene interconnector and an electronic device having flexibility, flexibility, and transparency using the same.
그러나, 본원이 해결하고자 하는 과제는 이상에서 언급한 과제로 제한되지 않으며, 언급되지 않은 또 다른 과제들은 아래의 기재로부터 당업자에게 명확하게 이해될 수 있을 것이다.However, the problem to be solved by the present application is not limited to the above-mentioned problem, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.
상기와 같은 목적을 달성하기 위하여, 본원의 제 1 측면은, 플렉시블(flexible)하고 스트레처블(stretchable)한 기판, 상기 기판에 형성된 반도체층, 및 상기 반도체층에 형성된 스트레처블 그래핀 전극을 포함하는, 플렉시블/스트레처블 반도체 소자를 제공할 수 있다.In order to achieve the above object, the first aspect of the present invention, a flexible (flexible) stretchable (stretchable) substrate, a semiconductor layer formed on the substrate, and a stretchable graphene electrode formed on the semiconductor layer A flexible / stretchable semiconductor device can be provided.
본원의 제 2 측면은, 반도체층과 그에 형성된 그래핀 전극 사이의 접촉저항을 감소시키는 방법으로서, (1) 상기 그래핀 전극 형성 전에 상기 반도체층 사이의 자연산화막을 제거하는 것, (2) 상기 그래핀 전극과 상기 반도체층과의 접촉 면적이 가능한 넓게 되도록 형성하는 것, (3) 상기 그래핀 전극과 상기 반도체층 사이에 버퍼층을 형성하는 것, 및 (4) 상기 그래핀 전극 상에 접촉저항 감소층을 형성하는 것으로 이루어진 군에서 선택되는 하나 이상을 포함하는, 반도체층과 그래핀 전극 사이의 접촉저항을 감소시키는 방법을 제공할 수 있다. According to a second aspect of the present invention, there is provided a method of reducing contact resistance between a semiconductor layer and a graphene electrode formed thereon, (1) removing a native oxide film between the semiconductor layers before forming the graphene electrode, (2) the Forming a contact area between the graphene electrode and the semiconductor layer as wide as possible, (3) forming a buffer layer between the graphene electrode and the semiconductor layer, and (4) contact resistance on the graphene electrode It is possible to provide a method for reducing contact resistance between a semiconductor layer and a graphene electrode, including one or more selected from the group consisting of forming a reduction layer.
본원의 제 3 측면은, 탄성체 기판; 상기 탄성체 기판 상에 형성되는 복수개의 소자; 및 상기 복수개의 소자를 상호 연결하는 그래핀 인터커넥터를 포함하는, 전자 디바이스를 제공할 수 있다.A third aspect of the present application, the elastic substrate; A plurality of elements formed on the elastic substrate; And a graphene interconnector interconnecting the plurality of devices.
본원에 의하면, 플렉시블하고 스트레처블한 기판 및 스트레처블 그래핀 전극을 이용하여 플렉시블/스트레처블 반도체 소자를 제공할 수 있으며, 또한, 상기와 같은 소자에 있어서, 반도체층과 그에 형성된 그래핀 전극 사이의 접촉저항을 감소시킴으로써, 스트레처블 그래핀 전극을 이용하여 플렉시블/스트레처블 반도체 소자의 전기적 특성을 더욱 향샹시킬 수 있다. 특히, 그래핀 전극과 반도체의 접촉시 접촉저항 증가로 인한 신호전달 지연 등의 문제점을 해결하여 반도체 소자의 제조 공정 수율 및 신뢰성을 향상시킬 수 있다. 또한, 본원에 의하여 그래핀 인터커넥터 및 이를 이용한 신축성, 유연성 및 투명도를 가지는 전자 디바이스를 제공할 수 있다.According to the present application, it is possible to provide a flexible / stretchable semiconductor device using a flexible and stretchable substrate and a stretchable graphene electrode, and in the above device, the semiconductor layer and the graphene formed thereon By reducing the contact resistance between the electrodes, the stretchable graphene electrode can be used to further improve the electrical characteristics of the flexible / stretchable semiconductor device. In particular, it is possible to improve the manufacturing process yield and reliability of a semiconductor device by solving problems such as signal transmission delay due to an increase in contact resistance when the graphene electrode is in contact with the semiconductor. In addition, the present invention can provide an electronic device having a graphene interconnect and stretch, flexibility and transparency using the same.
아울러, 우수한 전기적 특성을 갖는 그래핀 전극을 이용하여 게이트 전극 및/또는 투명 소스/드레인 전극으로 제조함으로써 전기적 광학적 및 기계적 특성이 우수한 유연성을 갖는 플렉시블/스트레처블 반도체 소자를 제조할 수 있다. 본원에 의하여, 대면적의 플렉시블 실리콘 박막 반도체 소자를 용이하게 제조할 수 있으며, 특히 상기 소자를 플렉시블 반투명하게 대면적으로 용이하게 제조할 수 있어, 다양한 전기, 전자 디바이스에 응용할 수 있다. 상기 플렉시블 실리콘 박막 반도체 소자는 박막 트랜지스터로서 사용될 수 있어, 액정디스플레이(LCD), 광전변환 소자(Photovoltaic Device), 유기발광소자(OLED), 센서, 메모리, 또는 집적회로에 응용될 수 있다.In addition, by manufacturing the gate electrode and / or the transparent source / drain electrode using the graphene electrode having excellent electrical properties, a flexible / stretchable semiconductor device having excellent flexibility in electrical and optical properties may be manufactured. According to the present application, a large-area flexible silicon thin film semiconductor device can be easily manufactured, and in particular, the device can be easily manufactured in a flexible semi-transparent large area, and can be applied to various electric and electronic devices. The flexible silicon thin film semiconductor device may be used as a thin film transistor, and thus may be applied to a liquid crystal display (LCD), a photovoltaic device, an organic light emitting device (OLED), a sensor, a memory, or an integrated circuit.
도 1은 본원의 일 구현예에 따라 제조된 플렉시블/스트레처블 반도체 소자의 제조과정을 나타낸 개략도이다.1 is a schematic diagram illustrating a manufacturing process of a flexible / stretchable semiconductor device manufactured according to an exemplary embodiment of the present disclosure.
도 2는 본원의 일 구현예에 따라 제조된 플렉시블/스트레처블 반도체 소자의 제조과정을 나타낸 개략도이다.2 is a schematic diagram illustrating a manufacturing process of a flexible / stretchable semiconductor device manufactured according to an exemplary embodiment of the present disclosure.
도 3은 본원의 일 구현예에 따른 플렉시블/스트레처블 반도체 소자의 단면도이다.3 is a cross-sectional view of a flexible / stretchable semiconductor device according to an embodiment of the present disclosure.
도 4는 본원의 일 구현예에 따른 플렉시블/스트레처블 반도체 소자의 단면도이다.4 is a cross-sectional view of a flexible / stretchable semiconductor device according to an embodiment of the present disclosure.
도 5a 및 도 5b는 본원의 일 구현예에 따른 플렉시블/스트레처블 반도체 소자의 단면도이다.5A and 5B are cross-sectional views of a flexible / stretchable semiconductor device according to one embodiment of the present disclosure.
도 6은 본원의 일 실시예에 따른 Si FET 에 있어서 그래핀 전극의 제조과정을 나타내는 개략도이다.6 is a schematic diagram illustrating a manufacturing process of a graphene electrode in a Si FET according to an embodiment of the present application.
도 7a는 본원의 일 실시예에 따라 제조된 하이브리드 TFT 의 어레이의 광학적 이미지이다. 7A is an optical image of an array of hybrid TFTs manufactured according to one embodiment of the present application.
도 7b는 본원의 일 실시예에 따라 제조된 디바이스의 각 부분의 광학적 광투광성을 나타내는 그래프이다.7B is a graph showing optical light transmissivity of each portion of a device made according to one embodiment of the present disclosure.
도 8a는 본원의 일 실시예에 따른 플렉시블/스트레처블 반도체 소자에 있어서 0.1 V 드레인 전압 하에서 BOE 처리 전후의 디바이스의 성능을 나타내는 그래프이다. 8A is a graph illustrating the performance of a device before and after BOE treatment under a 0.1 V drain voltage in a flexible / stretchable semiconductor device according to an embodiment of the present disclosure.
도 8b는 본원의 일 실시예에 따른 플렉시블/스트레처블 반도체 소자에 있어서 상이한 게이트 전압에서 채널 길이의 함수로서 On-상태(Ron)에서 저항을 나타내는 그래프이다.FIG. 8B is a graph showing resistance in the on- state (R on ) as a function of channel length at different gate voltages for a flexible / stretchable semiconductor device according to one embodiment of the present disclosure.
도 9a는 본원의 일 실시예에 따른 Cr/Au, 그래핀 및 ITO를 포함하는 다양한 전극을 이용한 단결정 Si TFT의 전달 특성을 나타낸 그래프이다.9A is a graph illustrating transfer characteristics of a single crystal Si TFT using various electrodes including Cr / Au, graphene, and ITO according to an embodiment of the present disclosure.
도 9b는 본원의 일 실시예에 따른 오믹 접촉, 저항 독립적인 전류-전압 특성을 나타내는 그래핀 전극을 가진 디바이스의 전류-전압 특성을 나타내는 그래프이다.FIG. 9B is a graph showing current-voltage characteristics of a device having a graphene electrode showing ohmic contact and resistance-independent current-voltage characteristics according to an embodiment of the present disclosure.
도 10a는 본원의 일 실시예에 따른 플렉시블/스트레처블 반도체 소자에 있어서 ITO 어닐링 전 후의 면저항을 나타내는 도면이다.FIG. 10A illustrates sheet resistance before and after ITO annealing in a flexible / stretchable semiconductor device according to an exemplary embodiment of the present disclosure.
도 10b는 본원의 일 실시예에 따른 SiO2 웨이퍼 상에 전사한 후에 그래핀전극의 프로브 측정 그래프이다. 10B is a graph of a probe measurement of a graphene electrode after transferring onto a SiO 2 wafer according to an embodiment of the present disclosure.
도 11은 본원의 일 실시예에 따라 제조된 플렉시블/스트레처블 반도체 소자에 있어서 각각 104, 105 및 102 의 온/오프(on/off) 비율을 나타내는 그래프이다.FIG. 11 is a graph showing on / off ratios of 10 4 , 10 5, and 10 2 in the flexible / stretchable semiconductor device manufactured in accordance with the example embodiment. FIG.
도 12a는 본원의 일 실시예에 따른 플렉시블/스트레처블 반도체 소자에 있어서 굽힘 시험 전 및 시험 중 디바이스를 나타낸다. 12A illustrates a device before and during a bending test in a flexible / stretchable semiconductor device in accordance with one embodiment of the present application.
도 12b는 본원의 일 실시예에 따른 플렉시블/스트레처블 반도체 소자에 있어서 0.4 %의 인장 및 압축 변형에 해당되는 20 mm 반경으로 구부리기 전, 구부리는 동안 및 구부린 후에 트랜지스터의 성능의 변화를 나타낸다.FIG. 12B illustrates a change in the performance of a transistor before bending, during bending, and after bending in a 20 mm radius corresponding to 0.4% tensile and compressive strain in a flexible / stretchable semiconductor device according to one embodiment of the present disclosure.
도 13은 본원의 일 실시예에 따라 제조된 넓은 접촉면적을 가진 FET의 전자 전달 특성을 나타낸 그래프이다.FIG. 13 is a graph showing electron transfer characteristics of a FET having a large contact area manufactured according to an embodiment of the present disclosure.
도 14는 본원의 일 실시예에 따라 제조된 Au 나노 파티클 형성 전후에 그래핀 전극을 가진 FET의 전달 특성을 나타낸 그래프이다.14 is a graph showing the transfer characteristics of the FET having a graphene electrode before and after the formation of Au nanoparticles prepared according to an embodiment of the present application.
도 15는 본원의 일 실시예에 따라 제조된 그래핀 박막 상에 Au 컨택층 형성 전후에 그래핀 전극을 가진 FET의 전달 특성을 나타낸 그래프이다.FIG. 15 is a graph illustrating a transfer characteristic of a FET having graphene electrodes before and after forming an Au contact layer on a graphene thin film manufactured according to an embodiment of the present disclosure.
도 16은 본원의 일 구현예에 따른 그래핀 인터커넥터를 포함하는 전자 디바이스의 단면도이다.16 is a cross-sectional view of an electronic device including a graphene interconnect in accordance with an embodiment of the present disclosure.
도 17는 본원의 일 구현예에 따른 그래핀 인터커넥터를 포함하는 전자 디바이스의 단면도이다.17 is a cross-sectional view of an electronic device including a graphene interconnect in accordance with an embodiment of the present disclosure.
도 18은 본원의 일 구현예에 따른 그래핀 인터커넥터를 포함하는 전자 디바이스의 단면도이다.18 is a cross-sectional view of an electronic device including a graphene interconnect in accordance with an embodiment of the present disclosure.
도 19는 본원의 일 구현예에 따른 그래핀 인터커넥터를 포함하는 전자 디바이스의 단면도이다.19 is a cross-sectional view of an electronic device including a graphene interconnect in accordance with an embodiment of the present disclosure.
도 20는 본원의 일 구현예에 따른 그래핀 인터커넥터를 포함하는 전자 디바이스 패턴을 나타내는 도면이다.20 is a diagram illustrating an electronic device pattern including a graphene interconnector according to an embodiment of the present disclosure.
도 21은 본원의 일 실시예에 따른 그래핀 인터커넥터를 포함하는 전자 디바이스의 제조방법을 나타내는 개략도이다. 21 is a schematic diagram illustrating a method of manufacturing an electronic device including a graphene interconnector according to an embodiment of the present disclosure.
도 22는 본원의 일 실시예에 따른 그래핀 인터커넥터를 포함하는 전자 디바이스의 이미지이다.22 is an image of an electronic device including a graphene interconnect according to one embodiment of the present disclosure.
도 23은 본원의 일 실시예에 따른 그래핀 인터커넥터를 포함하는 전자 디바이스의 스트레칭 테스트 이미지이다.23 is a stretch test image of an electronic device including a graphene interconnector according to an embodiment of the present disclosure.
도 24는 본원의 일 실시예에 따른 그래핀 인터커넥터를 포함하는 전자 디바이스의 전달 곡선 및 이를 로그 스케일로 나타낸 그래프이다. 24 is a graph showing a transfer curve of an electronic device including a graphene interconnector and a logarithmic scale according to an embodiment of the present disclosure.
도 25은 본원의 일 실시예에 따른 그래핀 인터커넥터를 포함하는 전자 디바이스의 전류-전압 곡선이다.25 is a current-voltage curve of an electronic device including a graphene interconnect according to one embodiment of the present disclosure.
도 26은 본원의 일 실시예에 따른 그래핀 인터커넥터를 포함하는 전자 디바이스의 변형률에 따른 전기적 특성을 나타낸 그래프이다.26 is a graph illustrating electrical characteristics according to strain of an electronic device including a graphene interconnector according to an exemplary embodiment of the present disclosure.
이하, 첨부한 도면을 참조하여 본원이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 본원의 구현예 및 실시예를 상세히 설명한다.Hereinafter, embodiments and examples of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present disclosure.
그러나 본원은 여러 가지 상이한 형태로 구현될 수 있으며 여기에서 설명하는 구현예 및 실시예에 한정되지 않는다. 그리고 도면에서 본원을 명확하게 설명하기 위해서 설명과 관계없는 부분은 생략하였으며, 명세서 전체를 통하여 유사한 부분에 대해서는 유사한 도면 부호를 붙였다.As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted for simplicity of explanation, and like reference numerals designate like parts throughout the specification.
본원 명세서 전체에서, 어떤 부분이 어떤 구성요소를 "포함" 한다고 할 때, 이는 특별히 반대되는 기재가 없는 한 다른 구성요소를 제외하는 것이 아니라 다른 구성 요소를 더 포함할 수 있는 것을 의미한다. 본원 명세서 전체에서 사용되는 정도의 용어 "약", "실질적으로" 등은 언급된 의미에 고유한 제조 및 물질 허용오차가 제시될 때 그 수치에서 또는 그 수치에 근접한 의미로 사용되고, 본원의 이해를 돕기 위해 정확하거나 절대적인 수치가 언급된 개시 내용을 비양심적인 침해자가 부당하게 이용하는 것을 방지하기 위해 사용된다. 본원 명세서 전체에서 사용되는 정도의 용어 "~(하는) 단계" 또는 "~의 단계"는 "~ 를 위한 단계"를 의미하지 않는다.Throughout this specification, when a part is said to "include" a certain component, it means that it can further include other components, without excluding the other components unless specifically stated otherwise. As used throughout this specification, the terms "about", "substantially" and the like are used at, or in the sense of, numerical values when a manufacturing and material tolerance inherent in the stated meanings is indicated, Accurate or absolute figures are used to assist in the prevention of unfair use by unscrupulous infringers. As used throughout this specification, the term "step to" or "step of" does not mean "step for."
본원의 제 1 측면은, 플렉시블(flexible)하고 스트레처블(stretchable)한 기판, 상기 기판에 형성된 반도체층, 및 상기 반도체층에 형성된 스트레처블 그래핀 전극을 포함하는, 플렉시블/스트레처블 반도체 소자를 제공할 수 있다.A first aspect of the present application is a flexible / stretchable semiconductor, comprising a flexible and stretchable substrate, a semiconductor layer formed on the substrate, and a stretchable graphene electrode formed on the semiconductor layer. An element can be provided.
예시적 구현예에 있어서, 상기 플렉시블하고 스트레처블한 기판은 폴리디메틸실록산(polydimethylsiloxane; PDMS), 폴리메틸메타아크릴레이트(polymethylmethacrylate; PMMA), 폴리카보네이트(polycarbonate), 폴리에틸렌(polyethylene), 폴리프로필렌(polyprolylene), 폴리스티렌(polystyrene), 폴리이미드(polyimide), 시클로 올레핀 공중합체(cyclo olefin copolymer; COC), 파릴린(parylene) 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the flexible and stretchable substrate may be polydimethylsiloxane (PDMS), polymethylmethacrylate (PMMA), polycarbonate, polyethylene, polypropylene (polypropylene) It may be selected from the group consisting of polyprolylene, polystyrene, polyimide, cyclo olefin copolymer (COC), parylene and combinations thereof, but is not limited thereto. no.
예시적 구현예에 있어서, 상기 반도체층은 유기물 반도체 또는 무기물 반도체일 수 있으나, 이에 제한되는 것은 아니다. 상기 무기물 반도체는, 예를 들어, Si, 탄소나노튜브, 그래핀, 화합물 반도체, 산화물 반도체 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있으나, 이에 제한되는 것은 아니다. 상기 산화물 반도체는, 예를 들어, InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO4, ZnInO, ZnSnO, In2O3, Ga2O3, HfInZnO, GaInZnO, HfO2, SnO2, WO3, TiO2, Ta2O5, In2O3SnO2, MgZnO, ZnSnO3, ZnSnO4, CdZnO, CuAlO2, CuGaO2, Nb2O5, TiSrO3 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있으나, 이에 제한되는 것은 아니다. 또한, 상기 유기물 반도체는, 예를 들어, 펜타센(pentacene), 알파-6T(alpha-sexithiophene), F-CuPc(hexadecafluorcopper phthalocyanine), P3HT[poly(3-hexylthiophene)], 및 이들의 조합들로 이루어진 군에서 선택되는 것을 포함할 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the semiconductor layer may be an organic semiconductor or an inorganic semiconductor, but is not limited thereto. The inorganic semiconductor may be selected from, for example, Si, carbon nanotubes, graphene, compound semiconductors, oxide semiconductors, and combinations thereof, but is not limited thereto. The oxide semiconductor is, for example, InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 , TiO 2 , Ta 2 O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5 , TiSrO 3 and combinations thereof However, it is not limited thereto. In addition, the organic semiconductor may be, for example, pentacene, alpha-6T (alpha-sexithiophene), F-CuPc (hexadecafluorcopper phthalocyanine), P3HT [poly (3-hexylthiophene)], and combinations thereof. It may include one selected from the group consisting of, but is not limited thereto.
일 구현예에 있어서, 상기 자연산화막은 HF, NH4F, SC1(standard chemical 1), PAN 및 이들의 조합들로 이루어진 군에서 선택되는 것을 포함하는 용액을 이용하여 제거된 것일 수 있으나, 이에 제한되는 것은 아니다.In one embodiment, the natural oxide film may be removed using a solution including one selected from the group consisting of HF, NH 4 F, standard chemical 1 (SC1), PAN, and combinations thereof, but is not limited thereto. It doesn't happen.
일 구현예에 있어서, 상기 그래핀 전극은 스트레처블하고 투명한 전극으로서 제공될 수 있으며, 상기 그래핀 전극은, 예를 들어, 화학 기상 증착법에 의하여 제조되는 대면적 그래핀 필름을 이용하여 제조될 수 있으나, 이에 제한되는 것은 아니다. 그래핀은 전기적, 기계적, 화학적인 특성이 매우 안정적이고 뛰어날 뿐 아니라 우수한 전도성 물질로서 실리콘보다 100 배 빠르게 전자를 이동시키며 구리보다도 약 100 배 가량 더 많은 전류를 흐르게 할 수 있다. 또한, 그래핀은 상대적으로 가벼운 원소인 탄소만으로 이루어져 1차원 또는 2차원 나노패턴을 가공하기가 매우 용이하다는 장점이 있으며, 이를 활용하면 그래핀의 반도체-도체 성질을 조절할 수 있을 뿐 아니라 탄소가 가지는 화학결합의 다양성을 이용해 센서, 메모리 등 광범위한 기능성 소자의 제작도 가능하다.In one embodiment, the graphene electrode may be provided as a stretchable and transparent electrode, the graphene electrode, for example, to be prepared using a large area graphene film prepared by chemical vapor deposition method May be, but is not limited thereto. In addition to being very stable and excellent in electrical, mechanical and chemical properties, graphene is an excellent conducting material that can move electrons 100 times faster than silicon and carry about 100 times more current than copper. In addition, graphene has the advantage that it is very easy to process one-dimensional or two-dimensional nanopattern consisting of only a relatively light element of carbon, by using this can not only control the semiconductor-conductor properties of graphene but also has a carbon The variety of chemical bonds allows the manufacture of a wide range of functional devices, including sensors and memories.
일 구현예에 있어서, 상기 그래핀 전극은 화학기상증착법에 의하여 합성된 대면적 그래핀 필름을 전사한 것일 수 있으며, 이러한 대면적 그래핀 필름의 패터닝 및 전사 등의 공정을 이용하여 대면적의 그래핀 투명 전극 또는 대면적의 투명 전극 패턴을 용이하게 제조할 수 있고, 이러한 대면적 그래핀 전극 또는 투명 전극 패턴을 이용하여 대면적의 플렉시블, 스트레처블 반도체 소자를 용이하게 제조할 수 있으며, 특히 상기 소자를 다양한 플렉시블, 스트레처블 투명 전기, 전자 디바이스에 응용할 수 있다 In one embodiment, the graphene electrode may be a transfer of a large-area graphene film synthesized by chemical vapor deposition, a large-area graphene using a process such as patterning and transfer of the large-area graphene film A pin transparent electrode or a large area transparent electrode pattern can be easily manufactured, and a large area flexible, stretchable semiconductor device can be easily manufactured using such a large area graphene electrode or a transparent electrode pattern. The device can be applied to various flexible, stretchable transparent electrical and electronic devices
예를 들어, 상기 그래핀 전극은, 그래핀 성장을 위한 금속 촉매층에 탄소 소스 및 열을 제공하여 화학 기상 증착법에 의하여 성장된 것일 수 있으나, 이에 제한되는 것은 아니다. 상기 금속 촉매층은, Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Rh, Si, Ta, Ti, W, U, V 및 Zr, 및 스테인레스 스틸로 이루어진 군으로부터 선택된 하나 이상을 포함하는 것 일 수 있으나, 이에 제한되는 것은 아니다. 상기 금속 촉매층은 박막 형태일 수 있으며, 예를 들어, 약 1 nm 내지 약 1,000 nm, 약 1 nm 내지 약 500 nm, 약 1 nm 내지 약 400 nm, 또는, 약 100 nm 내지 약 400 nm 두께의 박막일 수 있으나, 이에 제한되는 것은 아니다.For example, the graphene electrode may be grown by chemical vapor deposition by providing a carbon source and heat to the metal catalyst layer for graphene growth, but is not limited thereto. The metal catalyst layer is one selected from the group consisting of Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Rh, Si, Ta, Ti, W, U, V and Zr, and stainless steel It may be to include the above, but is not limited thereto. The metal catalyst layer may be in the form of a thin film, for example, about 1 nm to about 1,000 nm, about 1 nm to about 500 nm, about 1 nm to about 400 nm, or about 100 nm to about 400 nm thick It may be, but is not limited thereto.
상기 예시적 구현예에 있어서, 상기 그래핀 필름이 패터닝된 상기 금속 촉매층을 이용하여 성장된 것 일 수 있으나, 이에 제한되는 것은 아니다.In the exemplary embodiment, the graphene film may be grown using the patterned metal catalyst layer, but is not limited thereto.
예시적 구현예에 있어서, 상기 그래핀 필름을 투명 및/또는 유연성 기판이나 다른 투명 및/또는 유연성 박막 상에 전사함으로써 상기 투명 전극을 플렉시블(flexible)하게 할 수 있다.In an exemplary embodiment, the transparent electrode may be made flexible by transferring the graphene film onto a transparent and / or flexible substrate or another transparent and / or flexible thin film.
예시적 구현예에 있어서, 상기 그래핀 필름의 두께가 약 0.1 nm 내지 약 10 nm인 투명 박막일 수 있으나, 이에 제한되는 것은 아니다. In an exemplary embodiment, the graphene film may be a transparent thin film having a thickness of about 0.1 nm to about 10 nm, but is not limited thereto.
예시적 구현예에 있어서, 상기 투명 전극의 면저항이 약 1 Ω/sq 내지 약 1,000 Ω/sq 일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the sheet resistance of the transparent electrode may be about 1 kW / sq to about 1,000 kW / sq, but is not limited thereto.
예시적 구현예에 있어서, 상기 투명 전극의 투과도가 약 70% 이상, 예를 들어, 약 70% 이상 내지 약 98% 이하일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the transmittance of the transparent electrode may be about 70% or more, for example, about 70% or more to about 98% or less, but is not limited thereto.
예시적 구현예에 있어서, 상기 플렉시블/스트레처블 반도체 소자에 있어서, 상기 반도체층과 그에 형성된 스트레처블 그래핀 전극 사이의 접촉저항을 감소시킬 수 있으며, 이러한 접촉 저항 감소는, (1) 상기 그래핀 전극과 상기 반도체층 사이의 자연산화막을 제거하는 것, (2) 상기 그래핀 전극에 의하여 상기 반도체층과의 접촉 면적이 가능한 넓게 되도록 형성하는 것, (3) 상기 그래핀 전극과 상기 반도체층 사이에 버퍼층을 형성하는 것, 및 (4) 상기 그래핀 전극 상에 접촉저항 감소층을 형성하는 것으로 이루어진 군에서 선택되는 하나 이상을 포함하는 방법에 의하여 수행될 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, in the flexible / stretchable semiconductor device, the contact resistance between the semiconductor layer and the stretchable graphene electrode formed thereon may be reduced, and such contact resistance reduction may include (1) the Removing the native oxide film between the graphene electrode and the semiconductor layer, (2) forming the contact area with the semiconductor layer as wide as possible by the graphene electrode, (3) the graphene electrode and the semiconductor Forming a buffer layer between the layers, and (4) may be performed by a method comprising at least one selected from the group consisting of forming a contact resistance reducing layer on the graphene electrode, but is not limited thereto. .
일 구현예에 있어서, 상기 자연산화막은 HF, NH4F, SC1(standard chemical 1), PAN 및 이들의 조합들로 이루어진 군에서 선택되는 것을 포함하는 용액을 이용하여 제거된 것일 수 있으나, 이에 제한되는 것은 아니다.In one embodiment, the natural oxide film may be removed using a solution including one selected from the group consisting of HF, NH 4 F, standard chemical 1 (SC1), PAN, and combinations thereof, but is not limited thereto. It doesn't happen.
본원의 제 2 측면은, 반도체층과 그에 형성된 그래핀 전극 사이의 접촉저항을 감소시키는 방법으로서, (1) 상기 그래핀 전극과 상기 반도체층 사이의 자연산화막을 제거하는 것, (2) 상기 그래핀 전극과 상기 반도체층과의 접촉 면적을 가능한 넓게 되도록 형성하는 것, (3) 상기 그래핀 전극과 상기 반도체층 사이에 버퍼층을 형성하는 것, 및 (4) 상기 그래핀 전극 상에 접촉저항 감소층을 형성하는 것으로 이루어진 군에서 선택되는 하나 이상을 포함하는, 반도체층과 그래핀 전극 사이의 접촉저항을 감소시키는 방법을 제공할 수 있다.According to a second aspect of the present invention, there is provided a method of reducing contact resistance between a semiconductor layer and a graphene electrode formed thereon, (1) removing a natural oxide film between the graphene electrode and the semiconductor layer, and (2) the graphene. Forming a contact area between the pin electrode and the semiconductor layer as wide as possible, (3) forming a buffer layer between the graphene electrode and the semiconductor layer, and (4) reducing the contact resistance on the graphene electrode. It is possible to provide a method of reducing contact resistance between a semiconductor layer and a graphene electrode, including one or more selected from the group consisting of forming a layer.
예시적 구현예에 있어서, 상기 반도체층은 유기물 반도체 또는 무기물 반도체를 포함하는 것일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the semiconductor layer may include an organic semiconductor or an inorganic semiconductor, but is not limited thereto.
예시적 구현예에 있어서, 상기 (1)에서 상기 자연산화막을 제거하는 것은 HF, NH4F, SC1(standard chemical 1), PAN 및 이들의 조합들로 이루어진 군에서 선택되는 것을 포함하는 용액을 이용하여 수행되는 것일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the removal of the natural oxide film in (1) using a solution comprising a selected from the group consisting of HF, NH 4 F, standard chemical 1 (SC1), PAN and combinations thereof It may be performed by, but is not limited thereto.
예시적 구현예에 있어서, 상기 (3) 및 (4)에서 상기 버퍼층 및 상기 접촉저항 감소층 각각은 도전성 물질을 포함하여 형성되는 것일 수 있으나, 이에 제한되는 것은 아니다. 예를 들어, 상기 도전성 물질은 ITO, IZO, Ti, Cu, Au, Pt, Ir, Cr, Mg, Ag, Ni, Al 및 이들의 조합들로 이루어진 군에서 선택되는 것을 포함하는 것일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, each of the buffer layer and the contact resistance reducing layer in (3) and (4) may be formed including a conductive material, but is not limited thereto. For example, the conductive material may include one selected from the group consisting of ITO, IZO, Ti, Cu, Au, Pt, Ir, Cr, Mg, Ag, Ni, Al, and combinations thereof, but It is not limited.
일 구현예에 있어서, 상기 제조된 플렉시블/스트레처블 반도체 소자의 상기 반도체층 및 상기 그래핀 전극 사이에 자연적으로 생성되는 산화막은 화학용액을 이용한 처리에 의해 제거될 수 있다. 상기 화학용액은 예를 들어, HF, NH4F, SC1(standard chemical 1), PAN 및 이들의 조합들로 이루어진 군에서 선택되는 것을 포함하는 것일 수 있으나, 이에 제한되는 것은 아니다. 일 구현예에 있어서, HF를 버퍼 산화 식각 용액(Buffered Oxide Echant; BOE)으로 사용하는 경우에는 HF와 물의 비율을 약 1 : 약 200으로 혼합하여 사용할 수 있다. 다른 구현예에 있어서, NH4OH, H2O2, H2O의 혼합물인 SC1 용액을 사용하는 경우, 약 1 : 약 4 : 약 20 의 비율로 혼합하여 약 40℃ 내지 약 80℃에서 약 10분 동안 식각하여 사용할 수 있다. 또 다른 구현예에 있어서, H3PO4, HNO3, CH3COOH, 및 H2O의 혼합물인 PAN을 사용하는 경우에는, H2O2와 약 19 : 약 1의 비율로 혼합하여 65℃에서 30분 동안 식각하여 사용할 수 있다. 또 다른 실시예에 있어서, NH4F 및 HF의 비율을 약 7 : 약 1로 하는 버퍼 산화 식각용액(BOE)을 H2O와 약 1 : 약 5 내지 약 1 : 약 30의 비율로 혼합하여 사용할 수도 있다.In some embodiments, an oxide film naturally generated between the semiconductor layer and the graphene electrode of the manufactured flexible / stretchable semiconductor device may be removed by treatment with a chemical solution. The chemical solution, for example, HF, NH 4 F, SC1 (standard chemical 1), but may be to include those selected from the group consisting of the PAN and combinations thereof, but is not limited thereto. In one embodiment, when HF is used as a buffered oxide etch solution (BOE), the ratio of HF and water may be used in a mixture of about 1: 200. In another embodiment, when using a SC1 solution which is a mixture of NH 4 OH, H 2 O 2 , H 2 O, the mixture is mixed at a ratio of about 1: about 4: about 20 to about 40 ° C. to about 80 ° C. It can be used by etching for 10 minutes. In another embodiment, when using PAN which is a mixture of H 3 PO 4 , HNO 3 , CH 3 COOH, and H 2 O, the mixture is mixed with H 2 O 2 at a ratio of about 19: 1 to 65 ° C. It can be used by etching for 30 minutes. In another embodiment, a buffered oxidizing solution (BOE) having a ratio of NH 4 F and HF of about 7: about 1 is mixed with H 2 O at a ratio of about 1: about 5 to about 1: about 30: Can also be used.
상기 플렉시블/스트레처블 반도체 소자의 상기 반도체층 및 상기 그래핀 전극 사이에 자연적으로 생성되는 산화막은 화학용액을 이용한 처리에 의해 제거하는 공정은 상기에 서술한 바와 같이, 그래핀 전극을 형성한 후에 산화막 제거 공정을 수행할 수도 있지만, 상기 반도체층을 형성한 후에 형성된 산화막을 산화막 제거 공정을 수행하여 제거할 수도 있다.The step of removing the oxide film naturally generated between the semiconductor layer and the graphene electrode of the flexible / stretchable semiconductor element by treatment with a chemical solution is as described above, after forming the graphene electrode. Although the oxide film removing process may be performed, the oxide film formed after the semiconductor layer is formed may be removed by performing the oxide film removing process.
종래의 공정에서 그래핀 전극 및 반도체층 사이에 형성된 반도체 산화막이 제거되지 않고 남아서 컨택 저항의 증가 요인이 되었지만, 본원에 따른 화학 용액을 이용한 처리에 의해 절연막질인 자연산화막이 제거되기 때문에 저항증가 요인이 제거될 수 있다. 따라서, 그래핀 전극 및 반도체층 사이의 접촉 저항이 감소되어 소자의 신뢰성이 향상될 수 있다. In the conventional process, the semiconductor oxide film formed between the graphene electrode and the semiconductor layer was not removed, thereby increasing the contact resistance. However, the resistance increase factor is caused by the removal of the natural oxide film, which is an insulating material, by the treatment with the chemical solution according to the present application. This can be removed. Therefore, the contact resistance between the graphene electrode and the semiconductor layer is reduced to improve the reliability of the device.
다른 구현예에 있어서, 상기 플렉시블/스트레처블 반도체 소자에 있어서, 상기 반도체층 및 상기 그래핀 전극 사이에 접촉면적을 증가시킴으로써, 상기 반도체층 및 상기 그래핀 전극의 접촉저항을 감소시킬 수 있다. 예시적 구현예에 있어서, 상기 반도체층 및 상기 그래핀 전극 사이에 상기 접촉면적 증가는 상기 그래핀 전극 형성 시 상기 반도체층과 가능한 넓은 면적으로 접촉할 수 있도록 형성시키는 것일 수 있으나, 이에 제한되는 것은 아니다. 일 구현예에 있어서, 상기 플렉시블/스트레처블 반도체 소자에 있어서 상기 그래핀을 이용하여 소스 전극 및 드레인 전극을 형성하는 경우, 상기 소스 전극 및 드레인 전극이 상기 반도체층을 최대한 넓게 커버할 수 있도록 형성할 수 있다.In another embodiment, in the flexible / stretchable semiconductor device, the contact resistance between the semiconductor layer and the graphene electrode may be reduced by increasing the contact area between the semiconductor layer and the graphene electrode. In an exemplary embodiment, the increase in the contact area between the semiconductor layer and the graphene electrode may be to form contact with the semiconductor layer in the widest possible area when the graphene electrode is formed, but is not limited thereto. no. In example embodiments, when the source electrode and the drain electrode are formed using the graphene in the flexible / stretchable semiconductor device, the source electrode and the drain electrode are formed to cover the semiconductor layer as wide as possible. can do.
또 다른 구현예에 있어서, 상기 플렉시블/스트레처블 반도체 소자에 있어서, 상기 그래핀 전극과 상기 반도체층 사이에 버퍼층을 형성하여 상기 반도체층 및 상기 그래핀 전극의 접촉저항을 감소시킬 수 있다. 예시적 구현예에 있어서, 상기 버퍼층은 전도성 물질을 포함하여 형성될 수 있으며, 특히 상기 전도성 물질은 상기 소자 제조 과정에서 사용되는 다양한 식각액에 저항성이 있는 도전성 물질을 사용하는 것이 바람직하다. 예시적 구현예에 있어서, 상기 전도성 물질 ITO, IZO, Ti, Cu, Au, Pt, Ir, Cr, Mg, Ag, Ni, Al 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있으나, 이에 제한되는 것은 아니다. 상기 바퍼층의 두께는 ~수십 nm일 수 있다. 상기 전도성 물질을 포함하는 버퍼층이 형성되는 경우, 상기 반도체층 및 상기 그래핀 전극 사이의 자연사화막의 결함(defect) 등으로 상기 전도성 물질이 확산되어 침투함으로써 접촉 저항을 감소시키게 된다.In another embodiment, in the flexible / stretchable semiconductor device, a buffer layer may be formed between the graphene electrode and the semiconductor layer to reduce contact resistance between the semiconductor layer and the graphene electrode. In an exemplary embodiment, the buffer layer may include a conductive material, and in particular, the conductive material may be a conductive material that is resistant to various etchant used during the device manufacturing process. In an exemplary embodiment, the conductive material may be selected from the group consisting of ITO, IZO, Ti, Cu, Au, Pt, Ir, Cr, Mg, Ag, Ni, Al, and combinations thereof, but is not limited thereto. It doesn't happen. The buffer layer may have a thickness of several tens of nm. When the buffer layer including the conductive material is formed, the conductive material diffuses and penetrates into a defect of the natural vapor film between the semiconductor layer and the graphene electrode, thereby reducing contact resistance.
또 다른 구현예에 있어서, 상기 플렉시블/스트레처블 반도체 소자에 있어서, 상기 그래핀 전극 상에 접촉저항 감소층을 형성하여 상기 그래핀 전극의 접촉저항을 감소시킬 수 있다. 예시적 구현예에 있어서, 상기 접촉저항 감소층은 전도성 물질을 포함하여 형성될 수 있으며, 특히 상기 전도성 물질은 상기 소자 제조 과정에서 사용되는 다양한 식각액에 저항성이 있는 도전성 물질을 사용하는 것이 바람직하다. 예시적 구현예에 있어서, 상기 전도성 물질 ITO, IZO, Ti, Cu, Au, Pt, Ir, Cr, Mg, Ag, Ni, Al 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있으나, 이에 제한되는 것은 아니다. 상기 접촉저항 감소층의 두께는 ~수십 nm일 수 있다. 상기 그래핀 전극 상에 전도성 물질 입자를 포함하는 접촉저항 감소층을 증착시킴으로써, 상기 그래핀 전극 상에 전도성 물질 입자가 확산되어 상기 그래핀 전극 상에 전도성 물질 입자가 잔존하게 되어 접촉저항이 감소될 수 있다. 특히, 그래핀 전극 상에 형성되는 접촉저항 감소층은 상기 소자 제조 시 사용될 수 있는 식각액에 대한 저항성이 있는 전도성 물질을 이용하여 형성함으로써, 노출된 그래핀 전극을 습식 식각에 의한 악영향 즉, 그래핀 전극의 손상으로 인한 전극의 단선 발생을 방지하는 역할을 할 수 있다. 따라서, 반도체 소자의 특성이 시간에 따라 감소하는 단점을 보완해 줄 수 있다.In another embodiment, in the flexible / stretchable semiconductor device, a contact resistance reduction layer may be formed on the graphene electrode to reduce the contact resistance of the graphene electrode. In an exemplary embodiment, the contact resistance reducing layer may be formed of a conductive material, and in particular, the conductive material may be a conductive material that is resistant to various etching liquids used in the device manufacturing process. In an exemplary embodiment, the conductive material may be selected from the group consisting of ITO, IZO, Ti, Cu, Au, Pt, Ir, Cr, Mg, Ag, Ni, Al, and combinations thereof, but is not limited thereto. It doesn't happen. The contact resistance reducing layer may have a thickness of several tens of nm. By depositing a contact resistance reduction layer including conductive material particles on the graphene electrode, the conductive material particles are diffused on the graphene electrode so that the conductive material particles remain on the graphene electrode, thereby reducing the contact resistance. Can be. In particular, the contact resistance reduction layer formed on the graphene electrode is formed by using a conductive material resistant to an etchant that can be used in manufacturing the device, thereby adversely affecting the exposed graphene electrode by wet etching, that is, graphene. It may serve to prevent the occurrence of disconnection of the electrode due to damage to the electrode. Therefore, it is possible to compensate for the disadvantage that the characteristics of the semiconductor device decreases with time.
이하, 본원의 그래핀 투명 전극, 이를 포함하는, 플렉시블 실리콘 박막 반도체 소자 및 그의 제조 방법에 대하여 구현예 및 실시예를 도면을 이용하여 자세히 설명한다. 그러나, 본원이 이에 제한되는 것은 아니다.Hereinafter, the graphene transparent electrode of the present application, a flexible silicon thin film semiconductor device including the same, and a manufacturing method thereof will be described in detail with reference to the accompanying drawings. However, the present application is not limited thereto.
도 1 및 도 2는 본원의 일 구현예에 따라 제조된 플렉시블, 신축가능한 반도체 소자의 제조과정을 나타낸 개략도이다. 도 1 및 도 2에 도시된 바와 같이, 상기 플렉시블, 신축가능한 반도체 소자는 플렉시블하고, 스트레처블한 기판(11, 12) 상에 하부 그래핀 전극(21, 22), 절연체층(31, 32), 반도체층(41, 42)을 포함할 수 있고, 반도체층(41) 상에 자연적으로 생성되는 산화막(41', 42')을 포함할 수 있다.1 and 2 are schematic views showing a manufacturing process of a flexible, stretchable semiconductor device manufactured according to an embodiment of the present application. As shown in FIGS. 1 and 2, the flexible, stretchable semiconductor device has a lower graphene electrode 21, 22, an insulator layer 31, 32 on a flexible, stretchable substrate 11, 12. ), And may include semiconductor layers 41 and 42, and may include oxide layers 41 ′ and 42 ′ that are naturally generated on the semiconductor layer 41.
예시적 구현예에 있어서, 상기 플렉시블하고 스트레처블한 기판(11, 12)은 당업계에 알려진 물질을 당업자가 적의 선택하여 사용할 수 있으며, 폴리디메틸실록산(polydimethylsiloxane; PDMS), 폴리메틸메타아크릴레이트(polymethylmethacrylate; PMMA), 폴리카보네이트(polycarbonate), 폴리에틸렌(polyethylene), 폴리프로필렌(polyprolylene), 폴리스티렌(polystyrene), 폴리이미드(polyimide), 시클로 올레핀 공중합체(cyclo olefin copolymer; COC), 파릴린(parylene) 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the flexible and stretchable substrates 11 and 12 may be suitably used by those skilled in the art using materials known in the art, and may include polydimethylsiloxane (PDMS) and polymethylmethacrylate. polymethylmethacrylate (PMMA), polycarbonate, polyethylene, polyprolylene, polystyrene, polyimide, cyclo olefin copolymer (COC), parylene ) And combinations thereof, but is not limited thereto.
예시적 구현예에 있어서, 상기 반도체층(41, 42)은 유기물 반도체 또는 무기물 반도체일 수 있으나, 이에 제한되는 것은 아니다. 상기 무기물 반도체는 예를 들어, Si, 탄소나노튜브, 그래핀, 화합물 반도체, 산화물 반도체 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있고, 여기서, 산화물 반도체는, 예를 들어, InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO4, ZnInO, ZnSnO, In2O3, Ga2O3, HfInZnO, GaInZnO, HfO2, SnO2, WO3, TiO2, Ta2O5, In2O3SnO2, MgZnO, ZnSnO3, ZnSnO4, CdZnO, CuAlO2, CuGaO2, Nb2O5, TiSrO3 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있다. 또한, 상기 유기물 반도체는 예를 들어, 펜타센(pentacene), 알파-6T(alpha-sexithiophene), F-CuPc(hexadecafluorcopper phthalocyanine), P3HT(poly(3-hexylthiophene)), 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있다.In an exemplary embodiment, the semiconductor layers 41 and 42 may be organic semiconductors or inorganic semiconductors, but are not limited thereto. For example, the inorganic semiconductor may be selected from the group consisting of Si, carbon nanotubes, graphene, compound semiconductors, oxide semiconductors, and combinations thereof, wherein the oxide semiconductor is, for example, InGaZnO, ZnO. , ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 , TiO 2 , Ta 2 O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5 , TiSrO 3, and combinations thereof. In addition, the organic semiconductor may be formed of, for example, pentacene, alpha-6T (alpha-sexithiophene), F-CuPc (hexadecafluorcopper phthalocyanine), P3HT (poly (3-hexylthiophene)), and combinations thereof. It may be selected from the group.
예시적 구현예에 있어서, 스트레처블 그래핀 전극(51, 52)은, 그래핀 성장을 위한 금속 촉매층에 탄소 소스 및 열을 제공하여 화학 기상 증착법에 의하여 성장된 것 일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the stretchable graphene electrodes 51 and 52 may be grown by chemical vapor deposition by providing a carbon source and heat to the metal catalyst layer for graphene growth, but are not limited thereto. It is not.
예시적 구현예에 있어서, 상기 금속 촉매층은, Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Rh, Si, Ta, Ti, W, U, V 및 Zr, 및 스테인레스 스틸로 이루어진 군으로부터 선택된 하나 이상을 포함하는 것 일 수 있으나, 이에 제한되는 것은 아니다. 상기 금속 촉매층은 박막 형태일 수 있으며, 예를 들어, 약 1 nm 내지 약 1,000 nm, 약 1 nm 내지 약 500 nm, 약 1 nm 내지 약 400 nm, 또는, 약 100 nm 내지 약 400 nm 두께의 박막일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the metal catalyst layer is Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Rh, Si, Ta, Ti, W, U, V and Zr, and stainless It may include one or more selected from the group consisting of steel, but is not limited thereto. The metal catalyst layer may be in the form of a thin film, for example, about 1 nm to about 1,000 nm, about 1 nm to about 500 nm, about 1 nm to about 400 nm, or about 100 nm to about 400 nm thick It may be, but is not limited thereto.
상기 예시적 구현예에 있어서, 상기 그래핀 필름이 패터닝된 상기 금속 촉매층을 이용하여 성장된 것 일 수 있으나, 이에 제한되는 것은 아니다.In the exemplary embodiment, the graphene film may be grown using the patterned metal catalyst layer, but is not limited thereto.
예시적 구현예에 있어서, 상기 그래핀 필름을 투명 및/또는 유연성 기판이나 다른 투명 및/또는 유연성 박막 상에 전사함으로써 상기 투명 전극을 플렉시블(flexible)하게 할 수 있다.In an exemplary embodiment, the transparent electrode may be made flexible by transferring the graphene film onto a transparent and / or flexible substrate or another transparent and / or flexible thin film.
예시적 구현예에 있어서, 상기 그래핀 필름의 두께가 약 0.1 nm 내지 약 10 nm인 투Ω명 박막일 수 있으나, 이에 제한되는 것은 아니다. In an exemplary embodiment, the graphene film may be a transparent thin film having a thickness of about 0.1 nm to about 10 nm, but is not limited thereto.
예시적 구현예에 있어서, 상기 그래핀 전극의 면저항이 약 1 Ω/sq 내지 약 1,000 Ω/sq 일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the sheet resistance of the graphene electrode may be about 1 kW / sq to about 1,000 kW / sq, but is not limited thereto.
예시적 구현예에 있어서, 상기 그래핀 전극의 투과도가 약 70% 이상, 예를 들어, 약 70% 이상 내지 약 98% 이하일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the permeability of the graphene electrode may be about 70% or more, for example, about 70% or more to about 98% or less, but is not limited thereto.
제조된 플렉시블/스트레처블 반도체 소자의 상기 반도체층(41) 또는 상기 그래핀 전극(52) 상에 자연적으로 생성되는 산화막(41')은 화학용액을 이용한 처리에 의해 제거되며, 이때 사용되는 상기 화학용액은 예를 들어, HF, NH4F, SC1(standard chemical 1), PAN 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있다. 일 구현예에 있어서, HF를 버퍼 산화 식각 용액(Buffered Oxide Echant; BOE)으로 사용하는 경우에는 HF와 물의 비율을 약 1 : 약 200으로 혼합하여 사용할 수 있다. 다른 구현예에 있어서, NH4OH, H2O2, H2O의 혼합물인 SC1 용액을 사용하는 경우, 약 1 : 약 4 : 약 20 의 비율로 혼합하여 약 40℃ 내지 약 80℃에서 약 10분 동안 식각하여 사용할 수 있다. 또 다른 구현예에 있어서, H3PO4, HNO3, CH3COOH, H2O의 혼합물인 PAN을 사용하는 경우에는, H2O2와 약 19 : 약 1의 비율로 혼합하여 약 65℃ 에서 약 30분 동안 식각하여 사용할 수 있다. 또 다른 구현예에 있어서, NH4F 및 HF의 비율을 약 7 : 약 1로 하는 버퍼 산화 식각용액(BOE)을 H2O와 약 1 : 약 5 내지 약 1 : 약 30의 비율로 혼합하여 사용할 수도 있다.The oxide film 41 ′ naturally formed on the semiconductor layer 41 or the graphene electrode 52 of the manufactured flexible / stretchable semiconductor device is removed by a treatment using a chemical solution. For example, the chemical solution may be selected from the group consisting of HF, NH 4 F, standard chemical 1 (SC1), PAN, and combinations thereof. In one embodiment, when HF is used as a buffered oxide etch solution (BOE), the ratio of HF and water may be used in a mixture of about 1: 200. In another embodiment, when using a SC1 solution which is a mixture of NH 4 OH, H 2 O 2 , H 2 O, the mixture is mixed at a ratio of about 1: about 4: about 20 to about 40 ° C. to about 80 ° C. It can be used by etching for 10 minutes. In another embodiment, when using PAN which is a mixture of H 3 PO 4 , HNO 3 , CH 3 COOH, H 2 O, H 2 O 2 is mixed at a ratio of about 19: 1 to about 65 ° C. It can be used by etching for about 30 minutes. In another embodiment, a buffered oxidizing solution (BOE) having a ratio of NH 4 F and HF of about 7: about 1 is mixed with H 2 O at a ratio of about 1: about 5 to about 1: about 30: Can also be used.
또한, 플렉시블/스트레처블 반도체 소자의 상기 반도체층(41) 상에 자연적으로 생성되는 산화막(41')은 화학용액을 이용한 처리에 의해 제거하는 공정은 도 1에 도시된 바와 같이, 상기 반도체층(41)을 형성한 후에 형성된 산화막(41')을 산화막 제거 공정을 수행하고 그래핀 전극(52)을 형성할 수 있지만, 도 2에 도시된 바와 같이, 그래핀 전극(52)을 형성하고 패터닝한 후에 자연적으로 생성되는 산화막(42')을 제거하는 공정을 수행할 수도 있다.In addition, the process of removing the oxide film 41 ′ naturally generated on the semiconductor layer 41 of the flexible / stretchable semiconductor device by treatment with a chemical solution is shown in FIG. 1. Although the oxide film 41 ′ formed after the formation of the 41 may be subjected to the oxide film removing process and the graphene electrode 52 may be formed, as shown in FIG. 2, the graphene electrode 52 is formed and patterned. After that, a process of removing the naturally occurring oxide film 42 'may be performed.
종래의 공정에서 그래핀 전극 및 반도체층 사이에 형성된 반도체 산화막이 제거되지 않고 남아서 접촉 저항의 증가 요인이 되었지만, 본원에 따른 화학 용액을 이용한 처리에 의해 절연막질인 자연 산화막(41', 42')이 제거되기 때문에 저항증가 요인이 제거될 수 있다. 따라서, 그래핀 전극(51, 52) 및 반도체층(41, 42) 사이의 접촉 저항이 감소되어 소자의 신뢰성이 향상될 수 있다. In the conventional process, although the semiconductor oxide film formed between the graphene electrode and the semiconductor layer was not removed and became a factor of increasing the contact resistance, the natural oxide films 41 'and 42', which are insulating films, were treated by the chemical solution according to the present application. As this is eliminated, the resistance increasing factor can be eliminated. Therefore, the contact resistance between the graphene electrodes 51 and 52 and the semiconductor layers 41 and 42 may be reduced, thereby improving reliability of the device.
도 3은 본원의 일 구현예에 따른 플렉시블/스트레처블 반도체 소자의 단면도이다. 도 3에 도시된 바와 같이, 플렉시블/스트레처블 반도체 소자는 플렉시블/스트레처블 기판(13) 상에 하부 그래핀 전극(23), 절연체층(33), 반도체층(43) 및 상부 그래핀 전극(53)을 포함할 수 있으며, 상기 반도체층(43) 및 상기 상부 그래핀 전극(53) 사이에 접촉면적을 증가시킬 수 있다.3 is a cross-sectional view of a flexible / stretchable semiconductor device according to an embodiment of the present disclosure. As shown in FIG. 3, the flexible / stretchable semiconductor device includes a lower graphene electrode 23, an insulator layer 33, a semiconductor layer 43, and an upper graphene on the flexible / stretchable substrate 13. An electrode 53 may be included, and a contact area between the semiconductor layer 43 and the upper graphene electrode 53 may be increased.
예시적 구현예에 있어서, 상기 플렉시블하고, 신축가능한 기판(13)은 폴리디메틸실록산(polydimethylsiloxane; PDMS), 폴리메틸메타아크릴레이트(polymethylmethacrylate; PMMA), 폴리카보네이트(polycarbonate), 폴리에틸렌(polyethylene), 폴리프로필렌(polyprolylene), 폴리스티렌(polystyrene), 폴리이미드(polyimide), 시클로 올레핀 공중합체(cyclo olefin copolymer; COC), 파릴린(parylene) 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the flexible, stretchable substrate 13 may comprise polydimethylsiloxane (PDMS), polymethylmethacrylate (PMMA), polycarbonate, polyethylene, poly It may be selected from the group consisting of propylene (polyprolylene), polystyrene, polyimide, cyclo olefin copolymer (COC), parylene and combinations thereof, but is not limited thereto. It doesn't happen.
예시적 구현예에 있어서, 상기 반도체층(43)은 유기물 반도체 또는 무기물 반도체인 것일 수 있으나, 이에 제한되는 것은 아니다. In an exemplary embodiment, the semiconductor layer 43 may be an organic semiconductor or an inorganic semiconductor, but is not limited thereto.
예시적 구현예에 있어서, 상기 접촉면적 증가는 상기 그래핀 전극을 상기 반도체층에 넓게 형성시키는 것일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the contact area increase may be to form the graphene electrode in the semiconductor layer, but is not limited thereto.
도 4 는 본원의 일 구현예에 따른 버퍼층이 형성된 플렉시블/스트레처블 반도체 소자의 단면도이다. 도 4에 도시된 바와 같이, 상기 플렉시블/스트레처블 반도체 소자는 플렉시블/스트레처블 기판(14) 상에 하부 그래핀 전극(24), 절연체층(34), 반도체층(44) 및 상부 그래핀 전극(54)을 포함할 수 있으며, 상기 반도체층(44) 및 상기 상부 그래핀 전극(54) 사이에 증착된 버퍼층(44')을 포함할 수 있다.4 is a cross-sectional view of a flexible / stretchable semiconductor device having a buffer layer according to an embodiment of the present disclosure. As shown in FIG. 4, the flexible / stretchable semiconductor device includes a lower graphene electrode 24, an insulator layer 34, a semiconductor layer 44, and an upper graphene on the flexible / stretchable substrate 14. It may include a pin electrode 54, and may include a buffer layer 44 ′ deposited between the semiconductor layer 44 and the upper graphene electrode 54.
도 5는 본원의 일 구현예에 따른 접촉저항 감소층이 형성된 플렉시블/스트레처블 반도체 소자의 단면도이다. 도 5a에 도시된 바와 같이, 상기 플렉시블/스트레처블 반도체 소자는 플렉시블/스트레처블 기판(15) 상에 하부 그래핀 전극(25), 절연체층(35), 반도체층(45) 및 상부 그래핀 전극(55)을 포함할 수 있으며, 상기 그래핀 전극(55) 상에 증착된 접촉저항 감소층(55')을 포함할 수 있다. 도 5b를 참조하면, 일 구현예에 있어서, 플렉시블/스트레처블 기판(16) 상에 하부 그래핀 전극(26), 절연체층(36)을 포함하며, 산화물, 실리콘 등의 반도체층(46) 상에 그래핀 전극(55)을 올린 후, 전도도 향상을 위해 증착된 접촉저항 감소층(56')을 소스-드레인 및 배선 쪽 전체에 올린 구조를 형성할 수 있다. 상기 접촉저항 감소층(56')은 금속을 이용하여 제조될 수 있으며, 이러한 금속을 이용한 접촉저항 감소층(56')은 진공증착 혹은 용액을 이용한 전기도금, 자기조립법 등에 의하여 형성될 수 있다. 이러한 구조의 장점은 반도체층으로의 이온, 기체 침입을 막고 전도도를 향상시킬 수 있다.5 is a cross-sectional view of a flexible / stretchable semiconductor device in which a contact resistance reduction layer is formed according to an embodiment of the present disclosure. As shown in FIG. 5A, the flexible / stretchable semiconductor device includes a lower graphene electrode 25, an insulator layer 35, a semiconductor layer 45, and an upper graphene on the flexible / stretchable substrate 15. It may include a pin electrode 55, it may include a contact resistance reduction layer 55 'deposited on the graphene electrode 55. Referring to FIG. 5B, in an embodiment, the lower graphene electrode 26 and the insulator layer 36 are included on the flexible / stretchable substrate 16, and the semiconductor layer 46, such as an oxide or silicon, is formed. After the graphene electrode 55 is placed on the substrate, a structure in which the contact resistance reduction layer 56 ′ is deposited on the source-drain and the wiring lines may be formed to improve conductivity. The contact resistance reduction layer 56 ′ may be manufactured using a metal, and the contact resistance reduction layer 56 ′ using the metal may be formed by vacuum deposition or electroplating using a solution, or a self-assembly method. The advantage of this structure is that it can prevent the penetration of ions and gases into the semiconductor layer and improve the conductivity.
예시적 구현예에 있어서, 상기 플렉시블/스트레처블 기판(14, 15, 16)은 폴리디메틸실록산(polydimethylsiloxane; PDMS), 폴리메틸메타아크릴레이트(polymethylmethacrylate; PMMA), 폴리카보네이트(polycarbonate), 폴리에틸렌(polyethylene), 폴리프로필렌(polyprolylene), 폴리스티렌(polystyrene), 폴리이미드(polyimide), 시클로 올레핀 공중합체(cyclo olefin copolymer; COC), 파릴린(parylene) 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the flexible / stretchable substrates 14, 15, and 16 may be made of polydimethylsiloxane (PDMS), polymethylmethacrylate (PMMA), polycarbonate, polyethylene ( polyethylene, polyprolylene, polystyrene, polyimide, cyclo olefin copolymer (COC), parylene, and combinations thereof. However, it is not limited thereto.
예시적 구현예에 있어서, 상기 반도체층(44, 45, 46)은 유기물 반도체 또는 무기물 반도체인 것일 수 있으나, 이에 제한되는 것은 아니다 In an exemplary embodiment, the semiconductor layer 44, 45, 46 may be an organic semiconductor or an inorganic semiconductor, but is not limited thereto.
예시적 구현예에 있어서, 상기 버퍼층(44') 및 상기 접촉저항 감소층(55', 56') 각각은 식각액에 저항성이 있는 도전성 물질인 것일 수 있으나, 이에 제한되는 것은 아니다. 상기 도전성 물질은 예를 들어, ITO, IZO, Ti, Cu, Au, Pt, Ir, Cr, Mg, Ag, Ni, Al 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, each of the buffer layer 44 ′ and the contact resistance reducing layer 55 ′ and 56 ′ may be a conductive material resistant to an etchant, but is not limited thereto. The conductive material may be selected from, for example, ITO, IZO, Ti, Cu, Au, Pt, Ir, Cr, Mg, Ag, Ni, Al, and combinations thereof, but is not limited thereto. no.
상기 버퍼층(44') 및 상기 접촉저항 감소층(55', 56') 각각이 금속을 포함하는 전도성 물질을 이용하여 형성되는 경우, 상기 그래핀 전극(54, 55, 56) 사이 또는 그래핀 전극(54, 55, 56) 상에 도전성 물질의 상기 금속 분자 또는 입자가 확산되어 상기 그래핀 전극 사이 또는 그래핀 전극 상에 금속원자가 잔존하게 되어 접촉저항이 감소될 수 있다. 특히, 상기 접촉저항 감소층(55', 56') 각각은 식각액에 대한 저항성이 있는 전도성 물질을 이용하여 형성됨으로써, 노출된 그래핀 전극(55, 56)을 습식 식각에 의한 악영향 즉, 그래핀 전극(55, 56)의 손상으로 인한 전극의 단선 발생을 방지하는 역할을 할 수 있다. 따라서, 반도체 소자의 특성이 시간에 따라 감소하는 단점을 보완해 줄 수 있다.When each of the buffer layer 44 'and the contact resistance reducing layer 55', 56 'is formed using a conductive material including a metal, between the graphene electrodes 54, 55, 56 or graphene electrode The metal molecules or particles of the conductive material may be diffused on (54, 55, 56) so that metal atoms remain between the graphene electrodes or on the graphene electrodes, thereby reducing contact resistance. In particular, each of the contact resistance reducing layers 55 'and 56' is formed using a conductive material resistant to an etchant, thereby adversely affecting the exposed graphene electrodes 55 and 56 by wet etching, that is, graphene. It may serve to prevent the disconnection of the electrode due to the damage of the electrodes (55, 56). Therefore, it is possible to compensate for the disadvantage that the characteristics of the semiconductor device decreases with time.
본원의 제 3 측면은, 탄성체 기판; 상기 탄성체 기판 상에 형성되는 복수개의 소자; 및 상기 복수개의 소자를 상호 연결하는 그래핀 인터커넥터를 포함하는, 전자 디바이스를 제공할 수 있다.A third aspect of the present application, the elastic substrate; A plurality of elements formed on the elastic substrate; And a graphene interconnector interconnecting the plurality of devices.
본원의 제 3 측면에 따른 전자 디바이스의 상기 탄성체 기판 상에 형성되는 상기 복수개의 소자는 본원의 상기 제 1 측면에 따른 플렉시블/스트레처블 반도체 소자를 포함하는 것일 수 있으며, 상기 플렉시블/스트레처블 반도체 소자는 본원의 상기 제 2 측면에 따른 반도체층과 그래핀 전극 사이의 접촉저항을 감소시키는 방법에 의해 형성되는 것을 포함할 수 있으나, 이에 제한되는 것은 아니다.The plurality of elements formed on the elastic substrate of the electronic device according to the third aspect of the present application may include the flexible / stretchable semiconductor element according to the first aspect of the present application, and the flexible / stretchable The semiconductor device may include, but is not limited to being formed by a method of reducing the contact resistance between the semiconductor layer and the graphene electrode according to the second aspect of the present application.
예시적 구현예에 있어서, 상기 그래핀 인터커넥터는 도핑된 그래핀층으로 형성되는 것일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the graphene interconnector may be formed of a doped graphene layer, but is not limited thereto.
예시적 구현예에 있어서, 상기 그래핀 인터커넥터는 복수개의 그래핀층을 적층하여 형성되는 것일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the graphene interconnector may be formed by stacking a plurality of graphene layers, but is not limited thereto.
예시적 구현예에 있어서, 상기 그래핀 인터커넥터는 그래핀층 및 상기 그래핀 층에 증착된 금속 나노입자를 포함하여 형성되는 것일 수 있으나, 이에 제한되는 것은 아니다. 예를 들어, 상기 금속 나노입자는 Ag, Au, Pt, Pd, Fe, Ni, Al, Sb, W, Tb, Dy, Gd, Eu, Nd, Pr, Sr, Mg, Cu, Zn, Co, Mn, Cr, V, Mo, Zr, Ba 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the graphene interconnector may be formed including a graphene layer and metal nanoparticles deposited on the graphene layer, but is not limited thereto. For example, the metal nanoparticles are Ag, Au, Pt, Pd, Fe, Ni, Al, Sb, W, Tb, Dy, Gd, Eu, Nd, Pr, Sr, Mg, Cu, Zn, Co, Mn , Cr, V, Mo, Zr, Ba and combinations thereof may be selected from, but is not limited thereto.
예시적 구현예에 있어서, 상기 그래핀 인터커넥터는 금속 나노입자 및 그래핀층을 교대로 복수회 적층하여 형성되는 것일 수 있으나, 이에 제한되는 것은 아니다. 예를 들어, 상기 금속 나노입자는 Ag, Au, Pt, Pd, Fe, Ni, Al, Sb, W, Tb, Dy, Gd, Eu, Nd, Pr, Sr, Mg, Cu, Zn, Co, Mn, Cr, V, Mo, Zr, Ba 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the graphene interconnector may be formed by alternately stacking a plurality of metal nanoparticles and a graphene layer, but is not limited thereto. For example, the metal nanoparticles are Ag, Au, Pt, Pd, Fe, Ni, Al, Sb, W, Tb, Dy, Gd, Eu, Nd, Pr, Sr, Mg, Cu, Zn, Co, Mn , Cr, V, Mo, Zr, Ba and combinations thereof may be selected from, but is not limited thereto.
예시적 구현예에 있어서, 상기 탄성체 기판은 열가소성 탄성 중합체(thermoplastic elastomer), 스티렌계 물질(styrenic materials), 올레핀계 물질(olefenic materials), 폴리올레핀(polyolefin), 폴리우레탄 열가소성 탄성 중합체(polyurethane thermoplastic elastomers), 폴리아미드(polyamides), 합성고무(synthetic rubbers), 폴리디메틸실록산(polydimethylsiloxane; PDMS), 폴리부타디엔(polybutadiene), 폴리이소부티렌(polyisobutylene), 폴리(스티렌-부타디엔-스티렌)(poly(styrene-butadiene-styrene)), 폴리우레탄(polyurethanes), 폴리클로로프렌(polychloroprene), 실리콘 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있으나, 이에 제한되는 것은 아니다.In an exemplary embodiment, the elastomer substrate is a thermoplastic elastomer, styrenic materials, olefenic materials, polyolefins, polyurethane thermoplastic elastomers , Polyamides, synthetic rubbers, polydimethylsiloxane (PDMS), polybutadiene, polyisobutylene, poly (styrene-butadiene-styrene) (poly (styrene- butadiene-styrene)), polyurethane (polyurethanes), polychloroprene (polychloroprene), silicone and combinations thereof may be selected from the group consisting of, but is not limited thereto.
예시적 구현예에 있어서, 상기 탄성체 기판은 약 1% 내지 약 30%의 변형률로 변형되는 것일 수 있으나, 이에 제한되는 것은 아니다. 상기 탄성체 기판을 변형시키는 것은 외력을 적용할 수 있다. 예를 들어, 상기 탄성체 기판을 굽힘, 롤링, 굴곡 또는 확장시킴으로써 변형시킬 수 있다. 또한, 탄성체 기판의 변형은 열 방법을 통해 상기 탄성체 기판의 온도를 상승시킴으로써 유발되는 열팽창에 의해 성취될 수도 있다.In an exemplary embodiment, the elastic substrate may be deformed at a strain of about 1% to about 30%, but is not limited thereto. Deforming the elastic substrate may apply an external force. For example, the elastic substrate can be deformed by bending, rolling, bending or expanding. Deformation of the elastomer substrate may also be achieved by thermal expansion caused by raising the temperature of the elastomer substrate through a thermal method.
도 16은 본원의 일 구현예에 따른 전자 디바이스의 단면도이다. 도 16을 참조하면, 두 개의 소자 사이를 연결하는 상기 그래핀 인터커넥터는 도핑된 그래핀층으로 형성되는 것일 수 있다. 상기 그래핀층에 추가되는 도펀트로는 예를 들어, P형 도펀트 또는 N형 도펀트일 수 있으나, 이에 제한되는 것은 아니다. 순수한 그래핀은 밴드갭을 가지지 않고 있지만 도펀트가 추가된 그래핀은 밴드갭을 가지고 있어 전자적 구조를 조절하는 것이 가능하다. 따라서, 전계효과 트랜지스터와 같은 소자를 만드는 데에 매우 유용하다. 일부 구현예들에서, 상기 도펀트는 이온성 액체, 이온성 기체, 산류 화합물 및 유기분자계 화합물로 이루어지는 군으로부터 선택된 하나 이상을 사용하는 것일 수 있으며, 상기 도펀트는, 예를 들어, NO2BF4, NOBF4, NO2SbF6, HCl, H2PO4, H3CCOOH, H2SO4, HNO3, AuCl3, 나피온(Nafion), SOCl2, Br2, PVDF (polyvinylidene fluoride), 디클로로디시아노퀴논, 옥손, 디미리스토일포스파티딜이노시톨 및 트리플루오로메탄술폰이미드로 이루어진 군으로부터 선택된 하나 이상을 사용하는 것일 수 있으나, 이에 제한되는 것은 아니다.16 is a cross-sectional view of an electronic device according to an embodiment of the present disclosure. Referring to FIG. 16, the graphene interconnector connecting two devices may be formed of a doped graphene layer. The dopant added to the graphene layer may be, for example, a P-type dopant or an N-type dopant, but is not limited thereto. Pure graphene does not have a bandgap, but dopant-added graphene has a bandgap, which makes it possible to control the electronic structure. Therefore, it is very useful for making devices such as field effect transistors. In some embodiments, the dopant is an ionic liquid, ionic base, and may be used at least one selected from acids compounds and the group consisting of an organic molecular compounds, the dopant may be, for example, NO 2 BF 4 , NOBF 4 , NO 2 SbF 6 , HCl, H 2 PO 4 , H 3 CCOOH, H 2 SO 4 , HNO 3 , AuCl 3, Nafion, SOCl 2 , Br 2 , polyvinylidene fluoride (PVDF), dichloro One or more selected from the group consisting of dicyanoquinone, oxone, dimyristoyl phosphatidylinositol and trifluoromethanesulfonimide may be used, but is not limited thereto.
도 17은 본원의 일 구현예에 따른 전자 디바이스의 단면도이다. 도 17을 참조하면, 두 개의 소자 사이를 연결하는 상기 그래핀 인터커넥터는 그래핀층을 적층하여 형성되는 형성되는 것일 수 있다. 일 구현예에 있어서, 상기 그래핀층은, 그래핀 성장을 위한 전이금속 촉매층에 탄소 소스 및 열을 제공하여 화학기상증착(chemical vapour deposition; CVD) 방법에 의하여 성장될 수 있다. 17 is a cross-sectional view of an electronic device according to an embodiment of the present disclosure. Referring to FIG. 17, the graphene interconnector connecting two devices may be formed by stacking graphene layers. In one embodiment, the graphene layer may be grown by chemical vapor deposition (CVD) by providing a carbon source and heat to the transition metal catalyst layer for graphene growth.
예를 들어, 상기 전이금속 촉매층은, Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Rh, Si, Ta, Ti, W, U, V, Zr, 스테인레스 스틸 및 이들의 조합들로 이루어진 군에서 선택될 수 있다. 이 때 전이금속 촉매층은 단일층 그래핀을 형성하므로, 전사 과정을 반복함에 따라 그래핀의 층수의 제어가 가능할 수 있다. 일 구현예에 있어서, 그래핀의 층수가 한층, 두층, 및 세층으로 증가하여 적층함에 따라, 면저항은 약 500 Ω/sq 내지 약 50 Ω/sq에서 약 300 Ω/sq 내지 약 10 Ω/sq로, 투과도는 약 550 nm 파장의 빛에 대해 약 97.1% 에서 약 91.2% 로 감소할 수 있다. 이러한 결과는 그래핀 한층당 투과도를 약 2.3% 로 감소시킬 수 있으며, 또한 반복적인 전사 과정을 통해 그래핀 겹수를 완벽하게 제어할 수 있다는 것을 알 수 있다.For example, the transition metal catalyst layer is Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Rh, Si, Ta, Ti, W, U, V, Zr, stainless steel and these May be selected from the group consisting of. At this time, since the transition metal catalyst layer forms single layer graphene, the number of layers of graphene may be controlled by repeating the transfer process. In one embodiment, the sheet resistance increases from about 500 mW / sq to about 50 mW / sq to about 300 mW / sq to about 10 mW / sq as the number of layers of graphene increases to one, two, and three layers. The transmittance may decrease from about 97.1% to about 91.2% for light with a wavelength of about 550 nm. These results can reduce the permeability per graphene to about 2.3%, and it can be seen that it is possible to control the graphene layer number through the repeated transfer process.
상기 화학기상증착법은 고온 화학기상증착(Rapid thermal chemical vapour deposition; RTCVD), 유도결합플라즈마 화학기상증착(inductively coupled plasma-chemical vapor deposition; ICP-CVD), 저압 화학기상증착(low pressure chemical vapor deposition; LPCVD), 상압 화학기상증착(atmospheric pressure chemical vapor deposition; APCVD), 금속 유기화학기상증착(metal organic chemical vapor deposition; MOCVD), 및 플라즈마 강화 화학기상증착(plasma-enhanced chemical vapor deposition; PECVD) 방법을 포함할 수 있으나, 이제 제한되는 것은 아니다.The chemical vapor deposition method may include rapid thermal chemical vapor deposition (RTCVD), inductively coupled plasma-chemical vapor deposition (ICP-CVD), low pressure chemical vapor deposition; LPCVD), atmospheric pressure chemical vapor deposition (APCVD), metal organic chemical vapor deposition (MOCVD), and plasma-enhanced chemical vapor deposition (PECVD) methods. It may include, but is not limited to now.
상기 그래핀은 금속 촉매층을 기상 탄소 공급원을 투입하고 열처리함으로써 그래핀을 성장시킬 수 있다. 일 구현예에 있어서, 금속 촉매층을 챔버에 넣고 일산화탄소, 에탄, 에틸렌, 에탄올, 아세틸렌, 프로판, 부탄, 부타디엔, 펜탄, 펜텐, 사이클로펜타디엔, 헥산, 사이클로헥산, 벤젠, 톨루엔 등과 같은 탄소 공급원을 기상으로 투입하면서, 예를 들어, 약 300℃ 내지 약 2000℃의 온도로 열처리하면 상기 탄소 공급원에 존재하는 탄소 성분들이 결합하여 6각형의 판상 구조를 형성하면서 그래핀이 생성된다. 이를 냉각하면 균일한 배열 상태를 가지는 그래핀이 얻어지게 된다. 그러나, 금속 촉매층 상에서 그래핀을 형성시키는 방법이 화학기상증착 방법에 국한되지 않으며, 본원의 예시적인 구현예에 있어서는 금속 촉매층 상에 그래핀을 형성하는 모든 방법을 이용할 수 있으며, 본원이 금속 촉매층 상에 그래핀을 형성하는 특정 방법에 제한되지 않는다는 것이 이해될 것이다.The graphene may grow graphene by adding a gaseous carbon source and heat treating the metal catalyst layer. In one embodiment, a metal catalyst layer is placed in a chamber and a carbon source such as carbon monoxide, ethane, ethylene, ethanol, acetylene, propane, butane, butadiene, pentane, pentene, cyclopentadiene, hexane, cyclohexane, benzene, toluene, etc. For example, when heat treatment is performed at a temperature of about 300 ° C. to about 2000 ° C., graphene is generated while the carbon components present in the carbon source combine to form a hexagonal plate-like structure. Cooling this yields graphene with a uniform arrangement. However, the method of forming the graphene on the metal catalyst layer is not limited to the chemical vapor deposition method, and in the exemplary embodiment of the present application, any method of forming the graphene on the metal catalyst layer may be used, and the present application may be performed on the metal catalyst layer. It will be appreciated that it is not limited to any particular method of forming graphene in.
도 18은 본원의 일 구현예에 따른 전자 디바이스의 단면도이다. 도 18을 참조하면, 두 개의 소자 사이를 연결하는 상기 그래핀 인터커넥터는 금속 나노입자를 증착하여 형성되는 것일 수 있다. 예를 들어, 상기 금속 나노입자는 Ag, Au, Pt, Pd, Fe, Ni, Al, Sb, W, Tb, Dy, Gd, Eu, Nd, Pr, Sr, Mg, Cu, Zn, Co, Mn, Cr, V, Mo, Zr, Ba 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있다.18 is a cross-sectional view of an electronic device according to an embodiment of the present disclosure. Referring to FIG. 18, the graphene interconnector connecting two devices may be formed by depositing metal nanoparticles. For example, the metal nanoparticles are Ag, Au, Pt, Pd, Fe, Ni, Al, Sb, W, Tb, Dy, Gd, Eu, Nd, Pr, Sr, Mg, Cu, Zn, Co, Mn , Cr, V, Mo, Zr, Ba and combinations thereof may be selected.
도 19는 본원의 일 구현예에 따른 전자 디바이스의 단면도이다. 도 19를 참조하면, 두 개의 소자 사이를 연결하는 상기 그래핀 인터커넥터는 금속 나노입자 및 그래핀층을 교대로 복수회 적층하여 형성되는 것일 수 있다. 예를 들어, 상기 금속 나노입자는 Ag, Au, Pt, Pd, Fe, Ni, Al, Sb, W, Tb, Dy, Gd, Eu, Nd, Pr, Sr, Mg, Cu, Zn, Co, Mn, Cr, V, Mo, Zr, Ba 및 이들의 조합들로 이루어진 군에서 선택되는 것일 수 있다.19 is a cross-sectional view of an electronic device according to an embodiment of the present disclosure. Referring to FIG. 19, the graphene interconnector connecting between two devices may be formed by alternately stacking a plurality of metal nanoparticles and a graphene layer. For example, the metal nanoparticles are Ag, Au, Pt, Pd, Fe, Ni, Al, Sb, W, Tb, Dy, Gd, Eu, Nd, Pr, Sr, Mg, Cu, Zn, Co, Mn , Cr, V, Mo, Zr, Ba and combinations thereof may be selected.
상기 그래핀 인터커넥터의 길이가 길어지게 되면 그래핀 인터커넥트에서 발생하는 저항으로 인해 문제가 될 수 잇는데, 상기에 서술된 바와 같이, 그래핀에 도펀트를 추가하고, 그래핀층을 복수층으로 적층하고, 그래핀 층에 금속 나노입자를 증착하고, 금속 나노입자 및 그래핀 층을 복수 회 적층하여 샌드위치 구조로 형성하여 저항을 감소시킬 수 있다. When the length of the graphene interconnector becomes longer, there may be a problem due to the resistance generated in the graphene interconnect. As described above, a dopant is added to the graphene, the graphene layer is laminated in multiple layers, The metal nanoparticles may be deposited on the graphene layer, and the metal nanoparticles and the graphene layer may be stacked a plurality of times to form a sandwich structure to reduce resistance.
도 20은 본원의 일 구현예에 따른 전자 디바이스 패턴을 나타내는 도면이다. 도 20에 도시된 바와 같이, 소자가 복수 개 배열된 패턴에서 4배 확대된 이미지를 보면 흰색의 직사각형 패턴은 하나의 소자가 들어가는 부분이고, 이러한 각 소자 하나 하나는 중간의 인터커넥트에 의해 연결되어 있다. 1.5배 확대된 이미지에서 패드와 인터커넥트가 연결되는 부분에 스트레스를 흡수하여 스트레스가 집중되어 깨지는 것을 막아주도록 원형 모양의 패턴을 형성할 수 있다. 20 is a diagram illustrating an electronic device pattern according to an embodiment of the present disclosure. As shown in FIG. 20, when the image is magnified 4 times in a pattern in which a plurality of elements are arranged, a white rectangular pattern is a portion into which one element enters, and each of these elements is connected by an intermediate interconnect. . In the 1.5 times magnified image, a circular pattern can be formed to absorb stress at the part where the pad and interconnect are connected to prevent the stress from being concentrated and broken.
본원에 따른 전자 디바이스는 트랜지스터, 다이오드, 레이저, MEMS, NEMS, LEDS 및 OELDS와 같은 수많은 기능성 장치 및 장치 부품을 효과적으로 집적시킬 수 있다. 본원에 따른 전자 디바이스는 종래 단단한 무기 반도체에 비해 확실한 기능적 이점을 가진다. 첫째로, 전자 디바이스는 유연할 수 있으므로, 종래 딱딱한 무기 반도체보다 구부림, 굽힘 및/또는 변형에 의해 유발된 구조적 손상이 적게 받아들인다. 둘째로, 구부러진 반도체 소자가 곡면을 이루는 내표면을 제공하기 위해 약간 기계적으로 변형 상태에 있을 수 있을 때, 본원에 따른 잡아 늘이거나 압축가능한 전자 디바이스 종래의 변형되지 않은 무기 반도체보다 더 높은 고유 전계 효과성 이동도를 나타낼 수 있다. 마지막으로, 본원의 전자 디바이스는 장치 온도 사이클링에 대해서 자유롭게 확장 및 접촉할 수 있기 때문에 우수한 열적 성질을 제공할 수 있다.Electronic devices according to the present invention can effectively integrate numerous functional devices and device components such as transistors, diodes, lasers, MEMS, NEMS, LEDS and OELDS. The electronic device according to the invention has certain functional advantages over conventional rigid inorganic semiconductors. First, electronic devices can be flexible, so they accept less structural damage caused by bending, bending and / or deformation than conventional rigid inorganic semiconductors. Second, when the bent semiconductor device can be in a slightly mechanically deformed state to provide a curved inner surface, the stretchable or compressible electronic device according to the present invention a higher intrinsic field effect than conventional unmodified inorganic semiconductors. Sex mobility. Finally, the electronic devices herein can provide excellent thermal properties because they can freely expand and contact with device temperature cycling.
이하, 실시예를 이용하여 본원을 상세히 설명하지만, 본원에 이에 제한되는 것은 아니다. Hereinafter, the present invention will be described in detail with reference to Examples, but the present invention is not limited thereto.
[실시예 1]Example 1
도 6은 Si FET 기반 그래핀의 제조과정을 나타내는 개략도이다. TFT의 제조는 상부에 300 nm 이상의 두께를 가진 SiO2/Si 기판 상에 약 500 nm 두께의 Ni 촉매층을 형성하고, 상기 Ni 촉매층 상에 탄소 소스를 포함하는 가스 혼합물(CH4 : H2 : Ar = 50 : 65 : 200 sccm) 공급 하에서 950℃에서 직경 4 인치의 석영 튜브 내에서 상기 Ni 촉매층 상에 그래핀 필름을 성장시켰다. 성장된 그래핀 필름은 약 6개 층으로, 광학적 투명성에 의해 측정되었다. 상기 그래핀 박막의 면저항은 4-포인트 탐침에 의해 370 ± 10 Ω/sq로 측정되었다. 그리고 나서, Ni/SiO2/Si 웨이퍼 상에 그래핀 박막은 하부 게이트 전극으로서 PET(~ 200 ㎛)로 전사하였다. Si 채널 물질의 준비는 SOI(silicon-on-insulator) 웨이퍼(SOITEC Unibond; 상부 단결정 실리콘 박막 두께 100 nm, 비저항 13.5~22.5 慕cm) 상에 도핑된 접촉 영역을 지정하는 것으로 시작하였다. SiO2 마스크(~100 nm)로 지정한 영역은, P509(Filmtronics)와 같은 인을 함유한 도펀트를 SOD(spin-on-dopant) 방법을 통하여 코팅시키고 연속적으로 950℃에서 5 초 동안 어닐링 하였다. 도핑 농도는 홀 측정 시스템에 의해 2 x 1018 -3 로 측정되었다. SiO2 마스크 및 SiO2 밑을 제거한 후에, 상부 Si 층(~ 100 nm)은 PDMS(polydimethylsiloxane) 스탬프를 사용한 전사 프린팅 방법을 이용하여 접착층 및 게이트 전극의 역할로서 감광성 에폭시층(~ 500 nm의 두께, ~3.1의 유전상수)을 가진 PET 코팅된 그래핀 게이트 전극으로 전사하였다.6 is a schematic diagram illustrating a manufacturing process of Si FET based graphene. Fabrication of TFTs forms a Ni catalyst layer of about 500 nm thickness on a SiO 2 / Si substrate having a thickness of at least 300 nm on top, and a gas mixture (CH 4 : H 2 : Ar containing a carbon source on the Ni catalyst layer). 50: 65: 200 sccm) The graphene film was grown on the Ni catalyst layer in a quartz tube of 4 inches in diameter at 950 ° C under a supply. The grown graphene film was about six layers, measured by optical transparency. The sheet resistance of the graphene thin film was measured by 370 ± 10 Ω / sq by a four-point probe. Then, the graphene thin film on the Ni / SiO 2 / Si wafer was transferred to PET (˜200 μm) as a lower gate electrode. Preparation of the Si channel material began by designating doped contact regions on a silicon-on-insulator (SOI) wafer (SOITEC Unibond; 100 nm thick upper single crystal silicon thin film, resistivity of 13.5-22.5 cm 3). The region designated as the SiO 2 mask (˜100 nm) was coated with a phosphorus dopant such as P509 (Filmtronics) via a spin-on-dopant (SOD) method and subsequently annealed at 950 ° C. for 5 seconds. Doping concentration was determined to be 2 x 10 18 cm -3 by a hole measuring system. After removing the SiO 2 mask and the bottom of SiO 2 , the upper Si layer (˜100 nm) was transferred to the photosensitive epoxy layer (˜500 nm thickness as a role of the adhesive layer and the gate electrode using a transfer printing method using a polydimethylsiloxane (PDMS) stamp. Transfer to a PET coated graphene gate electrode with a dielectric constant of ˜3.1).
이후 단결정 실리콘 박막 하부의 산화 실리콘층을 BOE 용액을 이용한 에칭을 통해 제거시킨 후 광경화성 고분자 재질의 스탬프를 이용한 스탬핑 방법을 통하여 상기 단결정 실리콘층을 상기 PET/그래핀/에폭시 수지 적층체의 에폭시 수지층 상에 전사시켰다. 그리고 반도체 소자가 형성되는 영역을 제외한 나머지 영역의 단결정 실리콘층을 에칭을 통하여 제거하여 패터닝함으로써 채널층으로서 단결정 실리콘 패턴을 형성하였다.Thereafter, the silicon oxide layer under the single crystal silicon thin film is removed by etching using a BOE solution, and then the single crystal silicon layer is epoxy number of the PET / graphene / epoxy resin laminate through a stamping method using a photocurable polymer material. Transcribed onto strata. The single crystal silicon pattern was formed as a channel layer by removing and patterning the single crystal silicon layer in the remaining regions except for the region where the semiconductor element is formed.
이후, 상기한 방법과 동일한 방법으로 제조한 별도의 투명 그래핀 필름을 PDMS 스탬프에 접촉시킨 후, 상기 에폭시 수지층 상에 스탬핑 방법을 통해 전사시켰다. 이후 포토리소그래피 및 에칭 등의 과정을 통하여 상기 단결정 실리콘 박막 패턴 상의 각 실리콘 영역 상에 전기적으로 접촉되는 투명 소스/드레인 전극 패턴을 형성함으로써, 플렉시블 반투명 실리콘 박막 반도체 소자를 완성하였다.Thereafter, a separate transparent graphene film prepared by the same method as described above was contacted with the PDMS stamp, and then transferred onto the epoxy resin layer by a stamping method. Then, a transparent semi-transparent silicon thin film semiconductor device was completed by forming a transparent source / drain electrode pattern electrically contacting each silicon region on the single crystal silicon thin film pattern through photolithography and etching.
[실시예 2]Example 2
실시예 1과 동일하게 수행하되, Si을 분리시키고, 자연산화막을 제거하기 위해 15초 동안 BOE를 이용하여 표면 처리를 수행한 후에, 1 cm x 1 cm 의 영역을 가진 그래핀 필름을 Si을 이동시키는데 사용된 방법과 유사한 건식 프린팅 방법을 이용하여 소스-드레인 전극으로서 이용되었다. Si 및 그래핀의 전사 수율은 99% 이상이었다. 소스-드레인 패턴은 포토레지스트 (AZ5214) 마스크 패턴을 이용한 산소 플라즈만 반응성 이온 에칭 공정에 의해, 1.2 ㎛의 두께로 형성되었다. 도 6에서 확대된 이미지는 제조된 디바이스의 개략도를 나타낸다.Perform the same as in Example 1, but after the surface treatment using BOE for 15 seconds to separate the Si, and remove the natural oxide film, the graphene film having a region of 1 cm x 1 cm to move the Si It was used as a source-drain electrode using a dry printing method similar to the method used to. The transfer yield of Si and graphene was at least 99%. The source-drain pattern was formed to a thickness of 1.2 mu m by an oxygen plasmman reactive ion etching process using a photoresist (AZ5214) mask pattern. The enlarged image in FIG. 6 shows a schematic view of the manufactured device.
도 7a는 광학적 투광성 및 기계적 유연성의 수준을 보여주기 위한 SKKU 로고 위로 위치된 하이브리드 TFT의 어레이의 광학적 이미지를 나타낸다. 도 7b는 400 및 800 nm의 파장 사이에서 디바이스의 각 부분의 광학적 광투광성을 나타낸다. PET 기판 영향을 제외한 550 nm에서 Si 채널 영역(Si/에폭시/그래핀) 및 소스/드레인 영역(그래핀/Si/에폭시/그래핀)의 광투광도는 각각, 52% 및 38% 이다. Si 층을 통한 광투과도는 실리콘의 상부 및 하부 표면 사이에 간섭에 의해 야기된 합리적 프린지 패턴을 나타낸다. 여기에서, 550 nm에서의 소스/드레인의 광투광도는 단일 그래핀층이 가시파장 범위의 광학 광투광도에서 2.3% 감소로 이어지기 때문에 그래핀의 6개 층에 해당하는 그래핀 필름 때문에 채널 영역의 광투광도보다 14% 낮았다. 또한, 그래핀 필름의 품질은 라만 분광법에 의해 확인되었다. 에폭시/PET 기판 상에 그래핀 필름과 같은 SiO2 기판 상에 그래핀 필름에서 가져온 라만 스펙트럼은 우수한 전반적 그래핀 필름의 품질을 나타내는 약한 결합 관련된 D-밴드 피크를 나타낸다.7A shows an optical image of an array of hybrid TFTs positioned over the SKKU logo to show the level of optical translucency and mechanical flexibility. 7b shows the optical light transmissivity of each part of the device between wavelengths of 400 and 800 nm. The light transmittances of the Si channel region (Si / epoxy / graphene) and source / drain region (graphene / Si / epoxy / graphene) at 550 nm excluding the PET substrate influence are 52% and 38%, respectively. Light transmission through the Si layer exhibits a rational fringe pattern caused by interference between the top and bottom surfaces of the silicon. Here, the light transmittance of the source / drain at 550 nm is the light in the channel region due to the graphene film corresponding to the six layers of graphene, since a single graphene layer leads to a 2.3% reduction in optical light transmittance in the visible wavelength range. 14% lower than light transmittance. In addition, the quality of the graphene film was confirmed by Raman spectroscopy. Raman spectra taken from graphene films on SiO 2 substrates, such as graphene films on epoxy / PET substrates, show weak bond related D-band peaks indicating good overall graphene film quality.
도 8a는 0.1 V 드레인 전압 하에서 BOE 처리 전후의 디바이스의 성능을 나타낸다. 디바이스는 접촉 저항으로 인한 BOE 처리 전후에 큰 차이를 보인다. 도 8b는 상이한 게이트 전압에서 채널 길이의 함수로서 On-상태(Ron)에서 저항을 나타낸다. Ron 대 Lc의 선형 핏(fit)의 절편으로부터 결정된 것처럼, BOE 처리 전에 측정된 접촉 저항은 BOE 처리 후에 2.5 kΩ인 반면, 약 300 kΩ이었다.8A shows the performance of the device before and after BOE treatment under 0.1 V drain voltage. The device shows a big difference before and after BOE treatment due to contact resistance. 8B shows the resistance in the on- state R on as a function of channel length at different gate voltages. As determined from the intercept of the linear fit of R on vs L c , the contact resistance measured before BOE treatment was about 300 kΩ, while 2.5 kΩ after BOE treatment.
자연 산화물이 그래핀을 S/D 전극으로 사용하면 왜 거대한 콘택 저항을 유도하는지, 그렇지 않다면 그것이 왜 그렇지 않는지 알아내기 위해, 금 박막을 그래핀 전극의 중앙에 증착하였다. 급격하게 향상된 디바이스의 성능은 접촉 저항의 감소 때문이다. 이러한 현상은 캐리어의 양 및 일함수 변화에 의해 설명될 수 있다. 그래핀은 초박형 물질이기 때문에 , 그 두께가 자연 산화물 두께와 유사하고, 그래핀의 전하 캐리어의 양은 자연 산화물을 통하여 터널을 만들기에 충분히 있지 않다. 또한, 아무것도 없는 실리콘 및 금 증착 전후의 자연산화막에서 그래핀의 일함수의 변화를 관찰하였다.A thin film of gold was deposited in the center of the graphene electrode to find out why native oxide induces huge contact resistance when graphene is used as an S / D electrode, and why not. The drastically improved device performance is due to the reduction in contact resistance. This phenomenon can be explained by the change in the amount and work function of the carrier. Since graphene is an ultra-thin material, its thickness is similar to that of natural oxide, and the amount of charge carriers in graphene is not sufficient to tunnel through the native oxide. In addition, the change of the work function of graphene was observed in the natural oxide film before and after the deposition of silicon and gold.
도 9a는 0.1 V의 드레인 전압 하에서, 채널 길이 20 ㎛ 및 폭 50 ㎛ 를 가진 Cr/Au(①), 그래핀(②) 및 ITO(③)를 포함하는 다양한 전극을 각각 이용한 단결정 Si TFT의 전달 특성을 나타낸 그래프이고, 도 9a의 삽도는 그래핀 전극을 이용한 디바이스의 광학 현미경 이미지를 나타낸다. 전극으로서 ITO를 사용한 디바이스가 2 cm2/Vs 의 이동도와 0.5 V의 문턱전압을 나타내는 반면에, 전극으로서 Cr/Au 및 그래핀을 사용한 디바이스는 350 cm2/Vs 및 320 cm2/Vs 의 이동도와 각각, 1 V 및 2.5 V 문턱전압을 나타낸다. 도 9b는 본 실시예에 따른 오믹 접촉, 저항 독립적인 전류-전압 특성을 나타내는 그래핀 전극을 가진 디바이스의 전류-전압 특성을 나타내는 그래프이다(① VG=15 V, ② VG=12 V, ③ VG=9 V, ④ VG=6 V, ⑤ VG=3 V). 도 10a는 본 실시예에 따른 플렉시블/스트레처블 반도체 소자에 있어서 ITO 어닐링 전 후의 면저항을 나타내는 도면이고, 도 10b는 본 실시예에 따른 SiO2 웨이퍼 상에 전사한 후에 그래핀 전극의 프로브 측정 그래프이다. ITO 전극을 사용한 디바이스는 Cr/Au 및 그래핀을 사용한 디바이스와 비교하여 매우 낮은 특성을 보였으며, 이것은 그래핀과 비교하여 높은 면저항을 나타낸다(도 10a, 도 10b). 이러한 높은 면저항은 PET와 같은 플라스틱 기판 상에서는 불가능한 열 어닐링에 의해 극복할 수 있다. Cr/Au 의 on-상태 저항 및 그래핀 디바이스 사이에서의 갭은 2.5 KΩ으로 나타났다. 도 11은 채널 길이 20 ㎛ 및 폭 50 ㎛를 가진 Cr/Au(①), ITO(②) 및 그래핀(③)을 포함하는 다양한 전극을 각각 이용한 디바이스의 로그 스케일의 전달 곡선이다. 각각의 디바이스는, 104, 102및 105의 온/오프(on/off) 비율을 나타낸다. 9A shows the transfer of a single crystal Si TFT using various electrodes each including Cr / Au (①), graphene (②) and ITO (③) having a channel length of 20 μm and a width of 50 μm under a drain voltage of 0.1 V. FIG. A graph showing the characteristics, and the inset of FIG. 9A shows an optical microscope image of a device using graphene electrodes. Devices using ITO as electrodes show mobility of 2 cm 2 / Vs and threshold voltages of 0.5 V, while devices using Cr / Au and graphene as electrodes move 350 cm 2 / Vs and 320 cm 2 / Vs The diagrams show the 1 V and 2.5 V threshold voltages, respectively. 9B is a graph showing current-voltage characteristics of a device having a graphene electrode showing ohmic contact and resistance-independent current-voltage characteristics according to the present embodiment (① V G = 15 V, ② V G = 12 V, ③ V G = 9 V, ④ V G = 6 V, ⑤ V G = 3 V). 10A is a view showing sheet resistance before and after ITO annealing in the flexible / stretchable semiconductor device according to this embodiment, and FIG. 10B is a graph of probe measurement of graphene electrodes after transferring onto a SiO 2 wafer according to this embodiment. to be. The device using the ITO electrode showed very low characteristics compared with the device using Cr / Au and graphene, which shows a high sheet resistance compared to the graphene (FIGS. 10A and 10B). This high sheet resistance can be overcome by thermal annealing which is not possible on plastic substrates such as PET. The gap between the on-state resistance of Cr / Au and the graphene device was 2.5 K 2.5. FIG. 11 is a log scale transfer curve of a device using various electrodes including Cr / Au (①), ITO (②) and graphene (③) each having a channel length of 20 μm and a width of 50 μm. Each device exhibits an on / off ratio of 10 4 , 10 2, and 10 5 .
우수한 광학적 및 전기적 성질뿐만 아니라, 그래핀 기반 Si TFTs는 그래핀 전극의 강건한 굽힘 특성 때문에 우수한 기계적인 신축성을 가지고 있다. 굽힘 시험은 이러한 장치의 기계적인 특성을 확인하기 위해 수행되었다. 도 12a는 굽힘 시험 전 및 시험 중 디바이스를 나타낸다. 도 12b는 0.4 %의 인장 및 압축 변형에 해당되는 20 mm 반경으로 구부리기 전, 구부리는 동안 및 구부린 후에 트랜지스터의 성능의 변화를 나타낸다. 선형 방식의 효과적인 디바이스 이동도는 변형 및 벤딩 반경의 함수로서 펴진 상태 μ0off에서 관찰된 값으로 정상화되었다. 이러한 변형의 범위를 위해, 디바이스는 μoff0eff 에서의 큰 변화없이 안정적인 작동을 나타내었다. 이것은 그래핀 기반 실리콘 트랜지스터가 높은 변형 하에서 안정적인 작동을 나타낸다고 제안한다.In addition to excellent optical and electrical properties, graphene-based Si TFTs have excellent mechanical flexibility due to the robust bending characteristics of graphene electrodes. Bending tests were performed to verify the mechanical properties of these devices. 12A shows the device before and during the bending test. FIG. 12B shows the change in transistor performance before, during and after bending to a 20 mm radius corresponding to 0.4% tensile and compressive strain. Effective device mobility in the linear fashion was normalized to the value observed in the unfolded state μ 0off as a function of deformation and bending radius. For this range of modifications, the device exhibited stable operation without significant change in μ off / μ 0eff . This suggests that graphene-based silicon transistors exhibit stable operation under high strain.
[실시예 3]Example 3
실시예 1과 동일하게 수행하되, 상기 그래핀 박막을 450 ㎛ 면적으로 증착하여 반도체 소자를 제조하였다. 도 13은 본 실시예에 따라 제조된 넓은 접촉면적을 가진 FET의 전달 특성을 나타낸 그래프이다.A semiconductor device was fabricated in the same manner as in Example 1 except that the graphene thin film was deposited with a 450 μm area. 13 is a graph showing the transfer characteristics of a FET having a large contact area manufactured according to the present embodiment.
[실시예 4]Example 4
실시예 1과 동일하게 수행하되, 상기 그래핀 박막과 실리콘 사이에 버퍼층으로서, Au 나노 파티클을 1 nm 내지 수십 nm 증착하여 반도체 소자를 제조하였다. 도 14는 본 실시예에 따라 제조된 Au 나노 파티클 형성 전후에 그래핀 전극을 가진 FET의 전달 특성을 나타낸 그래프이다.In the same manner as in Example 1, as a buffer layer between the graphene thin film and silicon, Au nanoparticles were deposited by 1 nm to several tens of nm to manufacture a semiconductor device. 14 is a graph showing the transfer characteristics of the FET having graphene electrodes before and after the formation of Au nanoparticles prepared according to the present embodiment.
[실시예 5]Example 5
실시예 1과 동일하게 수행하되, 상기 그래핀 박막 상에 접촉 저항 감소 물질로서, Au 40 nm 을 증착하여 반도체 소자를 제조하였다. 도 15는 본실시예에 따라 제조된 그래핀 박막 상에 Au 컨택층 형성 전후에 그래핀 전극을 가진 FET의 전달 특성을 나타낸 그래프이다.The semiconductor device was fabricated in the same manner as in Example 1, but by depositing Au 40 nm as a contact resistance reducing material on the graphene thin film. 15 is a graph showing the transfer characteristics of the FET having graphene electrodes before and after the formation of the Au contact layer on the graphene thin film prepared according to the present embodiment.
[실시예 6]Example 6
도 21은 본 실시예에 따른 전자 디바이스의 제조방법을 나타내는 개략도이다. 본 실시예에 따른 전자 디바이스의 제조방법을 살펴보면, 먼저, 도핑 공정(고온 공정)을 마친 실리콘 층을 Su-8을 접착층으로 사용하여 게르마늄과 산화 실리콘이 희생층으로 사용된 모재기판 위로 전사한다(도 21(a)). 이어서, 모재 기판 상에 나머지 소자 공정을 마치고 그래핀을 증착하여 전극 및 인터커넥트를 형성한다(도 21(b)). 계속해서, SU-8을 보호층으로 소자 상에 도포 및 패터닝한 후 아래의 희생층인 게르마늄을 물에 넣어 제거하여 소자를 띄운 후 고무 스탬프로 떼어낸다(도 21(c)). 이어서, 산화 실리콘을 제거하고 미리 인장 변형률을 가한 고무 기판 상에 부착시킨다(도 21(d)). 마지막으로, 스탬프를 떼어내고 가했던 인장 변형률을 제거하면, 고무 기판이 원래대로 되돌아 오면서 소자들은 압축 변형률을 받게 되어, 주름진 형태의 인터커넥트를 가진 상태로 전자 디바이스가 완성된다(도 21(e)). 완성된 전자 디바이스의 이미지는 도 22에 도시되어 있다. 21 is a schematic view showing a method of manufacturing an electronic device according to the present embodiment. Looking at the manufacturing method of the electronic device according to the present embodiment, first, the silicon layer after the doping process (high temperature process) is transferred onto the base substrate using germanium and silicon oxide as a sacrificial layer using Su-8 as an adhesive layer ( Figure 21 (a)). Subsequently, graphene is deposited on the base substrate to form an electrode and an interconnect (FIG. 21 (b)). Subsequently, after SU-8 is applied and patterned on the device as a protective layer, germanium, which is a sacrificial layer below, is added to and removed from the water to float the device, and then peeled off with a rubber stamp (FIG. 21 (c)). Subsequently, the silicon oxide is removed and adhered to the rubber substrate to which tensile strain has been previously applied (Fig. 21 (d)). Finally, removing the stamp and removing the tensile strain applied, the rubber substrate returns to its original state and the elements are subjected to compressive strain, completing the electronic device with a corrugated interconnect (FIG. 21 (e)). . An image of the completed electronic device is shown in FIG. 22.
도 23은 본 실시예에 따른 전자 디바이스의 스트레칭 테스트 이미지이다. 도 23에 도시된 바와 같이, 고무 기판의 변형률 0%에서는 소자들이 압축 변형률을 갖고 있기 때문에 인터커넥트 부분에 주름이 형성되어 압축된 것을 볼 수 있다(도 23(a)). 고무 기판의 변형률 5%에서는 압축 변형률과 인장 변형률이 서로 상쇄되어 주름이 거의 사라진 것을 볼 수 있다(도 23(b)). 10%까지 당기면 인장 변형률이 압축 변형률보다 커지면서 인터커넥트 부분이 팽팽하게 당겨지고 푸아송 효과에 따라서 인장 변형률이 가해지는 방향에 수직된 방향으로 압축 응력이 가해지면서 패드 안이 더욱 더 주름지는 것을 볼 수 있다(도 23(c)). 도 23(c)에서 인터커넥트에 실질적인 스트레인이 가해지는 것을 알 수 있다. 그래핀 인터커넥트이기 때문에 이러한 실질적인 스트레인을 견디는 것이 가능할 수 있다.23 is a stretching test image of the electronic device according to the present embodiment. As shown in FIG. 23, at 0% strain of the rubber substrate, since the elements have a compressive strain, wrinkles are formed and compressed in the interconnect portion (FIG. 23A). It can be seen that at 5% strain of the rubber substrate, the compressive strain and the tensile strain cancel each other and almost eliminate the wrinkles (Fig. 23 (b)). When pulled up to 10%, the tensile strain is greater than the compressive strain, and the interconnect portion is pulled tight, and the Poisson effect causes the compressive stress to be applied in a direction perpendicular to the direction in which the tensile strain is applied to further crease the inside of the pad ( Figure 23 (c)). It can be seen from FIG. 23C that substantial strain is applied to the interconnect. It may be possible to withstand these substantial strains because of the graphene interconnect.
도 24는 본 실시예에 따른 전자 디바이스의 전달 곡선(②) 및 이를 로그 스케일(①)로 나타낸 그래프이다. 24 is a graph showing a transmission curve ② of the electronic device according to the present embodiment and a log scale ①.
도 25은 본 실시예에 따른 전자 디바이스의 전류-전압 곡선이다.25 is a current-voltage curve of the electronic device according to the present embodiment.
도 26은 본 실시예에 따른 전자 디바이스의 변형률에 따른 전기적 특성을 나타낸 그래프이다. 도 26에 도시된 바와 같이, 고무 기판의 변형률이 10%까지 가해지고 다시 0%까지 줄여주어도 전기적 특성이 거의 변하지 않다는 것을 보여준다.26 is a graph showing electrical characteristics according to strain of the electronic device according to the present embodiment. As shown in FIG. 26, even when the strain of the rubber substrate is applied up to 10% and again down to 0%, the electrical properties hardly change.
이상, 구현예 및 실시예를 들어 본원을 상세하게 설명하였으나, 본원은 상기 구현예 및 실시예들에 한정되지 않으며, 여러 가지 다양한 형태로 변형될 수 있으며, 본원의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 많은 변형이 가능함이 명백하다.Hereinbefore, the present invention has been described in detail with reference to the embodiments and examples, but the present invention is not limited to the above embodiments and embodiments, and may be modified in various forms, and is commonly used in the art within the technical spirit of the present application. It is evident that many variations are possible by those of skill in the art.

Claims (20)

  1. 플렉시블(flexible)하고 스트레처블(stretchable)한 기판;A flexible and stretchable substrate;
    상기 기판에 형성된 반도체층; 및,A semiconductor layer formed on the substrate; And,
    상기 반도체층에 형성된 스트레처블 그래핀 전극Stretchable graphene electrodes formed on the semiconductor layer
    을 포함하는, 플렉시블/스트레처블 반도체 소자.Flexible, stretchable semiconductor device comprising a.
  2. 제 1 항에 있어서,The method of claim 1,
    상기 그래핀 전극과 상기 반도체층 사이의 자연산화막을 제거함으로써 상기 그래핀 전극과 상기 반도체층 사이의 접촉저항을 감소시킨, 플렉시블/스트레처블 반도체 소자.The contact resistance between the graphene electrode and the semiconductor layer is reduced by removing the native oxide film between the graphene electrode and the semiconductor layer.
  3. 제 1 항에 있어서,The method of claim 1,
    상기 그래핀 전극에 의하여 상기 그래핀 전극과 상기 반도체층 사이의 접촉저항을 감소시킨, 플렉시블/스트레처블 반도체 소자.The contact resistance between the graphene electrode and the semiconductor layer is reduced by the graphene electrode, flexible / stretchable semiconductor device.
  4. 제 1 항에 있어서,The method of claim 1,
    상기 그래핀 전극과 상기 반도체층 사이에 버퍼층을 형성하여 상기 그래핀 전극과 상기 반도체층 사이의 접촉저항을 감소시킨, 플렉시블/스트레처블 반도체 소자.And a buffer layer formed between the graphene electrode and the semiconductor layer to reduce contact resistance between the graphene electrode and the semiconductor layer.
  5. 제 1 항에 있어서,The method of claim 1,
    상기 그래핀 전극 상에 접촉저항 감소층을 형성하여 상기 그래핀 전극과 상기 반도체층 사이의 접촉저항을 감소시킨, 플렉시블/스트레처블 반도체 소자.Forming a contact resistance reduction layer on the graphene electrode to reduce the contact resistance between the graphene electrode and the semiconductor layer.
  6. 제 1 항에 있어서,The method of claim 1,
    상기 그래핀 전극은 투명한 것인, 플렉시블/스트레처블 반도체 소자.The graphene electrode is transparent, stretchable semiconductor device.
  7. 제 1 항에 있어서,The method of claim 1,
    상기 반도체층은 유기물 반도체 또는 무기물 반도체를 포함하는 것인, 플렉시블/스트레처블 반도체 소자.The semiconductor layer is a flexible / stretchable semiconductor device comprising an organic semiconductor or an inorganic semiconductor.
  8. 제 7 항에 있어서,The method of claim 7, wherein
    상기 무기물 반도체는 Si, 탄소나노튜브, 그래핀, 화합물 반도체, 산화물 반도체 및 이들의 조합들로 이루어진 군에서 선택되는 것인, 플렉시블/스트레처블 반도체 소자.The inorganic semiconductor is selected from the group consisting of Si, carbon nanotubes, graphene, compound semiconductors, oxide semiconductors, and combinations thereof, flexible / stretchable semiconductor device.
  9. 반도체층과 그에 형성된 그래핀 전극 사이의 접촉저항을 감소시키는 방법으로서, A method of reducing contact resistance between a semiconductor layer and graphene electrodes formed thereon,
    (1) 상기 그래핀 전극과 상기 반도체층 사이의 자연산화막을 제거하는 것, (2) 상기 그래핀 전극과 상기 반도체층과의 접촉 면적을 가능한 넓게 되도록 형성하는 것, (3) 상기 그래핀 전극과 상기 반도체층 사이에 버퍼층을 형성하는 것, 및 (4) 상기 그래핀 전극 상에 접촉저항 감소층을 형성하는 것으로 이루어진 군에서 선택되는 하나 이상을 포함하는, (1) removing the native oxide film between the graphene electrode and the semiconductor layer, (2) forming the contact area between the graphene electrode and the semiconductor layer as wide as possible, and (3) the graphene electrode And forming at least one buffer layer between the semiconductor layer and (4) forming a contact resistance reducing layer on the graphene electrode.
    반도체층과 그래핀 전극 사이의 접촉저항을 감소시키는 방법.A method of reducing the contact resistance between the semiconductor layer and the graphene electrode.
  10. 제 9 항에 있어서,The method of claim 9,
    상기 반도체층은 유기물 반도체 또는 무기물 반도체를 포함하는 것인, 반도체층과 그래핀 전극 사이의 접촉저항을 감소시키는 방법.The semiconductor layer comprises an organic semiconductor or an inorganic semiconductor, the method of reducing the contact resistance between the semiconductor layer and the graphene electrode.
  11. 제 9 항에 있어서,The method of claim 9,
    상기 (3) 및 (4)에서 상기 버퍼층 및 접촉저항 감소층 각각은 도전성 물질을 포함하여 형성되는 것인, 반도체층과 그래핀 전극 사이의 접촉저항을 감소시키는 방법.In (3) and (4), each of the buffer layer and the contact resistance reduction layer is formed of a conductive material, the method of reducing the contact resistance between the semiconductor layer and the graphene electrode.
  12. 제 11 항에 있어서,The method of claim 11,
    상기 도전성 물질은 ITO, IZO, Ti, Cu, Au, Pt, Ir, Cr, Mg, Ag, Ni, Al 및 이들의 조합들로 이루어진 군에서 선택되는 것을 포함하는 것인, 반도체층과 그래핀 전극 사이의 접촉저항을 감소시키는 방법.The conductive material is selected from the group consisting of ITO, IZO, Ti, Cu, Au, Pt, Ir, Cr, Mg, Ag, Ni, Al, and combinations thereof, the semiconductor layer and the graphene electrode How to reduce the contact resistance between.
  13. 탄성체 기판;Elastic substrates;
    상기 탄성체 기판 상에 형성되는 복수개의 소자; 및A plurality of elements formed on the elastic substrate; And
    상기 복수개의 소자를 상호 연결하는 그래핀 인터커넥터Graphene interconnects interconnecting the plurality of devices
    를 포함하는, 전자 디바이스.Comprising an electronic device.
  14. 제 13 항에 있어서,The method of claim 13,
    상기 그래핀 인터커넥터는 도핑된 그래핀층으로 형성되는 것인, 전자 디바이스.Wherein said graphene interconnect is formed of a doped graphene layer.
  15. 제 13 항에 있어서,The method of claim 13,
    상기 그래핀 인터커넥터는 복수개의 그래핀층을 적층하여 형성되는 것인, 전자 디바이스.Wherein said graphene interconnector is formed by stacking a plurality of graphene layers.
  16. 제 13 항에 있어서,The method of claim 13,
    상기 그래핀 인터커넥터는 그래핀층 및 상기 그래핀층에 증착된 금속 나노입자를 포함하는 것인, 전자 디바이스.Wherein said graphene interconnect comprises a graphene layer and metal nanoparticles deposited on said graphene layer.
  17. 제 16 항에 있어서,The method of claim 16,
    상기 금속 나노입자는 Ag, Au, Pt, Pd, Fe, Ni, Al, Sb, W, Tb, Dy, Gd, Eu, Nd, Pr, Sr, Mg, Cu, Zn, Co, Mn, Cr, V, Mo, Zr, Ba 및 이들의 조합들로 이루어진 군에서 선택되는 것을 포함하는 것인, 전자 디바이스.The metal nanoparticles are Ag, Au, Pt, Pd, Fe, Ni, Al, Sb, W, Tb, Dy, Gd, Eu, Nd, Pr, Sr, Mg, Cu, Zn, Co, Mn, Cr, V , Mo, Zr, Ba, and combinations thereof.
  18. 제 13 항에 있어서,The method of claim 13,
    상기 그래핀 인터커넥터는 금속 나노입자 및 그래핀층을 교대로 복수회 적층하여 형성되는 것인, 전자 디바이스.Wherein said graphene interconnect is formed by alternately stacking metal nanoparticles and graphene layers multiple times.
  19. 제 13 항에 있어서,The method of claim 13,
    상기 탄성체 기판은 열가소성 탄성 중합체(thermoplastic elastomer), 스티렌계 물질(styrenic materials), 올레핀계 물질(olefenic materials), 폴리올레핀(polyolefin), 폴리우레탄 열가소성 탄성 중합체(polyurethane thermoplastic elastomers), 폴리아미드(polyamides), 합성고무(synthetic rubbers), 폴리디메틸실록산(polydimethylsiloxane; PDMS), 폴리부타디엔(polybutadiene), 폴리이소부티렌(polyisobutylene), 폴리(스티렌-부타디엔-스티렌)(poly(styrene-butadiene-styrene)), 폴리우레탄(polyurethanes), 폴리클로로프렌(polychloroprene), 실리콘 및 이들의 조합들로 이루어진 군에서 선택되는 것인, 전자 디바이스.The elastomer substrate may include thermoplastic elastomers, styrenic materials, olefenic materials, polyolefins, polyurethane thermoplastic elastomers, polyamides, Synthetic rubbers, polydimethylsiloxane (PDMS), polybutadiene, polyisobutylene, poly (styrene-butadiene-styrene), poly An electronic device selected from the group consisting of urethanes, polychloroprene, silicon and combinations thereof.
  20. 제 13 항에 있어서,The method of claim 13,
    상기 탄성체 기판은 1% 내지 30%의 변형률로 변형되는 것인, 전자 디바이스.Wherein the elastomeric substrate is deformed at a strain of 1% to 30%.
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