TW200914653A - Semiconductor wafer and its manufacturing method - Google Patents

Semiconductor wafer and its manufacturing method Download PDF

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Publication number
TW200914653A
TW200914653A TW97131098A TW97131098A TW200914653A TW 200914653 A TW200914653 A TW 200914653A TW 97131098 A TW97131098 A TW 97131098A TW 97131098 A TW97131098 A TW 97131098A TW 200914653 A TW200914653 A TW 200914653A
Authority
TW
Taiwan
Prior art keywords
wafer
small
wafers
semiconductor wafer
semiconductor
Prior art date
Application number
TW97131098A
Other languages
English (en)
Chinese (zh)
Inventor
Kazushige Takaishi
Seiji Sugimoto
Original Assignee
Sumco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corp filed Critical Sumco Corp
Publication of TW200914653A publication Critical patent/TW200914653A/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
TW97131098A 2007-08-24 2008-08-15 Semiconductor wafer and its manufacturing method TW200914653A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007218956 2007-08-24

Publications (1)

Publication Number Publication Date
TW200914653A true TW200914653A (en) 2009-04-01

Family

ID=40387121

Family Applications (1)

Application Number Title Priority Date Filing Date
TW97131098A TW200914653A (en) 2007-08-24 2008-08-15 Semiconductor wafer and its manufacturing method

Country Status (3)

Country Link
JP (1) JP5294087B2 (fr)
TW (1) TW200914653A (fr)
WO (1) WO2009028399A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8981519B2 (en) * 2010-11-05 2015-03-17 Sharp Kabushiki Kaisha Semiconductor substrate, method of manufacturing semiconductor substrate, thin film transistor, semiconductor circuit, liquid crystal display apparatus, electroluminescence apparatus, wireless communication apparatus, and light emitting apparatus
KR20150038335A (ko) * 2012-07-30 2015-04-08 스미또모 가가꾸 가부시키가이샤 복합 기판의 제조 방법 및 반도체 결정층 형성 기판의 제조 방법
JP6854516B2 (ja) * 2017-07-19 2021-04-07 株式会社テンシックス 化合物半導体基板及びその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0832038A (ja) * 1994-07-15 1996-02-02 Komatsu Electron Metals Co Ltd 貼り合わせｓｏｉ基板の製造方法および貼り合わせｓｏｉ基板
JP3342442B2 (ja) * 1999-07-30 2002-11-11 キヤノン株式会社 半導体基板の作製方法及び半導体基板
JP3785067B2 (ja) * 2001-08-22 2006-06-14 株式会社東芝 半導体素子の製造方法
JP4103447B2 (ja) * 2002-04-30 2008-06-18 株式会社Ｉｈｉ 大面積単結晶シリコン基板の製造方法
WO2006114999A1 (fr) * 2005-04-18 2006-11-02 Kyoto University Dispositif a semi-conducteurs de compose et son procede de fabrication

Also Published As

Publication number Publication date
WO2009028399A1 (fr) 2009-03-05
JPWO2009028399A1 (ja) 2010-12-02
JP5294087B2 (ja) 2013-09-18

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