TW200715563A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same

Info

Publication number
TW200715563A
TW200715563A TW095125491A TW95125491A TW200715563A TW 200715563 A TW200715563 A TW 200715563A TW 095125491 A TW095125491 A TW 095125491A TW 95125491 A TW95125491 A TW 95125491A TW 200715563 A TW200715563 A TW 200715563A
Authority
TW
Taiwan
Prior art keywords
layer
semiconductor
semiconductor substrate
semiconductor device
gate electrode
Prior art date
Application number
TW095125491A
Other languages
English (en)
Inventor
Toshiki Hara
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of TW200715563A publication Critical patent/TW200715563A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
TW095125491A 2005-07-13 2006-07-12 Semiconductor device and method for manufacturing the same TW200715563A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005203918A JP2007027232A (ja) 2005-07-13 2005-07-13 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
TW200715563A true TW200715563A (en) 2007-04-16

Family

ID=37609749

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095125491A TW200715563A (en) 2005-07-13 2006-07-12 Semiconductor device and method for manufacturing the same

Country Status (5)

Country Link
US (1) US7534687B2 (zh)
JP (1) JP2007027232A (zh)
KR (1) KR100780855B1 (zh)
CN (1) CN100474630C (zh)
TW (1) TW200715563A (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5348916B2 (ja) * 2007-04-25 2013-11-20 株式会社半導体エネルギー研究所 半導体装置
JP5350655B2 (ja) * 2007-04-27 2013-11-27 株式会社半導体エネルギー研究所 半導体装置
US20110084356A1 (en) * 2008-06-02 2011-04-14 Nxp B.V. Local buried layer forming method and semiconductor device having such a layer
WO2011064891A1 (ja) 2009-11-30 2011-06-03 富士通セミコンダクター株式会社 半導体装置の製造方法、ダイナミックスレッショルドトランジスタの製造方法
JP5720244B2 (ja) * 2010-12-28 2015-05-20 富士通セミコンダクター株式会社 半導体基板の製造方法及び半導体装置の製造方法
CN102412202B (zh) * 2011-05-13 2013-12-11 上海华力微电子有限公司 一种具有自对准空洞层的son互补型金属氧化物半导体制备方法
CN104900713B (zh) 2015-06-15 2017-12-08 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示基板、显示装置
WO2018154754A1 (ja) * 2017-02-27 2018-08-30 三菱電機株式会社 半導体装置及びその製造方法
KR102318560B1 (ko) 2017-04-12 2021-11-01 삼성전자주식회사 반도체 소자
JP7151620B2 (ja) * 2019-05-15 2022-10-12 株式会社デンソー 半導体装置の製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07107937B2 (ja) * 1988-02-22 1995-11-15 日本電気株式会社 絶縁ゲート電界効果トランジスタおよびその製造方法
KR100194618B1 (ko) * 1995-12-20 1999-06-15 정선종 모스 트랜지스터의 제조방법
FR2791178B1 (fr) 1999-03-19 2001-11-16 France Telecom NOUVEAU DISPOSITIF SEMI-CONDUCTEUR COMBINANT LES AVANTAGES DES ARCHITECTURES MASSIVE ET soi, ET PROCEDE DE FABRICATION
FR2795555B1 (fr) * 1999-06-28 2002-12-13 France Telecom Procede de fabrication d'un dispositif semi-conducteur comprenant un empilement forme alternativement de couches de silicium et de couches de materiau dielectrique
JP4074051B2 (ja) * 1999-08-31 2008-04-09 株式会社東芝 半導体基板およびその製造方法
US6677209B2 (en) * 2000-02-14 2004-01-13 Micron Technology, Inc. Low dielectric constant STI with SOI devices
KR100347253B1 (ko) * 2000-11-02 2002-08-07 한민구 다결정 실리콘 박막 트랜지스터 및 그 제조방법
US6630714B2 (en) * 2001-12-27 2003-10-07 Kabushiki Kaisha Toshiba Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer
JP2003298047A (ja) * 2002-04-02 2003-10-17 Takehide Shirato 半導体装置及びその製造方法
JP4277481B2 (ja) 2002-05-08 2009-06-10 日本電気株式会社 半導体基板の製造方法、半導体装置の製造方法
KR100553683B1 (ko) * 2003-05-02 2006-02-24 삼성전자주식회사 반도체 소자 및 그 제조 방법
US7078298B2 (en) * 2003-05-20 2006-07-18 Sharp Laboratories Of America, Inc. Silicon-on-nothing fabrication process
KR100583725B1 (ko) * 2003-11-07 2006-05-25 삼성전자주식회사 부분적으로 절연된 전계효과 트랜지스터를 구비하는반도체 장치 및 그 제조 방법
KR100513310B1 (ko) * 2003-12-19 2005-09-07 삼성전자주식회사 비대칭 매몰절연막을 채택하여 두 개의 다른 동작모드들을갖는 반도체소자 및 그것을 제조하는 방법
KR100583390B1 (ko) * 2005-03-17 2006-05-26 한국과학기술원 에스오엔 모스 전계 효과 트랜지스터 및 그 제조 방법

Also Published As

Publication number Publication date
KR100780855B1 (ko) 2007-11-30
US7534687B2 (en) 2009-05-19
CN1897308A (zh) 2007-01-17
CN100474630C (zh) 2009-04-01
US20070013005A1 (en) 2007-01-18
JP2007027232A (ja) 2007-02-01
KR20070008443A (ko) 2007-01-17

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