TW200707654A - Method for fabricating a memory cell arrangement with a folded bit line arrangement, and corresponding memory cell arrangement with a folded bit line arrangement - Google Patents

Method for fabricating a memory cell arrangement with a folded bit line arrangement, and corresponding memory cell arrangement with a folded bit line arrangement

Info

Publication number
TW200707654A
TW200707654A TW095126610A TW95126610A TW200707654A TW 200707654 A TW200707654 A TW 200707654A TW 095126610 A TW095126610 A TW 095126610A TW 95126610 A TW95126610 A TW 95126610A TW 200707654 A TW200707654 A TW 200707654A
Authority
TW
Taiwan
Prior art keywords
memory cell
bit line
arrangement
forming
semiconductor substrate
Prior art date
Application number
TW095126610A
Other languages
English (en)
Other versions
TWI328864B (en
Inventor
Till Schloesser
Original Assignee
Qimonda Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=37669842&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=TW200707654(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Qimonda Ag filed Critical Qimonda Ag
Publication of TW200707654A publication Critical patent/TW200707654A/zh
Application granted granted Critical
Publication of TWI328864B publication Critical patent/TWI328864B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Landscapes

  • Semiconductor Memories (AREA)
TW095126610A 2005-07-29 2006-07-20 Method for fabricating a memory cell arrangement with a folded bit line arrangement, and corresponding memory cell arrangement with a folded bit line arrangement TWI328864B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102005035641A DE102005035641B4 (de) 2005-07-29 2005-07-29 Herstellungsverfahren für eine Speicherzellenanordnung mit gefalteter Bitleitungs-Anordnung und entsprechende Speicherzellenanordnung mit gefalteter Bitleitungs-Anordnung

Publications (2)

Publication Number Publication Date
TW200707654A true TW200707654A (en) 2007-02-16
TWI328864B TWI328864B (en) 2010-08-11

Family

ID=37669842

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095126610A TWI328864B (en) 2005-07-29 2006-07-20 Method for fabricating a memory cell arrangement with a folded bit line arrangement, and corresponding memory cell arrangement with a folded bit line arrangement

Country Status (4)

Country Link
US (1) US7772631B2 (zh)
CN (1) CN100428444C (zh)
DE (1) DE102005035641B4 (zh)
TW (1) TWI328864B (zh)

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TWI553810B (zh) * 2011-11-15 2016-10-11 海力士半導體股份有限公司 用於增加位元線接觸面積的半導體裝置及方法及包括其之模組和系統

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KR100891329B1 (ko) * 2007-01-26 2009-03-31 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR101159900B1 (ko) * 2009-04-22 2012-06-25 에스케이하이닉스 주식회사 반도체 소자 및 그 제조방법
KR101186043B1 (ko) 2009-06-22 2012-09-25 에스케이하이닉스 주식회사 반도체 소자 및 그 제조방법
KR101119774B1 (ko) * 2009-08-11 2012-03-26 주식회사 하이닉스반도체 반도체 소자 및 그 형성방법
KR101096875B1 (ko) * 2009-12-09 2011-12-22 주식회사 하이닉스반도체 매립 게이트를 갖는 반도체 소자 제조 방법
KR101699442B1 (ko) * 2010-10-13 2017-01-25 삼성전자 주식회사 수직 채널 트랜지스터를 구비한 반도체 소자의 제조 방법
US8609457B2 (en) 2011-05-03 2013-12-17 Globalfoundries Inc. Semiconductor device with DRAM bit lines made from same material as gate electrodes in non-memory regions of the device, and methods of making same
US20120292716A1 (en) * 2011-05-17 2012-11-22 Nanya Technology Corporation Dram structure with buried word lines and fabrication thereof, and ic structure and fabrication thereof
US8691680B2 (en) * 2011-07-14 2014-04-08 Nanya Technology Corp. Method for fabricating memory device with buried digit lines and buried word lines
KR101954330B1 (ko) * 2012-03-27 2019-03-05 에스케이하이닉스 주식회사 반도체 소자, 그 반도체 소자를 갖는 모듈과 시스템 및 그 반도체 소자의 제조 방법
KR20140028802A (ko) * 2012-08-30 2014-03-10 삼성전자주식회사 반도체 장치 및 그 제조방법
US9042702B2 (en) * 2012-09-18 2015-05-26 Corning Cable Systems Llc Platforms and systems for fiber optic cable attachment
US20150340368A1 (en) * 2012-12-27 2015-11-26 Ps4 Luxco S.A.R.L. Semiconductor device manufacturing method
KR102203459B1 (ko) * 2014-08-11 2021-01-15 삼성전자주식회사 반도체 소자
CN107818980B (zh) 2016-09-12 2019-07-05 联华电子股份有限公司 有源区域结构以及其形成方法
CN109509751B (zh) * 2017-09-14 2020-09-22 联华电子股份有限公司 具有字符线的半导体结构及其制作方法
CN107946302A (zh) * 2017-12-06 2018-04-20 睿力集成电路有限公司 半导体存储器及其制造方法
CN107994018B (zh) * 2017-12-27 2024-03-29 长鑫存储技术有限公司 半导体存储器件结构及其制作方法
CN114005791B (zh) * 2020-07-28 2024-05-17 长鑫存储技术有限公司 存储器件及其形成方法
CN114373754A (zh) * 2020-10-15 2022-04-19 长鑫存储技术有限公司 存储器及其制作方法
US11812605B2 (en) * 2021-01-12 2023-11-07 Winbond Electronics Corp. Semiconductor structure with air gaps for buried semiconductor gate and method for forming the same
CN115968192A (zh) * 2021-10-11 2023-04-14 长鑫存储技术有限公司 半导体结构及其形成方法
CN117542834A (zh) * 2022-08-01 2024-02-09 长鑫存储技术有限公司 存储器结构、半导体结构及其制备方法
US20240079326A1 (en) * 2022-09-06 2024-03-07 International Business Machines Corporation Buried metal signal rail for memory arrays

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JP3311070B2 (ja) * 1993-03-15 2002-08-05 株式会社東芝 半導体装置
JP2751909B2 (ja) * 1996-02-26 1998-05-18 日本電気株式会社 半導体装置の製造方法
US6172390B1 (en) * 1998-03-25 2001-01-09 Siemens Aktiengesellschaft Semiconductor device with vertical transistor and buried word line
EP1003219B1 (en) * 1998-11-19 2011-12-28 Qimonda AG DRAM with stacked capacitor and buried word line
JP2000228520A (ja) * 1999-02-05 2000-08-15 Toshiba Corp 半導体装置及びその製造方法
DE19928781C1 (de) * 1999-06-23 2000-07-06 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
US6396096B1 (en) * 2000-06-21 2002-05-28 International Business Machines Corporation Design layout for a dense memory cell structure
US6545904B2 (en) * 2001-03-16 2003-04-08 Micron Technology, Inc. 6f2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6f2 dram array and a method of isolating a single row of memory cells in a 6f2 dram array
KR100510527B1 (ko) * 2003-05-01 2005-08-26 삼성전자주식회사 스토리지 전극을 포함하는 반도체 소자 및 그 제조 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI553810B (zh) * 2011-11-15 2016-10-11 海力士半導體股份有限公司 用於增加位元線接觸面積的半導體裝置及方法及包括其之模組和系統

Also Published As

Publication number Publication date
DE102005035641A1 (de) 2007-02-08
CN100428444C (zh) 2008-10-22
TWI328864B (en) 2010-08-11
US20070023784A1 (en) 2007-02-01
DE102005035641B4 (de) 2010-11-25
US7772631B2 (en) 2010-08-10
CN1905161A (zh) 2007-01-31

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