TWI549260B - 半導體結構 - Google Patents

半導體結構 Download PDF

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TWI549260B
TWI549260B TW103138611A TW103138611A TWI549260B TW I549260 B TWI549260 B TW I549260B TW 103138611 A TW103138611 A TW 103138611A TW 103138611 A TW103138611 A TW 103138611A TW I549260 B TWI549260 B TW I549260B
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semiconductor structure
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李宗翰
施能泰
耀文 胡
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華亞科技股份有限公司
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    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/42356—Disposition, e.g. buried gate electrode
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

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Description

半導體結構
本發明係有關於一種半導體結構，特別是有關於一種改良的半導體記憶體裝置，能夠在操作該記憶體裝置時抑制字元線-字元線干擾(WL-WL disturb)或位元線-位元線耦合(BL-BL coupling)。此外，亦揭露製作該半導體結構的方法。
已知，記憶體單元佈局隨著產品的需求以及高集成度、高性能和低功耗的趨勢不斷的微縮化。
傳統的動態隨機存取記憶體(DRAM)佈局，包括字元線，其垂直於位元線。兩個字元線可以通過一個相同的主動區，形成一種主動區有兩個電晶體的結構。主動區的長度方向可與字元線相交成一個銳角。位元線接觸插塞位於所述兩個晶體管之間，並電連接到一個位元線。位元線電性耦接至源極摻雜區，其通常由所述兩個晶體管共用。
然而，上述DRAM組態容易遇到所謂的字元線-字元線干擾(WL-WL disturb)，當相鄰記憶胞之一在操作中改變了儲存於其它相鄰記憶胞的資訊狀態時，即發生字元線-字元線干擾錯誤。於是，在DRAM技術領域中，仍需要一種改進的半導體結構，其能夠減少WL-WL干擾故障。
本發明一實施例提供一種半導體結構，包含有一半導體基底；一主動區，位於該半導體基底中；兩條溝槽，截穿過該主動區並將該主動區區隔成一源極區和兩個汲極區；一馬鞍形的N+/N-/N+結構，位於該主動區的 該源極區中；以及兩個N+汲極摻雜區分別位於該兩個汲極區中。
根據本發明一實施例，另包含有兩個溝槽閘極分別埋設在該兩條溝槽的下部。所述兩個溝槽閘極包含有氮化鈦(TiN)層和鎢(W)層。一介電層，填滿所述兩條溝槽的上部。
根據本發明一實施例，所述馬鞍形的N+/N-/N+結構包括一N+源極摻雜區、兩個分開的N+延伸區域，以及一N-區126，設於該N+源極摻雜區下方且設置在該兩個N+延伸區域之間。所述兩個N+延伸區域分別沿著所述兩條溝槽的彼此相面側壁向下延伸。
根據本發明一實施例，所述兩個N+延伸區域分別與該溝槽閘極部分重疊。
1‧‧‧半導體結構
1a‧‧‧半導體結構
10‧‧‧主動區
12‧‧‧N+源極摻雜區
12’‧‧‧N+摻雜區
12”‧‧‧N+摻雜區
14、16‧‧‧N+汲極摻雜區
20‧‧‧隔離區域
50‧‧‧位元線
100‧‧‧半導體基底
102‧‧‧溝槽
110‧‧‧溝槽閘極
112‧‧‧閘極介電層
114‧‧‧氮化鈦層
116‧‧‧鎢層
122、124‧‧‧N+延伸區域
126‧‧‧N-區
126a‧‧‧N+/N-接面
130‧‧‧凹陷通道
202‧‧‧溝槽
210‧‧‧溝槽閘極
212‧‧‧閘極介電層
214‧‧‧氮化鈦層
216‧‧‧鎢層
230‧‧‧凹陷通道
310‧‧‧介電層
312‧‧‧位元線接觸
400‧‧‧自對準離子佈植製程
402‧‧‧硬遮罩層
404‧‧‧圖案化介電層
404a‧‧‧開口
406‧‧‧間隙壁層
d1、d2、d3‧‧‧接面深度
T1、T2‧‧‧電晶體
WL1、WL2‧‧‧字元線
BL‧‧‧位元線
S‧‧‧源極區
D‧‧‧汲極區
P‧‧‧間距
w‧‧‧橫向接面深
C1、C2‧‧‧電容器
BLC‧‧‧位元線接觸
第1圖例示一半導體結構的俯視圖。
第2圖是沿第1圖的線I-I'截取的示意性剖面圖。
第3圖例示本發明另一實施例半導體結構的剖面圖。
第4圖至第7圖例示製作第2圖中半導體結構的方法。
在下面的描述中，已提供許多具體細節以便徹底理解本發明。然而，很明顯，對本領域技術人員而言，本發明還是可以在沒有這些具體細節的情況下實施。此外，一些公知的系統配置和製程步驟沒有被鉅細靡遺的披露出來，因為這些應是本領域技術人員所熟知的。
同樣地，例示的裝置的實施例的附圖是半示意且未按比例繪製，並且，附圖中為了清楚呈現，某些尺寸可能被放大。此外，公開和描述多個實施例中具有通用的某些特徵時，相同或類似的特徵通常以相同的附圖標記描述，以方便於說明和描述。
請參考第1圖和第2圖。根據本發明一實施例，第1圖例示一半導體結構1的俯視圖。第2圖是沿第1圖的線I-I'截取的示意性剖面圖。如第1圖和第2圖中所示，半導體結構1被製造在主動區10上，通過隔離區域20，諸如淺溝絕緣(STI)區域，包圍主動區10。半導體結構1包括兩個串聯連接的電晶體T1和T2，嵌入在主動區10。電晶體T1和T2也被稱為具有埋入閘極和凹陷通道的溝槽閘極電晶體。但是應當理解的是，為簡化說明，記憶體陣列中的其它主動區被省略了。各擴散區的導電型僅為例示。
從第1圖中可以看出，兩個平行的字元線WL1和WL2可以穿過主動區10並將主動區10區隔成為三個部分：一源極區(S)和兩個汲極區(D)，其中，所述源極區(S)位於兩個平行的字元線WL1和WL2之間。兩個平行的字元線WL1和WL2可以沿第一方向延伸，例如，參考y軸，且兩個平行的字元線WL1和WL2可以與細長的主動區10的長度方向以銳角相交。兩個平行的字元線WL1和WL2均埋在半導體基底100中，其中半導體基底100可以包括，但不限於，P型矽基底。
如第1圖和第2圖所示，N+源極摻雜區12形成在源極區(S)。N+汲極摻雜區14和N+汲極摻雜區16形成在汲極區(D)，其相對於N+源極摻雜區12。電晶體T1包括溝槽閘極110僅位於溝槽102的下部。在溝槽102的上部填充有介電層310根據該實施例，溝槽閘極110是WL1的一部分，其可以包括氮化鈦(TiN)層114和鎢(W)層116。應當理解的是，也可使用其它閘極材料。閘極介電層112，如氧化矽層至少被設置在溝槽閘極110和半導體基底100之間。電晶體T1進一步包括N+汲極摻雜區16和N+源極摻雜區12。
同樣地，電晶體T2包括溝槽閘極210僅位於溝槽202的下部。溝槽202的上部填充有介電層310。根據該實施例，溝槽閘極210，它是WL2的一部分，可以包括氮化鈦(TiN)層214和鎢(W)層216。應當理解的是，可使用其它閘極材料。閘極介電層212，如氧化矽層至少被設置在溝槽閘極 210和半導體基底100之間。電晶體T2進一步包括N+汲極摻雜區16和N+源極摻雜區12。N+源極摻雜區12通常由兩個溝槽閘極電晶體T1和T2共用。根據本實施例中，兩個相鄰的溝槽102和202之間的間距表示為P，其中P可為20nm和30nm的範圍之間。
本發明的一個特徵在於，所述N+源極摻雜區12包含兩個N+延伸區域122和124，其沿著相面的溝槽102的側壁及溝槽202的側壁向下延伸，分別部分與溝槽閘極110和210重疊。例如，在N+延伸區域122和124可以分別僅重疊1/3~1/2溝槽閘極110和210。根據本實施例中，一個N-區126可以佈置在兩個N+延伸區域122和124之間所夾的口袋區域，由此形成兩個溝槽102和202之間的N+/N-接面126a。
根據該實施例中，N+源極摻雜區12具有接面深度d1(半導體基底的主表面與所述N+/N-接面126a之間的垂直距離)，其基本上等於N+汲極摻雜區16的接面深度d2和N+汲極摻雜區14的接面深度d3。也就是，在本實施例中，N+源極摻雜區12，N+汲極摻雜區14和N+汲極摻雜區16具有相同的接面深度。根據該實施例，在N+延伸區域122和124都具有一個橫向接面深w(從溝槽102和202的側壁橫向至N+/N-接面的距離)，其中w可為3nm和5nm的範圍之間。
如第2圖中所示，凹陷通道130定義於N+汲極摻雜區16和N+延伸區域122之間。凹陷通道230定義於N+汲極摻雜區14和N+延伸區域124之間。位元線接觸(BLC)312可形成在介電層310中，將N+源極摻雜區12電連接到上方的位元線(BL)50。位元線(BL)50沿第二方向延伸，例如，參考x軸，如第1圖中所示。一電容器(或存儲元件)C1和電容器C2可以形成在介電層310上，以分別電耦合到N+汲極摻雜區16和N+汲極摻雜區14。
綜上所述，本發明提供一種獨特的馬鞍形的N+/N-/N+結構12/122/126/124嵌入在的半導體結構1的源極區(S)中，所述半導體結構1 包括兩個串聯連接的溝槽閘極電晶體T1和T2。馬鞍形的N+/N-/N+結構12/122/126/124位於兩個相鄰的溝槽102和202之間。通過設置這種結構，字元線-字元線(WL-WL)干擾可以被抑制，且位元線-位元線(BL-BL)耦合可以被降低。
請參考第3圖。第3圖例示本發明另一實施例半導體結構1a的剖面圖。如第3圖所示，在第3圖中半導體結構1a與第2圖所示的半導體結構1之間的差異在於：第3圖中半導體結構1a的N+源極摻雜區12、N+汲極摻雜區14和N+汲極摻雜區16具有不同的接面深度。N+汲極摻雜區14/16的接面深度d2和d3比N+源極摻雜區12接面結深度d1淺。
第4圖至第7圖例示製作第2圖中半導體結構的方法。如第4圖中所示，在溝槽102和202內形成溝槽閘極110和210，以及N+摻雜區12'、14和16之後，在硬遮罩層402上形成圖案化介電層404。圖案化介電層404可包含氮化矽層，但不限於此。圖案化介電層404包括開口404a，暴露出N+摻雜區12'正上方的硬遮罩圖案。N+摻雜區12'正上方的硬遮罩圖案經由開口404a中除去。
如第5圖中所示，於N+摻雜區12’下的半導體基底100中形成一N+摻雜區12"。N+摻雜區12'’的摻雜濃度可以等於N+摻雜區12'的摻雜濃度。在其他實施例中，N+摻雜區12'’的摻雜濃度可以與N+摻雜區12’的摻雜濃度不同。
如第6圖中所示，可在圖案化介電層404上沉積間隙壁層406，例如氧化矽層。間隙壁層406共形地覆蓋著圖案化介電層404和開口404a的內表面。接著，進行自對準離子佈植製程400，通過縮小的開口部404a，將P型摻質植入到半導體基底100。可控制自對準離子佈植製程400的能量和劑量，使得P型摻質可以被注入到N+摻雜區12'下的預定深度，如此在兩個N+延伸區域122和124之間形成N-區126。
如第7圖中所示，隨後，間隙壁層406可以被移除。可選擇進行 一熱驅入製程，從而形成馬鞍形的N+/N-/N+結構12/122/126/124，嵌入在半導體結構1的源極區(S)。
應當理解的是，馬鞍形的N+/N-/N+結構12/122/126/124可以通過其他方法來形成。例如，N+延伸區域122和124可以由傾斜角度離子佈植製程或氣體擴散製程，配合合適的遮罩圖案來形成。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1‧‧‧半導體結構
12‧‧‧N+源極摻雜區
14、16‧‧‧N+汲極摻雜區
20‧‧‧隔離區域
50‧‧‧位元線
100‧‧‧半導體基底
102‧‧‧溝槽
110‧‧‧溝槽閘極
112‧‧‧閘極介電層
114‧‧‧氮化鈦層
116‧‧‧鎢層
122、124‧‧‧N+延伸區域
126‧‧‧N-區
130‧‧‧凹陷通道
202‧‧‧溝槽
210‧‧‧溝槽閘極
212‧‧‧閘極介電層
214‧‧‧氮化鈦層
216‧‧‧鎢層
230‧‧‧凹陷通道
310‧‧‧介電層
d1、d2、d3‧‧‧接面深度
T1、T2‧‧‧電晶體
BL‧‧‧位元線
S‧‧‧源極區
D‧‧‧汲極區
P‧‧‧間距
w‧‧‧橫向接面深
C1、C2‧‧‧電容器
BLC‧‧‧位元線接觸

Claims (10)

  1. 一種半導體結構，包含有：一半導體基底；一主動區，位於該半導體基底中；兩條溝槽，截穿過該主動區並將該主動區區隔成一源極區和兩個汲極區；一馬鞍形的N+/N-/N+結構，位於該主動區的該源極區中；以及兩個N+汲極摻雜區分別位於該兩個汲極區中。
  2. 如申請專利範圍第1項所述的半導體結構，其中另包含有兩個溝槽閘極分別埋設在該兩條溝槽的下部。
  3. 如申請專利範圍第1項所述的半導體結構，其中另包含有一閘極介電層位於各溝槽中。
  4. 如申請專利範圍第2項所述的半導體結構，其中所述馬鞍形的N+/N-/N+結構包括一N+源極摻雜區、兩個分開的N+延伸區域，以及一N-區，設於該N+源極摻雜區下方且設置在該兩個N+延伸區域之間。
  5. 如申請專利範圍第4項所述的半導體結構，其中所述兩個N+延伸區域分別與該溝槽閘極部分重疊。
  6. 如申請專利範圍第4項所述的半導體結構，其中所述兩個N+延伸區域分別沿著所述兩條溝槽的彼此相面側壁向下延伸。
  7. 如申請專利範圍第4項所述的半導體結構，其中該N+源極摻雜區與所述 兩個N+汲極摻雜區具有相同的接面深度。
  8. 如申請專利範圍第4項所述的半導體結構，其中所述兩個N+汲極摻雜區的接面深度比N+源極摻雜區的接面結深度淺。
  9. 如申請專利範圍第2項所述的半導體結構，其中另包含有一介電層，填滿所述兩條溝槽的上部。
  10. 如申請專利範圍第2項所述的半導體結構，其中所述兩個溝槽閘極包含有氮化鈦(TiN)層和鎢(W)層。
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