1323938 98-1-19 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種非揮發記憶體，且特別是有關於 一種具有電荷捕陷層的非揮發記憶體，以及其操作方法與 製造方法。 【先前技術】 電荷捕陷型的非揮發記憶體因製程較簡化，且每記憶 胞可有一個以上的儲存位置，所以近來已被廣泛地研究。 例如，Eitan et al. (/五五五凡μ 2〇〇〇, Vol. 21，No. 11，543-545) 提出一種局部捕陷型的金氧半(MOS)結構二位元非揮發記 憶胞，其具有η型閘極及位於基底與閘極間的氧化矽/氮化 石夕/氧化矽(ΟΝΟ)複合層，其中氮化矽層作為電荷捕陷層。 然而’由於此種記憶胞的通道長度报小，所以會造成嚴重 的擊穿漏電與第二位元效應(second_bit effect)。 另外，/五冗E 2003, 42-43揭露了一種U形的非 揮發記憶胞’其同樣具有η型閘極與ΟΝΟ複合層，其中 通道長度因形成溝渠而增加’故可解決短通道問題。該文 並敎不以基底至電荷捕陷層的頻帶間熱電洞穿隨機制 (ΒΤΒΗΗΤ)抹除該記憶胞的方法，但此方法中穿隧氧化層 容易被熱電洞損傷’使後續程式化時寫入的電荷容易茂漏。 【發明内容】 本發明的一觀點是一種非揮發記憶體，其特別適合以 閘極電洞注入機制進行抹除。 本發明的另一觀點是一種非揮發記憶體的操作方法， [s] 5 98-1-19 -、系用以操作上述本發明的非揮發記憶體。 j明的再一觀點則是—種非揮發記憶陣列的製造方 ’匕陣列包括多個本發明的非揮發記憶胞。 泪的非揮發記紐包括具有溝渠的基底、位於溝 Ξ穿隧氧陷？、配置於電荷捕陷層與半導體基底之間 化層、位於溝渠中且以電荷捕陷層以及穿隧氧化 區::相&的閑極’以及位於溝渠兩側基底中的源/及極 閘極的材質包括㈣雜半導體材料，以降低電 /5 $極注入電荷捕陷層的能障(energy barrier)。 雷本發明的非揮發記憶體中，閘極例如是直接與 摻：丰觸，以進一步降低電洞注入的能障。另外，Ρ ^ + ^體材料例如是ρ型濃摻雜複晶石夕。基底的材質例 鉍：Ρ二’此蚪源’汲極區為η型摻雜。電荷捕陷層的 -二·!疋_化石夕卿）、氧化紹⑷2〇3)、氧化給(Hf〇2)、 或五氧化二组叫基底上的溝渠例 如具有圓化的底部，以降低應力。 的非揮發記龍操作方法係用以操作上述本發 體，其在寫入時係利用由基底至電荷捕陷 層的通道熱％子注入(C跑)機制或F〇wler版dheim _ 且在抹除時利用由閘極至電荷捕陷層的閘極電 洞注入機制。 在上^本發明的非揮發記憶體操作方法中，利用間極 主入機=于抹除的步驟例如是在ρ型閘極上施加第 -電屋，亚在基底、第—源/汲極區、第二源/汲㈣上分 6 98-1-19 ί三、第四電壓，其$第二至第四電壓皆低 』、f ’ /、差異足使電洞由閘極注人電荷捕陷層中: ，為簡化操作程序’第二至第四電壓較佳彼此相同。 本發明的非揮發記憶陣列製造方法如下。首 成多條埋入式位元線，再於各埋入式位元線之 形成多個溝渠。接著於每—溝渠中形成電荷捕 底上方形成與埋人絲元線交錯的多條字元 雜半ίΐΐΐ元ί有部分填入溝渠中’且其材質包括Ρ捧 極其中’字元線的填入溝渠中的部分係作為 上述本發明的非揮發記憶陣列製造方法中，於形成 ^捕陷層之前，例如可先於各溝渠巾形成—穿随氧化 t另外’形成埋入式位元線的方法例如是先於基底上形 成夕個條狀圖案，再以條狀圖案為罩幕對基底進行離子植 2以於各條狀圖案間的基底中形成埋入式位元線。在此 ^吓於各埋入式位元線間形成溝渠的 =;間填入罩幕材料，再除去條狀圖案，然= 罩幕材枓為罩幕_基底。其中，罩幕娜例如是氧化石夕。 =卜’上述P摻雜半導體材料例如是p型濃摻雜複晶 n的材質例如是P摻雜矽，此時埋入式位元線即為 η认雜。再者’電荷捕陷層的材質可如前述者。 導許=本發記憶體的間極材質包括Ρ推雜半 : 雜閘極注入電洞至電荷捕陷層的能障 逐低於由η摻_極注人者，所以此非揮發記憶 [S] 7 1323938 98-1-19 制進行抹除，以細氧化層受損而 ¥敫俊，程式化％寫人的電·漏。 與電荷捕陷層接觸，以進—步降低電洞注人的』了^ 低抹除所需的電壓。 』崎I降 為^本發明之上述和其他目的、特徵和優點能更明顯 ，文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 <記憶陣列與記憶胞的結構> 圖1為本發明較佳實施例之非揮發記憶卩車列結構的剖 面圖’圖6F為此結構的上視圖，而圖i對應圖6F的ίν ιν， 剖面。請參照圖i與6F，此非揮發記憶陣列至少包括且有 多個溝渠110的半導縣底·、埋人式低線⑽、電荷 捕陷層140與多條字元線150。 、上述基底100例如是主要由p摻雜石夕構成的基底，且 各溝木110較佳具有圓化的底部，以降低應力而減少通道 漏電"IL。埋入式位元線120位於各溝渠110之間的基底1〇〇 中，且可藉由尚濃度η型摻雜而形成，其所用離子例如是 磷離子與/或砷離子。電荷捕捉層14〇配置於基底ι〇〇上及 溝呆110中，其材質例如是SiN、Al2〇3、Hf02、HfAlO或 Ta2〇5。此外，基底100與電荷捕陷層14〇之間較佳更設有 牙隧氧化層130，以防止程式化時寫入的電荷茂漏。 字元線150位在埋入式位元線120上方而與其交錯， 並有部分填入溝渠110中以作為閘極。字元線15〇的材質 98-1-19 低電洞從閘極注人，捕型濃摻雜複晶石夕，以降 150較佳直接陷層140的能障。再者，字元線 -步降低電洞二Γ 140接觸，如圖1所示，以進 一步降低抹除電^ ^人電荷捕陷層⑽的能障，而可進 非捏二ϋι、圖1 ’如以記憶胞騎絲看，本實施例的 括具溝渠nG的基底⑽、位於基底⑽ 二H10中的穿隧氧化層130、穿隨氧化層13〇上的 電何捕陷層14G、溝渠11G中的閘極15G，以及溝渠11〇 兩側基底100中的源/汲極區12G。其中，閘極與基底 1〇〇之間&有電荷捕陷層14〇及穿隧氧化層13Q，且閘極 150的材質包括p摻雜半導體材料，如p+摻雜複晶矽。 <記憶體的操作方法> 圖2A/2B繪示以CHEI機制/FN穿隧效應寫入上述非 揮發記憶胞的步驟，當此記憶胞係以CiiEI機制（或FN效 應)寫入時’其可儲存二(或一)位元的資料。請參照圖2a， 如要以CHEI法寫入記憶胞的左儲存位置16〇a，則例如可 在閘極150上施加5V〜10V的正電壓Vg，基底1〇〇上施加 -3V〜0V的電壓Vb，右源/汲極區120b上施加0V(V2=0V)， 並在左源/汲極區120a上施加3V〜7V的正電壓V〗，其值足 以在接近左源/汲極區120a的部分通道中引發熱電子。此 熱電子將注入靠近左源/汲極區120a的電荷捕陷層140,而 被捕陷於其中。以CHEI機制寫入右儲存位置160b的方法 則與上述者類似，只要將V!與乂2的設定值對調即可。 98-1-19 明參照圖2B，如要以fn穿随效應寫入此記憶胞，則 例如可在閘極150上施加〇v〜2〇v的相對較高電壓Vg，基 底100上施加-20V〜0V的相對較低電壓vb，並使左、右源 /沒極區職、腿浮置。此v#Vb之間的差足以^ FN穿隧效應，使電子由基底1〇〇注入電荷捕陷層14〇中。 接著’圖3A/3B緣示本發明的實施例中，之前以chei 機制/FN穿隧效應寫入的記憶胞的抹除步驟以青參照圖 3B，當之前以CHEI機制或FN穿隧效應寫入的記憶胞要 =閘極電洞注入機制抹除時，可在閘極15〇上施加第一電 以Vg)並在基底1〇〇、左源/沒極區l2〇a、右源/汲極區 120b上分施加第二、第三、第四電壓、Vi、％)，其值 皆低於第-電壓，且與第—電壓的差值足使電洞由閑極 150注^電荷捕陷層14〇，以消除其中儲存的負電荷。其 中’為fl化域程序’第二至第四電壓較佳彼此相同。上 述Vg可為0V〜20V ’且％、％、％各自可為^〜,。 二此處需制說㈣是，在叫極電洞注人機制抹除之 别以CHEI機制寫人的記憶胞時，制也纽人電荷捕陷 層H0的兩儲存位置咖與祕之間的電中性部分，如 圖3A所示。‘然*，由於累積在此部分電荷捕陷層刚中 的電洞總量依抹除時的電壓差而有—定的上限，且此上限 =曰明顯W響錢胞的啟始電壓，所以電洞注人電荷捕陷 θ H0中&的縣並不會影響到記憶胞的後續操作。 閘極=述==:’ 摻雜半導體材料製做 J降低电洞由閘極15〇注入電荷捕陷層14〇 1323938 98-1-19 矽^參照圖4與圖1，其令圖4為本發明實施例之 能^圖'，發層·氮财層·Ρ+摻雜複晶㈣極堆疊結構的 雜複曰射If料f知_基底切層_η+換 此種堆疊結構的能階圖。比較圖4〜5即可知，將 即?令的複晶石夕閉極摻雜型態由n型改成P型， 7月b障由i.4eV大幅降為〇 3eV， 造二==發==;冓揮^ =參照圖6A，首先在半導體基底1〇〇上形成多個條狀 f:曰’其中每一個皆包括閉介電層102、閘極線1〇4 (例如奸曰# 層疋在之厨製程中與其他元件 L子植^的元件)同步形成的。接著進行 植入’以在各條狀堆叠層之間的基底⑽ =線120,此離子植入步驟可能同時用以形成1他二 1的摻雜區。接著，進行相於溝填製程 電 沉積(祕CVD)製程，以形成氧化層⑽ /、入條狀堆豐層間的部分及位在條狀堆叠層上乂 者係作為稱後定義記憶陣列的溝渠時的罩幕材料。。刀’月，】 請參照圖6B’接著例如以濕_法除去⑽層 ΪΓ=所的T堆疊層上的部分同時:除去： 接者，如圖0C所不，先除去閘介 太 再以留下的_⑽為罩_，^底刚，^成= 11 1 1323938 98-1-19 ^ U0，其中所用的蝕刻配方較佳是可令各溝準110 j圓化的底部者，以降低應力而減少通道的漏電。另外， ^於^的長度可藉溝渠m的深度來調整，所以埋入式 二大1Γ二接面深度可以遠大於習知的淺S/D接面深 X 大崎低電阻。下—步剩是除去氧化層⑽。 請參照圖6D’接著在基底則上與溝渠u 130， ΗίΑΙοΠ捕陷層140的材f例如是隨、Al2〇3、Hf〇2、 〆a2〇5’其中SlN、Al2〇3較常用。穿隧氧化層130 厚度較佳為丨如，電荷義層⑽厚度較料si。 ^時參照圖6E#6F，其中_與圖1完全相同， 圖6F的IV_IV，剖面圖。接著，於基底 P掺雜的字元線150,其位於埋入式位元線= =1、之交錯’並直接與電荷捕陷層14G接觸1於 二15^為p摻雜，又直接與電荷捕陷層14〇接觸，所以恭 洞由字7L線150注人電荷獅層⑽的能障得以大幅降电 =本發明已以較佳實施例揭露如上，然其並非用以 限=本發明，任何熟習此技藝者，在不脫離本發 内：當可作些許之更動與潤飾，因此本發明“错 乾圍备視後附之申請專利範圍所界定者為準。 …又 【圖式簡單說明】 面圖= 發記_列結構的剖 圖2Α/2Β繪示本發明較佳實施例中，_ c邮機制 12 ^23938 98-1-19 /FN穿隧效應寫入圖1所示之非揮發記憶胞的步驟。 圖3A/3B繪示本發明較佳實施例中，之前利用^ 機制/FN穿隨寫人的記憶胞的閘極電洞注人抹除操作。 圖4為本發明實施例之矽基底_氧化矽層-氮化矽層、+ 摻雜複晶矽閘極堆疊結構的能階圖，圖5為習知的矽 氧化破層·氮切層_η+複晶㈣極堆疊結_能階圖二& 、圖6Α〜6Ε為本發明較佳實施例之非揮發記憶陣列製 ^方法的流程剖面圖，其巾圖6F為所得結制上視圖。 【主要元件符號說明】 100 :基底 102 :閘介電層 104 :閘極線 1〇6 :頂蓋層 108 :氧化石夕層 110 =溝渠 120 :埋入式位元線(源/汲極區） 120a ' 120b :左、右源/沒極區 130 .穿隨氧化層 140 :電荷捕陷層 150 :字元線(含閘極） 160a、160b :左、右儲存位置 IV-IV’ ：剖面線 vg、Vb ' Vi ' V2 :電壓代號 131323938 98-1-19 IX. Description of the Invention: [Technical Field] The present invention relates to a non-volatile memory, and more particularly to a non-volatile memory having a charge trapping layer, and a method of operating the same And manufacturing methods. [Prior Art] The charge trap type non-volatile memory has been extensively studied recently because of its simplified process and more than one storage position per memory cell. For example, Eitan et al. (/五五五凡μ 2〇〇〇, Vol. 21, No. 11, 543-545) proposed a partial trapping type of gold oxide half (MOS) structure two-dimensional non-volatile memory The cell has an n-type gate and a yttrium oxide/nitride/yttria (yttrium) composite layer between the substrate and the gate, wherein the tantalum nitride layer serves as a charge trapping layer. However, due to the small channel length of such a memory cell, severe breakdown leakage and a second_bit effect are caused. In addition, /5 E., 42-43 discloses a U-shaped non-volatile memory cell which also has an n-type gate and germanium composite layer in which the channel length is increased by the formation of a trench, so that the short channel problem can be solved. In this paper, the method of erasing the memory cell by the thermoelectric hole penetration between the substrate and the charge trapping layer is not used. However, in this method, the tunneling oxide layer is easily damaged by the hot hole, so that the subsequent stylization is written. The incoming charge is easy to leak. SUMMARY OF THE INVENTION One aspect of the present invention is a non-volatile memory that is particularly suitable for erasing by a gate hole injection mechanism. Another aspect of the present invention is a method of operating a non-volatile memory, [s] 5 98-1-19 - for operating the non-volatile memory of the present invention described above. A further point of view is that the manufacturer of non-volatile memory arrays comprises a plurality of non-volatile memory cells of the invention. The non-volatile notes of tears include the base with ditches, and the oxygen traps in the trenches. , disposed between the charge trapping layer and the semiconductor substrate, in the trench and in the charge trapping layer and the tunneling oxide region:: phase & idle poles and source/pole in the substrate on both sides of the trench The material of the gate includes (4) a hetero-semiconductor material to reduce the energy barrier of the electric charge hole into the charge trap layer. In the non-volatile memory of Rayben's invention, the gate is, for example, directly coupled with the dopant to further reduce the energy barrier of the hole injection. Further, the Ρ ^ + ^ body material is, for example, a p-type concentrated doped ceramsite. Example of the material of the substrate 铋: Ρ二' This source is the n-type doping of the drain region. The charge trapping layer of -2·疋疋_ fossil Xiqing), oxidized (4)2〇3), oxidized (Hf〇2), or pentoxide group called the trench on the substrate, for example, has a rounded bottom to reduce stress. The non-volatile recording method is used to operate the above-mentioned present invention, which utilizes a channel heat % sub-injection (C run) mechanism from the substrate to the charge trap layer or a F〇wler version of dheim _ at the time of writing. The erase hole injection mechanism from the gate to the charge trapping layer is utilized during erasing. In the non-volatile memory operating method of the present invention, the step of using the interpole main input=in the erasing step is, for example, applying a first electric house on the p-type gate, sub-base, first-source/drain region The second source / 汲 (four) is divided into 6 98-1-19 ί three, the fourth voltage, its $ second to fourth voltage are low, f ' /, the difference is enough to make the hole trapped by the gate In the trap layer: , in order to simplify the operation procedure, the second to fourth voltages are preferably identical to each other. The non-volatile memory array manufacturing method of the present invention is as follows. A plurality of buried bit lines are formed, and a plurality of trenches are formed in each of the buried bit lines. Then, in each of the ditches, a plurality of characters are formed above the charge trapping bottom and are interlaced with the buried wire element. The part is filled in the ditch and the material thereof includes the filling of the 'character line'. The portion into the trench is used in the method for fabricating the non-volatile memory array of the present invention. Before the formation of the trap layer, for example, the trench can be formed prior to the formation of the buried bit line. For example, the strip pattern is formed on the substrate prior to the substrate, and the substrate is ion implanted in a strip pattern to form a buried bit line in the substrate between the strip patterns. In this case, the ditch is formed between the buried bit lines; the mask material is filled in, and the strip pattern is removed, and the mask material is the mask. Among them, the cover curtain Na is, for example, an oxidized stone eve. The material of the P-doped semiconductor material, for example, the p-type heavily doped polycrystal n is, for example, a P-doped germanium. In this case, the buried bit line is η-doped. Furthermore, the material of the charge trapping layer can be as described above. Guideline = the interpolar material of the memory is composed of Ρ Ρ : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : ] 7 1323938 98-1-19 The system is erased, the fine oxide layer is damaged, and ¥敫俊, stylized % writes people's electricity and leakage. Contact with the charge trapping layer to further reduce the voltage required for the hole to be erased. The above and other objects, features, and advantages of the present invention will be apparent from the description and appended claims appended claims [Embodiment] <Structure of Memory Array and Memory Cell> Fig. 1 is a cross-sectional view of a structure of a nonvolatile memory track of a preferred embodiment of the present invention. Fig. 6F is a top view of the structure, and Fig. 1 corresponds to Fig. 6F ίν ιν, profile. Referring to Figures i and 6F, the non-volatile memory array includes at least a plurality of trenches 110, a buried low line (10), a charge trapping layer 140, and a plurality of word lines 150. The substrate 100 is, for example, a substrate mainly composed of p-doped stone, and each of the trenches 110 preferably has a rounded bottom to reduce stress and reduce channel leakage. The buried bit line 120 is located in the substrate 1 between the trenches 110 and can be formed by doping n-type doping, such as phosphorus ions and/or arsenic ions. The charge trap layer 14 is disposed on the substrate ι and in the trench 110, and is made of, for example, SiN, Al2〇3, Hf02, HfAlO or Ta2〇5. Further, between the substrate 100 and the charge trap layer 14A, a tunnel oxide layer 130 is preferably provided to prevent the charge written in the stylization from leaking. The word line 150 is interleaved over the buried bit line 120 and partially filled into the trench 110 to serve as a gate. The material of the character line 15〇 98-1-19 The low hole is injected from the gate, and the trapping type is heavily doped with the polycrystalline stone, so that the energy barrier of the direct trapping layer 140 is better. Furthermore, the word line-step reduces the hole contact of the second hole 140, as shown in Fig. 1, to further reduce the energy barrier of the electric charge trapping layer (10), and can enter the non-pinch two, Figure 1' As seen in the memory cell, the substrate (10) having the trench nG, the tunneling oxide layer 130 in the substrate (10) and the H10, the electrical trap layer 14G on the oxide layer 13, and the trench 11G are shown. The gate 15G in the middle, and the source/drain region 12G in the substrate 100 on both sides of the trench 11〇. Wherein, between the gate and the substrate, there is a charge trapping layer 14 and a tunneling oxide layer 13Q, and the material of the gate 150 comprises a p-doped semiconductor material, such as a p+ doped germanium. <Operation method of memory> Fig. 2A/2B illustrates the step of writing the above non-volatile memory cell by the CHEI mechanism/FN tunneling effect when the memory cell system is written by the CiiEI mechanism (or FN effect) It can store two (or one) bits of data. Referring to FIG. 2a, if the left storage location 16〇a of the memory cell is to be written by the CHEI method, for example, a positive voltage Vg of 5V~10V can be applied to the gate 150, and -3V~0V is applied to the substrate 1〇〇. Voltage Vb, 0V (V2 = 0V) is applied to the right source/drain region 120b, and a positive voltage V of 3V to 7V is applied to the left source/drain region 120a, which is sufficient to be close to the left source/drain region. Hot electrons are induced in part of the channel of 120a. This hot electron will be injected into the charge trapping layer 140 near the left source/drain region 120a and trapped therein. The method of writing the right storage location 160b by the CHEI mechanism is similar to the above, as long as the set values of V! and 乂2 are reversed. 98-1-19 Referring to FIG. 2B, if the memory cell is to be written with the fn wear effect, for example, a relatively high voltage Vg of 〇v~2〇v can be applied to the gate 150, and the substrate 100 is applied with - The relatively low voltage vb of 20V~0V, and the left and right source/no-polar area, the legs are floating. The difference between this v#Vb is sufficient for the FN tunneling effect, so that electrons are injected from the substrate 1〇〇 into the charge trap layer 14〇. 3A/3B, in the embodiment of the present invention, the erasing step of the memory cell previously written by the chei mechanism/FN tunneling effect is referred to FIG. 3B, when previously written by the CHEI mechanism or the FN tunneling effect. When entering the memory cell = the gate hole injection mechanism is erased, the first electrode can be applied to the gate 15〇 to Vg) and in the substrate 1〇〇, left source/no-polar region l2〇a, right source/ The second, third, fourth voltage, Vi, %) are applied to the drain region 120b, and the values are lower than the first voltage, and the difference from the first voltage is sufficient for the hole to be charged by the idle pole 150. The trap layer 14〇 is removed to eliminate the negative charge stored therein. The second to fourth voltages of the 'ffl domain program' are preferably identical to each other. The above Vg may be 0V to 20V' and each of %, %, and % may be ^~. Second, the need to say here (four) is that in the call of the polar hole injection mechanism to erase the memory cells of the CHEI mechanism, the two storage locations of the charge trap layer H0 between the coffee and the secret The electrically neutral portion is shown in Figure 3A. 'Right*, since the total amount of holes accumulated in this part of the charge trapping layer has a certain upper limit depending on the voltage difference at the time of erasing, and this upper limit = 曰 obviously W is the starting voltage of the cell, so The electric charge injection of the charge trapping θ H0 & count does not affect the subsequent operation of the memory cell. Gate ===:' Doped semiconductor material is made to reduce the hole from the gate 15〇 into the charge trapping layer 14〇1323938 98-1-19 矽^ Refer to Figure 4 and Figure 1, which makes Figure 4 The energy of the embodiment of the present invention, the hair layer, the nitrogen layer, the Ρ+ doped polycrystal (four) pole stack structure, the complex 曰 If If f _ _ 基底 基底 基底 基底 基底 基底 基底 基底 换 换Stage diagram. Comparing Fig. 4~5, it can be seen that the polycrystalline spine occlusion doping pattern of the instant is changed from n type to P type, and the July b barrier is greatly reduced from i.4eV to 〇3eV, making two == ==; 冓 ^ ^ = Referring to FIG. 6A, a plurality of strips f: 曰' are first formed on the semiconductor substrate 1 其中 each of which includes a closed dielectric layer 102 and a gate line 1 〇 4 (eg, 曰# The layer is formed synchronously with the components of the other components in the kitchen process. Subsequent implantation is performed to substrate (10) = line 120 between each strip of stacked layers, and this ion implantation step may be used simultaneously to form a doped region of 1 . Then, a phase-filling process (secret CVD) process is performed to form an oxide layer (10), a portion between the strip-like stack layers, and a strip on the strip stack layer as a trench defining a memory array. The mask material at the time. . Knife 'month,】 Please refer to FIG. 6B'. Then, for example, the portion on the T-stack layer of the layer (10) is removed by wet_method at the same time: remove: pick-up, as shown in FIG. 0C, first remove the gate and then leave The lower _(10) is the cover _, ^ bottom just, ^ into = 11 1 1323938 98-1-19 ^ U0, wherein the etching recipe used is preferably a bottom that can make each groove 110 j round to reduce stress And reduce the leakage of the channel. In addition, the length of ^^ can be adjusted by the depth of the trench m, so the depth of the buried two-in-one junction can be much larger than the conventional shallow S/D junction depth X-azaki low resistance. The next step is to remove the oxide layer (10). Referring to Fig. 6D', then the material f of the trapping layer 140 on the substrate and the trench u 130, 例如ίΑΙοΠ, for example, is, Al2〇3, Hf〇2, 〆a2〇5', of which S1N, Al2〇3 are more commonly used. The thickness of the tunnel oxide layer 130 is preferably, for example, the thickness of the charge layer (10) is larger than that of the Si. Reference is made to Fig. 6E#6F, where _ is identical to Fig. 1, and Fig. 6F is IV_IV, cross-sectional view. Next, the word line 150 doped on the substrate P is located in the buried bit line = =1, the interleaved 'and directly contacts the charge trapping layer 14G 1 and the second 15^ is p-doped, and directly The charge trapping layer 14 is in contact with each other, so that the energy barrier of the charge lion layer (10) is greatly reduced by the word 7L line 150. The present invention has been disclosed in the preferred embodiment as above, but it is not limited to the present invention. Anyone who is familiar with this skill, without departing from this issue: When a little change and refinement can be made, the invention is defined as the scope of the patent application scope attached to the application. Description] FIG. 2 is a cross-sectional view of the structure of the _ column structure. In the preferred embodiment of the present invention, the tunneling effect of the _ c mail mechanism 12 ^ 23938 98-1-19 /FN is written as shown in FIG. 1 . Steps of non-volatile memory cells. Fig. 3A/3B illustrates a gate hole injecting operation of a memory cell of a memory cell previously used in the preferred embodiment of the present invention. The energy level diagram of the ruthenium substrate _ yttria layer-tantalum nitride layer and the + doped eutectic gate stack structure of the embodiment, FIG. 5 is a conventional ruthenium oxide ruthenium layer. Nitrogen cut layer _η+ multi-crystal (four) pole stack junction _ energy diagram 2 & Figure 6 Α ~ 6 Ε is a flow chart of the non-volatile memory array method of the preferred embodiment of the present invention, the towel Figure 6F is obtained The upper view is drawn. [Main component symbol description] 100: Substrate 102: Gate dielectric layer 104: Gate line 1〇6: Top cover layer 108: Oxide layer 110 = Ditch 120: Buried bit line ( Source/drain region 120a '120b: left and right source/no-polar region 130. Wear-by-oxide layer 140: charge trapping layer 150: word line (including gate) 160a, 160b: left and right storage position IV -IV' : section line vg, Vb ' Vi ' V2 : voltage code 13