TWI224394B - 3D polysilicon read only memory and the manufacturing method thereof - Google Patents

Abstract

The present invention provides a 3D polysilicon read only memory and the manufacturing method thereof. The 3D polysilicon read only memory includes: a silicon substrate, an insulative oxide layer, an N-type heavily doped polysilicon layer, a P-type lightly doped polysilicon layer, a dielectric layer, and a silicon dioxide layer; wherein, the insulative oxide layer is located on the silicon substrate; the N-type heavily doped polysilicon layer is located on the insulative oxide layer including a plurality of word lines in parallel and separated from each other. There is an oxide layer between the word lines, and the dielectric layer is located on the word line and the oxide layer. The P-type lightly doped polysilicon layer is located on the dielectric layer, which includes a plurality of bit lines in parallel and separated from each other. The bit lines are substantially vertical to and crossed with the word lines. There is at least a neck structure in the dielectric layer formed below the bit lines, and the other oxide layer is located between the bit lines, and located on the word lines and the first oxide layer.

Description

1224394

[Technical field to which the invention belongs] The present invention relates to a read-only memory and a manufacturing method thereof, and more particularly to a three-dimensional polycrystalline silicon read-only memory and a manufacturing method thereof. [Previous technology] Non-volatile memory has a "memory" function. The data stored in the IC can be saved even after the power is turned off. Generally speaking, non-volatile memory can be roughly divided into mask-type read-only memory (MASK ROM), one-time = read-only memory (0TP R0M), erasable and programmable memory Reading memory (EPROM), erasable and programmable read-only memory (EEpR〇M), = ί 忆? (FlaSh Me · 7) and multiple programmable read-only memories. In the 0TP memory array, the connection between the transistor and the transistor V, is equipped with a fuse. When the customer uses the writer, the unnecessary fuse is blown to store the program. Due to the damage of the fuse is It is permanent, so it can only be written once. β Please refer to Figure 1. Figure 丨 shows the schematic cross-section of a conventional three-dimensional polycrystalline silicon read-only memory. In the first figure, a section is taken in the direction of the bit line = red shows that the two-dimensional polycrystalline silicon read-only memory 10 is a multilayer structure, at least ^ • silicon substrate 110, 'insulating oxide layer, N A heavily-doped polycrystalline silicon layer 2, a p-type lightly doped polycrystalline silicon layer 1, a dielectric layer 130, and an oxide layer 124. The evening chemical layer 111 is located on the stone evening substrate 110, and the N-type heavily doped evening and evening layer 120 is located on the insulating oxide layer 111. The N-type heavily doped silicon side includes several spaced apart and parallel word lines (two: ^

1224394 V. Description of the invention (2) WL), for convenience of explanation, in the first figure, it is represented by three character lines, which are the character lines 122a, 122b, and 122c, respectively. The oxide layer 124 is located between two adjacent word lines', that is, the oxide layer 124 is located between the word lines 122a and 122b, and the oxide layer 124 is located between the word lines 122b and 122c. The dielectric layer 130 is located on the word lines 122a, 122b, 122c and the oxide layer 124. The P-type lightly-doped polycrystalline silicon layer 140 is located on the dielectric layer 130, and the P-type lightly-doped polycrystalline silicon layer 140 and the dielectric layer 130 below it are further defined as several spaced apart and parallel to each other. Bit lines (BL) 1 42. A plurality of bit lines 142 and word lines 22 2a, 222b, and 222c are vertically staggered in the projection direction. From the above, it can be known that due to the structure of the conventional three-dimensional polycrystalline silicon read-only memory, in order to conduct the two polycrystalline silicon layers up and down, a sufficient voltage must be applied to achieve it. In addition, since the area where the electrical breakdown occurs is arbitrary, there is no limited area range for the interface between the two polycrystalline stone layers, so that the correct position of the memory cell is affected, and Affect the yield of the product. [Summary of the Invention] In view of this, the object of the present invention is to provide a three-dimensional polycrystalline silicon read-only memory (ROM) and a method for manufacturing the same, so as to reduce the required external breakdown voltage and learn that an electrical breakdown has occurred. The right area to increase product yield. According to the purpose of the present invention, a three-dimensional polycrystalline silicon read-only memory (ROM) and a manufacturing method thereof are provided. The three-dimensional polycrystalline silicon read-only memory includes

TW1269F (Wang Hong) .ptd 1224394

V. Description of the invention (3) Substrate, N-type heavily doped polycrystalline silicon layer, p, and this layer includes several spaced apart and flat stomachs deposited on a silicon substrate (Line, WL) ·, deposited between word lines You—Ju \ Yu line (Word is deposited on the word line and the oxide layer respectively. P ▲: 2 :: dielectric layer # 沈 lending to the dielectric screen μ g, L ja. Xinggong tf said sun stone The xi layer 'is immersed in; 丨 the layer of injustice, and this layer includes several mutual line (Bit Line, BL), the bit line and the character Xing Xing = Liu Li Cuo. Located below the bit line In the dielectric layer, 直 贝贝 pStraight father ^ ^ 1, the birth ceremony T forms a number of continuous narrow neck-shaped ', neck (neck). Another lice formation layer is deposited in the word line and the _ Ϋ, ϋ, deep, and located at the bottom of the ί Ϊ 的 Ϊ Ϊ 据 Ϊ 据 据 据 据 据 据 — 目的 目的 目的 目的-purpose, and further proposed-a kind of three-dimensional polycrystalline stone Xiyue reading board, several character lines, several bits: the body includes Shi Xiji electric Layer, the first-emulsified layer and the second oxide layer. The word line system deposition boards are separated from each other and parallel. The bit line blocks are respectively formed on two lines and are parallel and discontinuously connected. Dielectric layer Area It is formed one-to-one below the niche line block and located on the character line. In each electric layer area, a neck-like structure of an independent area is formed. And the first oxidation; 1 layer is deposited separately Between word lines, between bit line blocks and electrical layer blocks, and on word lines. Bit lines are formed on bit line blocks and the first oxide layer, and bit lines They are spaced apart from each other and parallel, and are substantially perpendicular to the word line. The bit line is a bit line block that is electrically connected. The second oxide layer is deposited between the bit lines and located between the line and the line. On the first oxide layer.

TW1269F (Wang Hong) .ptd Page 8 1224394 V. Description of the Invention (4) In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following two embodiments are given in conjunction with the accompanying drawings, The detailed description is as follows: [Embodiment] Please refer to FIG. 2A for the first embodiment. FIG. 2A shows a cross-sectional view of a three-dimensional polycrystalline silicon read-only memory according to the first embodiment of the present invention. Three-dimensional polycrystalline silicon read-only ten thinking body 2 includes: Shi Xi substrate (si 1 ic ο nsubstrate) 2 1 0, insulating oxide layer 211, N-type heavily doped polycrystalline silicon layer 220, P-type lightly doped polycrystalline silicon layer 240, dielectric The electrical layer 230 and the oxide layers 224 and 244. The insulating oxide layer 2 1 1 is located on the silicon substrate 2 10, and the N-type heavily doped spar crystal layer 2 2 0 is located on the insulating oxide layer 2 11. The N-type heavily doped polycrystalline silicon layer 2 2 0 is located on the silicon substrate 21 〇, and the N-type heavily doped polycrystalline silicon layer 2 2 〇 includes several spaced and parallel word lines (Word Line , WL), for convenience of explanation, in FIG. 2A, it is represented by three character lines, which are character lines 222a, 222b, and 222c, respectively. The oxide layer 224 is located between two adjacent word lines, that is, the oxide layer 2 2 4 is located between the word lines 2 2 2 a and 2 2 2 b, and the oxide layer 224 is located between the word lines 222b and 2 22c. between. A dielectric layer 230 is located on the word lines 222a, 222b, and 222c and the oxide layer 224. The P-type lightly doped polycrystalline silicon layer 240 is located on the dielectric layer 230, and the p-type lightly doped polycrystalline silicon layer 240 and the dielectric layer 230 below it are further defined as a plurality of spaced and parallel bit lines. (Bit Line, BL). For the convenience of illustration, in Figure 2A, it is represented by two bit lines, which are bit lines.

1224394 V. Description of the invention (5) 242a, 2 42b. The bit lines 242a, 242b and the word lines 222a, 22 2b, 222c are vertically staggered in the projection direction. In the 'dielectric layer 230, neck structures 231a and 2 3 1 b are formed. The neck structures 2 3 1 a and 2 3 1 b are located below the bit lines 2 4 2 a and 2 4 2 b, respectively. The oxide layer 2 4 4 is located between two adjacent bit lines, that is, the oxide layer 244 is located between the bit lines 242a and 242b, and the oxide layer 244 is located between the word lines 222a, 222b, 222c, and the oxide layer 224. Up. Please refer to FIGS. 2B and 2C to 2H at the same time. FIG. 2B shows a flowchart of a method for manufacturing a three-dimensional polycrystalline silicon read-only memory according to the first embodiment of the present invention, and FIGS. 2C to 2H show A flow cross-sectional view of a method for manufacturing a two-dimensional polysilicon read-only memory according to the first embodiment of the present invention. First, in step 261, a silicon substrate 21 is provided. Next, in step 263, an insulating oxide layer 211 is deposited on the substrate 210. Then, in step 265, an N-type heavily doped polycrystalline silicon layer 220 is deposited on the insulating oxide layer 211, and a plurality of spaced apart and parallel word lines are defined in the N-type heavily doped polycrystalline silicon layer 2 2 0 ( WL), for convenience of explanation, are represented by three character lines, which are character lines 22 2a, 2 22b, and 22 2c, as shown in FIG. 2C. Then, in step 267, an oxide layer 224 is deposited between two adjacent word lines, that is, the oxide layer 224 is located between the word lines 222a and 22 2b, and the oxide layer 224 is located between the word lines 222b and 2 Between 22c, as shown in Figure 2D. Then, in step 269, a dielectric layer 230 is deposited on the word lines 2 22a, 22 2b, 222c, and the oxide layer 224. Then, in step 271, a p-type lightly doped polycrystalline silicon layer 240 is formed on the dielectric layer 230. , As shown in Figure 2E. And in step 271, a plurality of mutually separated spaces are defined in the P-type lightly doped polycrystalline silicon layer 24o.

TW1269F (Wang Hong) .ptd Page 10 1224394 V. Description of the Invention (6) Open and parallel bit lines (B L). For the convenience of description, “representing a bit line” is a bit line 242a, 242b. The bit lines 242a, 242b and the character lines 222a, 222b, 222c are substantially vertically intersected in the projection direction, as shown in FIG. 2F. Then, a self-limiting (sel f -1 imi ted) wet etching method is used to engrav the dielectric layer between the two polycrystalline silicon layers. In this embodiment, it is preferable to use a hydrofluoric acid (HF) solution for etching. In step 2 73, the dielectric layer 230 is etched with a diluted hydrofluoric acid solution, so that the dielectric layer 230 forms two continuous narrow neck structures 23a1 and 231b, which are respectively located under the bit lines 242a and 242b, as shown in 2G. As shown. Finally, in step 275, an oxide layer 244 is deposited between the two bit lines 242a, 242b, and the oxide layer 244 is located above the word lines 2 22a, 222b, 2 22c, and the oxide layer 224, as shown in FIG. 2 . In the method of manufacturing the three-dimensional polycrystalline silicon read-only memory and the method described above in the first embodiment, the 'maker can repeat the steps described above according to the number of stacked layers he wants to achieve the required The number of stacked layers. In addition, the material of the dielectric material is preferably silicon dioxide (Silicon dioxide, Γ, etc.), and other materials such as nitrides or high-dielectric constants A1 0 1 electrical materials such as It is aluminum oxide (Hafnium oxide, Hf〇2) and oxidized lrcOniUmoxide, Zr〇 袓. 23. The time is the opposite; the second is to form a dielectric layer 23 0 Etching is performed.… Type etching solution to reduce the resistance of dielectric 220 and P-type _ ^ a, f, N-type heavily doped polycrystalline silicon layer I doped polycrystalline layer ♦ 24G can be used for multiple ^ / metal containing

Page 11 1224394 V. Description of the invention (7) Polysilicon / silicide / polysilicon is substituted to increase its conductivity. Again. The oxide layers 222 and 224 can be deposited using high-density plasma methods between the word lines 222a, 222b, and 222c and deposited between the bit lines 242a, 242b. Or, the material of the oxide layers 222, 2 24 may be silicon nitride (Silicon nitride,

Si3N4) 'Borop hs sphosilicate Glass (BPSG), polymer (poiymer), or a substance with a low dielectric constant. For the second embodiment, please refer to FIGS. 3A and 3B to 3F at the same time. The edge of FIG. 3A is a flowchart of a method for manufacturing a three-dimensional polycrystalline silicon read-only memory according to the second embodiment of the present invention. Figures 3B ~ 3F are cross-sectional views of the method for manufacturing a three-dimensional polycrystalline silicon read-only memory according to the second embodiment of the present invention. As shown in FIG. 3F, the three-dimensional polycrystalline silicon read-only memory 30 includes a silicon substrate 31, an insulating layer 311, an N-type heavily doped polycrystalline silicon layer 32, a dielectric layer 33, and a p-type lightly doped polycrystalline silicon layer. 34 0, 35 0 and oxide layers 344, 354. The manufacturing method of the three-dimensional polycrystalline silicon read-only memory according to the second embodiment of the present invention is as follows: First, in step 361, a silicon substrate 31 is provided. Next, in step 363, an insulating oxide layer 311 is deposited on the substrate 31o. Thereafter, in step 3 65, an N-type heavily doped polycrystalline silicon layer 32 is deposited on the insulating oxygen layer 311. Then, in step 3 67, a dielectric layer 33_-type heavy b heteropolycrystalline stone layer 320 is deposited. In step (2), the crystalline silicon layer 340 is on the dielectric layer 330, and then the mountain is described. Τ / Dan means several spaced parallel lines. For convenience, three lines are used. The element lines represent "bits 12th page TW1269F (Wang Hong) .ptd 1224394 V. Description of the invention (8) Line 3 4 2 a, 342b, 342c. In addition, the dielectric layer 330 is further formed with a dielectric layer region 332a , 332b, 332c are located one-to-one below the bit lines 342a, 342b, 342c, respectively, as shown in FIG. 3B.

After that, in step 371, a plurality of discontinuously connected bit line blocks are formed in each bit line, and at the same time, several dielectric lines are formed in the dielectric layer area relative to the bit line blocks. Electrical layer block. That is, in the bit line 342a and the dielectric layer region 33 2a, bit line blocks 342al, 242bl and dielectric layer blocks 3 32al, 332bl are further formed; in the bit line 342b and the dielectric layer region 332b In the bit line block 342a2, 242b2 and the dielectric layer block 332a2, 332b2; in the bit line 342c and the dielectric layer region 332c, the bit line block 342a3, 242b3 and the dielectric layer region are further formed. Blocks 332a3, 332b3. Bit line blocks 342al, 342a2, 342a3 and dielectric layer blocks 332al,

332a2, 332a3 are located above the same character line, that is, above character line 332a; bit line blocks 342bl, 342b2, 342b3 and dielectric layer blocks 332bl, 332b2, 332b3 are located above character line 332b, such as Figure 3C. Then, a self-limiting wet etching method is used to etch the dielectric layer between the two polycrystalline stone layers. In this embodiment, a hydrofluoric acid (HF) solution is preferably used for etching. In step 373, the dielectric layer blocks 332ai, 332a2, 332a3, 332bl, 332b2, 33 2b3 are etched using the diluted hydrofluoric acid solution, so that all four sides of each dielectric layer block are etched inward, respectively at The bit line direction BL forms a neck-shaped structure of an independent region and the word line direction WL forms another neck-shaped structure of an independent region to obtain the etched dielectric layer blocks 332al, 332a2, 332a3, and 332M. ,,

1224394 V. Description of the invention (9) 332b2 ', 332b3. Dielectric layer blocks 332al ', 332a2', 332a3 ', 332bl', 332b2 ', and 332b3' are located below the bit line blocks 342al, 342a2, 342a, 3 34 2bl, 342b2, 342b3, as shown in Figure 3D Show. Then, in step 375, an oxide layer 344 is deposited between the character lines 322a and 322b, and is located on the character lines 322a and 322b. And the oxide layer 344 is located between the adjacent bit line blocks and between the adjacent dielectric layer blocks, that is, the oxide layer 344 is located in the bit line blocks 34 2a1, 342a2, 342a, 3 3 42bl , 342b2, 342b3, and the dielectric layer blocks 332al ', 332a2, 332a3, 332bl', 332b2 ', 332b3', as shown in Figure 3E. Afterwards, in step 3 7 7, a plurality of bit lines separated from each other and formed on the bit line block and the oxide layer 3 4 4 are formed, that is, the bit line 3 5 2 a 1 is located on the bit line. On blocks 34 2al, 342bl and oxide layer 344, bit line 3 5 2 a 1 electrically connects bit line blocks 3 4 2 a 1, 3 4 2 b 1 to each other; bit line 35 2a 2 is located at the bit Bit line blocks 342a2, 3 42b2 and oxide layer 344, bit line 352a2 electrically connects bit line blocks 342a2, 3 42b2 to each other; bit line 3 52a3 is located in bit line blocks 342a3, 342b3 and oxide 'Bit line 3 52 a3 on layer 344 enables bit line blocks 3 42 a 3' 342 b 3 to be electrically connected to each other. Finally, in step 3 7.9, an oxide layer 3 5 4 is deposited between two adjacent two bit lines. That is, an oxide layer 3 5 4 is deposited between bit lines 3 5 2 a 1 and 352a 2. And the oxide layer 354 is deposited between the bit lines 352a2, 352a3 'as shown in FIG. 3F. The three-dimensional polycrystalline silicon read-only memory of the second embodiment described above and its

TW1269F (Wanghong) .ptd Page 14 1224394

V. Description of the Invention (ίο) Manufacturing> + 'The manufacturer can repeat the steps described in Figure 3A according to the number of stacked layers he wants to achieve the required stacked layers. Moreover, the material of the dielectric layer 330 is preferably silicon dioxide. The dielectric layer 33 may be formed of other materials such as silicon nitride or a high dielectric constant material. The dielectric constant material is, for example, alumina, hafnium, and oxide. When the dielectric layer 230 is formed using different materials, it is relatively necessary to use a different etching solution to etch the dielectric layer 230. In addition, in order to reduce the resistance, polysilicon / metal-containing debris / polysilicon layers (polysilicon layer) can be used for the N-type heavily doped polycrystalline silicon layer 320 and the p-type lightly doped polycrystalline silicon layer 340 and 350 respectively. / silicide / polysilicon) to increase its conductivity. Again. The oxide layers 344, 3 54 can be deposited using high-density plasma methods between the bit line blocks 342al, 342a2, 342a, 3342bl, 342b2, 342b3, and the dielectric layer blocks 332al, 332a2. ', 332a3', 332bl ', 332b2, and 332b3, between two pairs, and between bit lines 352al, 352a2 and bit lines 352a2, 352a3. Or alternatively, the material of the oxide layers 222 and 224 may be nitride; ^, glass, polymer, or a material with a low dielectric constant. It can be known from the above that the three-dimensional polycrystalline silicon read-only memory disclosed in the above two embodiments of the present invention and the manufacturing method thereof utilize a self-limiting wet etching method, preferably using a diluted hydrofluoric acid solution for a while. A dielectric layer between the two polycrystalline stone layers can obtain a neck-like structure, so that the required applied breakdown voltage can be reduced, and the two polycrystalline silicon layers can be electrically turned on. In addition, the self-limiting and self-aligning neck-like structure can further define the positive reading position of the memory cell, and learn the correct area where the electrical breakdown occurs, so as to increase the product's goodness.

TW1269F (Wang Hong) .ptd Page 15 1224394 V. Description of the Invention (11) Rate 0 In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention, anyone familiar with this Artists can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent scope.

TW1269F (Wanghong) .ptd Page 16 1224394

[Schematic description] Figure 1 shows the intention of the traditional three-dimensional polycrystalline silicon read-only memory. ~ Surface View FIG. 2A is a schematic cross-sectional view of a Sanyo read-only memory according to the first embodiment of the present invention. I. Xixi Stone Xixi Figure 2B shows a flowchart of a method for manufacturing a read-only memory according to the third embodiment of the first embodiment of the present invention. Figures 2C to 2C are schematic cross-sectional views of a method for manufacturing a sparite read-only memory according to the third embodiment of the present invention. — ,,, Xi Figure 3A shows a flowchart of a method for manufacturing a three-dimensional multi-read-only memory according to the second embodiment of the present invention. Figures 3B to 3F of the Japanese stone are flow cross-sectional views of a method for manufacturing a three-dimensional polycrystalline stone read-only memory according to the second embodiment of the present invention. Description of drawings: 10, 20, 30 Two-dimensional polycrystalline read-only memory 11 0, 2 1 0, 31 0: silicon substrate 11 1, 2 1 1, 31 1: insulating oxide layer 120, 22 0, 32 0: N-type heavily doped polycrystalline stone layers 122a, 122b, 122c, 222a, 222b, 222c, 322a, 3 22b: word lines 124, 224, 244, 324, 344: oxide g 130, 23 0, 33 0: Dielectric layer ^ 140, 24 0, 34 0, 35 0: P-type lightly doped polycrystalline stone layer

1224394 Schematic description of 142, 242a, 242b, 342a, 342b, 342c, 352al, 352a2, 352a3 ... Bit line 231a, 231b: Neck structure 33 2a, 3 32b, 332c: Dielectric layer areas 332al, 332a2, 332a3, 332bl, 332b2, 332b3, 332al ', 332 a2', 332a3 ', 332bl', 332b2 ', 3 32b3' · Dielectric layer blocks 342bl, 342b2, 342b3, 342al, 342a2, 342a3: Bit line area Piece

TW1269F (Wanghong) .ptd Page 18

Claims (1)

1224394 VI. Scope of patent application 1. A three-dimensional polycrystalline stone (P0lysi 1 icon) read only memory (ROM), including at least a silicon substrate (silicon substrate); an insulating oxide layer ( Silicon dioxide (Si02) is located on the silicon substrate, an N-type heavily doped polycrystalline silicon layer is located on the insulating oxide layer, and the N-type heavily doped polycrystalline silicon layer includes a plurality of spaced apart and parallel Word Line (WL); a first oxide layer is located between each of the word lines; a dielectric layer is located between the word lines and the first oxide layer are P-type The lightly doped polycrystalline silicon layer is located on the dielectric layer, and the P-type lightly doped polycrystalline silicon layer includes a plurality of spaced apart and parallel bit lines (BL lines) BL, the bits Lines and the character lines are substantially staggered vertically; at least one neck structure is formed in each of the dielectric layers below the bit lines; and an oxide layer is The second oxide layer is located on each of the word lines and the first oxide layers. An oxide layer worker. 2. The three-dimensional polycrystalline silicon read-only memory as described in item 1 of the scope of the patent application, wherein the N-type heavily doped polycrystalline silicon layer is a polycrystalline silicon / metal-containing silicide / polycrystalline silicon layer (5). ^] ^^ (^ / 1) 〇1 ^^^ 〇1 ^. 3 ^ The P-type lightly doped polycrystalline silicon in the three-dimensional polycrystalline silicon read-only memory as described in the scope of application for patent! Hairline system is polycrystalline / metal-containing stone TW1269F (Wang Hong). Ptd f 19 pages 1224394 6. Scope of patent application (polysilicone / silicide / polysilicone). 4 · The three-dimensional polycrystalline silicon read-only memory according to item 1 of the scope of the patent application, wherein the first oxide layer and the second oxide layer are deposited using high-density plasma method on each of the word lines. And between each of the bit lines. 5. The three-dimensional polycrystalline silicon read-only memory according to item 1 of the scope of the patent application, wherein the material of the first oxide layer and the second oxide layer is silicon nitride (Si 1 icon ni tride (Si3N4)). 6. The three-dimensional polycrystalline silicon read-only memory according to item 1 of the scope of the patent application, wherein the material of the first oxide layer and the second oxide layer is Borophosphosilicate Glass (BPSG). 7 · The three-dimensional polycrystalline silicon read-only memory according to item 1 of the scope of patent application, wherein the material of the first oxide layer and the second oxide layer is a polymer 〇 8 · The scope of patent application The three-dimensional polycrystalline silicon read-only memory of item 1, wherein the material of the first oxide layer and the second oxide layer is a substance with a low dielectric constant. 9. The three-dimensional polycrystalline silicon read-only memory according to item 1 of the scope of the patent application, wherein the material of the dielectric layer is selected from the group consisting of silicon dioxide (Si02), silicon nitride (Si3N4) Among the group consisting of Aluminum oxide 'Al203, Oxygen oxide (Hfnium oxide) and Zirconium oxide (Zrconium oxide) 1 0 · —Three-dimensional polycrystalline silicon read-only memory (ROM) Manufacture method, TW1269F (wanghong) .ptd Page 20 1224394 6. The scope of patent application includes at least: providing a substrate; depositing an insulating oxide layer on the substrate; depositing a first polycrystalline silicon layer on the insulating oxide layer And define a plurality of spaced and parallel word lines (Word Line, WL) in the first polycrystalline silicon layer; depositing a first oxide layer between each of the word lines; depositing a A dielectric layer is formed on the word lines and the first oxide layer; a second polycrystalline silicon layer is formed on the dielectric layer, and a plurality of spaced apart and defined in the second polycrystalline silicon layer are defined; Parallel bit lines (BL), the bit lines and the word lines are substantially staggered vertically; using a wet etching method, the dielectric layer is etched so as to be located on the bit lines The dielectric layers below form a neck structure respectively; and a second oxide layer is deposited between each of the bit lines, and the second oxide layer is located on the first polycrystalline silicon layers and On the first oxide layers. 11. The manufacturing method as described in item 10 of the scope of the patent application, wherein the first polycrystalline silicon layer is an N-type heavily doped polycrystalline silicon layer, and the second polycrystalline silicon layer is a P-type light-doped polycrystalline silicon layer. Crystal seconds layer. 12. The manufacturing method as described in item 11 of the scope of the patent application, wherein the N-type heavily doped polycrystalline silicon layer is a polycrystalline silicon material / metallic material / polycrystalline silicon material. 13. The manufacturing method according to item 11 of the scope of patent application, wherein the P-type lightly doped polycrystalline silicon layer is a polycrystalline silicon / metal-containing silicide / polycrystalline silicon TW1269F (Wang Hong) .ptd Page 21 1224394 6. Application for patent scope. 14. The manufacturing method described in item 1Q of the patent application scope, wherein the steps of depositing the first oxide layer between each of the word lines, and depositing the second oxide layer on each of the bit lines The less frequent step is the use of high-density plasma method. '15. The manufacturing method as described in item No. 0 of the application, wherein the materials of the first oxide layer and the second oxide layer are silicon nitride. 16. The manufacturing method as described in item 10 of the scope of patent application, wherein the material of the first oxide layer and the second oxide layer is borophosphosilicate glass. 17. The manufacturing method as described in item 1 of the scope of the patent application, wherein the material of the first oxide layer and the second oxide layer is a polymer. 18. The manufacturing method as described in item 1 of the scope of the patent application, wherein the material of the first oxide layer and the second oxide layer is a material with a low dielectric constant. 19. According to the manufacturing method described in Item 10 of the scope of patent application, the material of the dielectric f in the bean is selected from the group consisting of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, and emulsified hafnium. 2． · Two-dimensional polycrystalline quasi-reading memory 'includes at least: a silicon substrate; an insulating oxide layer on the silicon substrate; a plurality of spaced and parallel word lines on the layer, which are located in the Insulation and oxidation of some characters ΐ ί ΐ Parallel and discontinuous bit line blocks, which are located in the TW1269F (wanghong) .ptd page 22 ~ ..... — ~ 1 " " 1224394 VI. Patent Application A range of a plurality of dielectric layer regions are respectively located below the bit line blocks, and the dielectric layer regions are located on the character lines; at least one neck-shaped structure is respectively located on the bit line blocks. In the dielectric layer region, a first oxide layer is located between the word lines, each of the bit line blocks, and each of the dielectric layer blocks, and is located on the word lines. A plurality of bit lines, located on the bit line blocks and the first oxide layer, the bit lines are spaced apart from and parallel to each other, and are vertically staggered with the character lines, and The bit lines are the bit line blocks of the electrical connection portion; and a second oxide layer Lines were located between each of the plurality of bit lines, and the second oxide layer on the wordlines and the first / oxide layer. 21. The two-dimensional polycrystalline silicon read-only memory according to item 20 of the scope of patent application, wherein the first oxide layer and the second oxide layer are deposited using high-density electropolymerization method to deposit on each The word lines are respectively deposited between the bit lines of the mother. 2 2. The two-dimensional polycrystalline silicon read-only memory described in item 20 of the scope of the patent application, wherein the material of the first oxide layer and the second oxide layer is nitride nitride. 23. If the scope of the patent application is item 20 In the three-dimensional polycrystalline silicon read-only memory, the material of the first oxide layer and the second oxide layer is borophosphosilicate glass. 2 4 · The two-dimensional polycrystalline stone read-only memory as described in item 20 of the scope of patent application, wherein the material of the first halide layer and the second oxide layer is polymerized. 1224394 6. Scope of Patent Application. 25. The three-dimensional polycrystalline silicon read-only memory according to item 20 of the scope of the patent application, wherein the material of the first oxide layer and the second oxide layer is a substance with a low dielectric constant. 26. The two-dimensional polycrystalline silicon read-only memory as described in item 20 of the scope of patent application, wherein the material of the dielectric layer is selected from the group consisting of silicon dioxide, silicon nitride, oxidized oxide, and oxidized gas. Into a group of people. 27. A method for manufacturing a three-dimensional polycrystalline silicon read-only memory (ROM), at least including: providing a substrate; depositing an insulating oxide layer on the substrate; depositing a first polycrystalline silicon layer on the insulating oxide layer Depositing a dielectric layer on the first polycrystalline silicon layer; depositing a second polycrystalline silicon layer on the dielectric layer, and defining a plurality of first bits in the second polycrystalline silicon layer Lines, and a plurality of dielectric layer regions are defined in the dielectric layer; the first bit lines are spaced apart and parallel to each other; the dielectric layer regions are spaced apart and parallel to each other, and are located at each of the branches respectively. ”Below the bit line; — forming a plurality of discontinuously connected bit line blocks in each of the first bit lines, and forming a plurality of dollar line areas in the dielectric layer regions relative to the $ line lines; Block of the dielectric layer block, the bit line blocks are spaced apart from each other I parallel 'the dielectric layer blocks located under the bit line blocks are also spaced apart and parallel to each other; # Use a wet Touch-engraving method 'to etch these dielectric layer blocks TW1269F (Wanghong) .ptd Page 24 —— '--- 1224394 VI. Patent Application Range These dielectric layer blocks form a neck structure in the direction of the bit line and another neck shape in the direction of the word line. Structure; depositing a first oxide layer between the word lines, each bit line block, and each dielectric layer block, and located on the word lines; One bit line, forming a plurality of second bit lines on the bit line blocks and the first oxide layer, respectively, the second bit lines are spaced apart from each other and parallel, and are parallel to the characters The lines are substantially vertically staggered, and the second bit lines are electrically connected to the bit line blocks; and a second oxide layer is deposited between each of the second bit lines. 28. The manufacturing method as described in item 27 of the scope of the patent application, wherein the first polycrystalline silicon layer is an N-type heavily doped polycrystalline silicon layer, and the second polycrystalline silicon layer is a P-type light-transmuted polycrystalline silicon Shi Xi layer. 29. The manufacturing method as described in item 28 of the patent application, wherein the N-type heavily doped polycrystalline silicon layer is a polycrystalline silicon / metal-containing silicide / polycrystalline silicon layer. 30. The manufacturing method as described in item 28 of the scope of patent application, wherein the P-type lightly doped polycrystalline silicon layer is a polycrystalline silicon / metal-containing silicide / polycrystalline silicon layer. 31. The manufacturing method as described in item 27 of the scope of patent application, wherein the steps of depositing the first oxide layer between each of the word lines, and depositing the second oxide layer between each of the bit lines Between steps, a high-density plasma method is used. 32. The manufacturing method according to item 27 of the scope of patent application, wherein the material of the first oxide layer and the second oxide layer is silicon nitride. TW1269F (Wang Hong) .ptd Page 25 1224394 VI. Application for patent scope 33. The manufacturing method described in item 27 of the scope of patent application, wherein the material of the first oxide layer and the second oxide layer is borophosphosilicate glass . 34. The manufacturing method as described in claim 27, wherein the material of the first oxide layer and the second oxide layer is a polymer. 35. The manufacturing method as described in item 27 of the scope of patent application, wherein the material of the first oxide layer and the second oxide layer is a material with a low dielectric constant. 36. The manufacturing method according to item 27 of the scope of patent application, wherein the material of the dielectric layer and the second oxide layer is selected from the group consisting of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, and zirconia. Ethnic group. TW1269F (Wanghong) .ptd Page 26