TW200520207A - 3D polysilicon read only memory and the manufacturing method thereof - Google Patents
3D polysilicon read only memory and the manufacturing method thereofInfo
- Publication number
- TW200520207A TW200520207A TW092134463A TW92134463A TW200520207A TW 200520207 A TW200520207 A TW 200520207A TW 092134463 A TW092134463 A TW 092134463A TW 92134463 A TW92134463 A TW 92134463A TW 200520207 A TW200520207 A TW 200520207A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- oxide layer
- memory
- doped polysilicon
- bit lines
- Prior art date
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title abstract 7
- 229920005591 polysilicon Polymers 0.000 title abstract 7
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
Landscapes
- Semiconductor Memories (AREA)
Abstract
The present invention provides a 3D polysilicon read only memory and the manufacturing method thereof. The 3D polysilicon read only memory includes: a silicon substrate, an insulative oxide layer, an N-type heavily doped polysilicon layer, a P-type lightly doped polysilicon layer, a dielectric layer, and a silicon dioxide layer; wherein, the insulative oxide layer is located on the silicon substrate; the N-type heavily doped polysilicon layer is located on the insulative oxide layer including a plurality of word lines in parallel and separated from each other. There is an oxide layer between the word lines, and the dielectric layer is located on the word line and the oxide layer. The P-type lightly doped polysilicon layer is located on the dielectric layer, which includes a plurality of bit lines in parallel and separated from each other. The bit lines are substantially vertical to and crossed with the word lines. There is at least a neck structure in the dielectric layer formed below the bit lines, and the other oxide layer is located between the bit lines, and located on the word lines and the first oxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW92134463A TWI224394B (en) | 2003-12-05 | 2003-12-05 | 3D polysilicon read only memory and the manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW92134463A TWI224394B (en) | 2003-12-05 | 2003-12-05 | 3D polysilicon read only memory and the manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI224394B TWI224394B (en) | 2004-11-21 |
| TW200520207A true TW200520207A (en) | 2005-06-16 |
Family
ID=34568701
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW92134463A TWI224394B (en) | 2003-12-05 | 2003-12-05 | 3D polysilicon read only memory and the manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI224394B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI478324B (en) * | 2009-01-13 | 2015-03-21 | Macronix Int Co Ltd | Memory array and method for manufacturing the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9171847B1 (en) * | 2014-10-02 | 2015-10-27 | Inotera Memories, Inc. | Semiconductor structure |
-
2003
- 2003-12-05 TW TW92134463A patent/TWI224394B/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI478324B (en) * | 2009-01-13 | 2015-03-21 | Macronix Int Co Ltd | Memory array and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI224394B (en) | 2004-11-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MK4A | Expiration of patent term of an invention patent |