TW200639969A - Treatmeny of a removed layer of Si1-yGey - Google Patents

Treatmeny of a removed layer of Si1-yGey

Info

Publication number
TW200639969A
TW200639969A TW095101822A TW95101822A TW200639969A TW 200639969 A TW200639969 A TW 200639969A TW 095101822 A TW095101822 A TW 095101822A TW 95101822 A TW95101822 A TW 95101822A TW 200639969 A TW200639969 A TW 200639969A
Authority
TW
Taiwan
Prior art keywords
layer
donor wafer
ygey
zone
wafer
Prior art date
Application number
TW095101822A
Other languages
English (en)
Other versions
TWI307935B (en
Inventor
Nicolas Daval
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of TW200639969A publication Critical patent/TW200639969A/zh
Application granted granted Critical
Publication of TWI307935B publication Critical patent/TWI307935B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V
TW095101822A 2005-01-19 2006-01-18 Treatment of a removed layer of si1-ygey TWI307935B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0500524A FR2880988B1 (fr) 2005-01-19 2005-01-19 TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE
US11/145,482 US7232737B2 (en) 2005-01-19 2005-06-02 Treatment of a removed layer of silicon-germanium

Publications (2)

Publication Number Publication Date
TW200639969A true TW200639969A (en) 2006-11-16
TWI307935B TWI307935B (en) 2009-03-21

Family

ID=34979043

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095101822A TWI307935B (en) 2005-01-19 2006-01-18 Treatment of a removed layer of si1-ygey

Country Status (5)

Country Link
US (1) US7232737B2 (zh)
JP (1) JP4975642B2 (zh)
CN (1) CN101142669B (zh)
FR (1) FR2880988B1 (zh)
TW (1) TWI307935B (zh)

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US7538010B2 (en) * 2003-07-24 2009-05-26 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating an epitaxially grown layer
FR2896619B1 (fr) * 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite a proprietes electriques ameliorees
US7863157B2 (en) * 2006-03-17 2011-01-04 Silicon Genesis Corporation Method and structure for fabricating solar cells using a layer transfer process
FR2912258B1 (fr) * 2007-02-01 2009-05-08 Soitec Silicon On Insulator "procede de fabrication d'un substrat du type silicium sur isolant"
FR2912259B1 (fr) * 2007-02-01 2009-06-05 Soitec Silicon On Insulator Procede de fabrication d'un substrat du type "silicium sur isolant".
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WO2009056169A1 (en) * 2007-10-31 2009-05-07 Robert Bosch Gmbh Drive belt ring component and manufacturing method therefor
JP2010135538A (ja) * 2008-12-04 2010-06-17 Sumco Corp 貼り合わせウェーハの製造方法
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FR2957190B1 (fr) 2010-03-02 2012-04-27 Soitec Silicon On Insulator Procede de realisation d'une structure multicouche avec detourage par effets thermomecaniques.
CN102347267B (zh) * 2011-10-24 2013-06-19 中国科学院上海微系统与信息技术研究所 一种利用超晶格结构材料制备的高质量sgoi及其制备方法
CN103165512A (zh) * 2011-12-14 2013-06-19 中国科学院上海微系统与信息技术研究所 一种超薄绝缘体上半导体材料及其制备方法
CN103165511B (zh) * 2011-12-14 2015-07-22 中国科学院上海微系统与信息技术研究所 一种制备goi的方法
US8946054B2 (en) 2013-04-19 2015-02-03 International Business Machines Corporation Crack control for substrate separation
US9058990B1 (en) 2013-12-19 2015-06-16 International Business Machines Corporation Controlled spalling of group III nitrides containing an embedded spall releasing plane
US9870940B2 (en) * 2015-08-03 2018-01-16 Samsung Electronics Co., Ltd. Methods of forming nanosheets on lattice mismatched substrates
FR3048548B1 (fr) * 2016-03-02 2018-03-02 Soitec Procede de determination d'une energie convenable d'implantation dans un substrat donneur et procede de fabrication d'une structure de type semi-conducteur sur isolant

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FR2852143B1 (fr) 2003-03-04 2005-10-14 Soitec Silicon On Insulator Procede de traitement preventif de la couronne d'une tranche multicouche
FR2858462B1 (fr) 2003-07-29 2005-12-09 Soitec Silicon On Insulator Procede d'obtention d'une couche mince de qualite accrue par co-implantation et recuit thermique
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FR2867310B1 (fr) * 2004-03-05 2006-05-26 Soitec Silicon On Insulator Technique d'amelioration de la qualite d'une couche mince prelevee

Also Published As

Publication number Publication date
JP2008527752A (ja) 2008-07-24
JP4975642B2 (ja) 2012-07-11
FR2880988A1 (fr) 2006-07-21
CN101142669A (zh) 2008-03-12
US20060160328A1 (en) 2006-07-20
CN101142669B (zh) 2010-08-18
US7232737B2 (en) 2007-06-19
FR2880988B1 (fr) 2007-03-30
TWI307935B (en) 2009-03-21

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees