TW200625413A - Epitaxial wafer and method for manufacturing epitaxial wafer - Google Patents

Epitaxial wafer and method for manufacturing epitaxial wafer

Info

Publication number
TW200625413A
TW200625413A TW094142833A TW94142833A TW200625413A TW 200625413 A TW200625413 A TW 200625413A TW 094142833 A TW094142833 A TW 094142833A TW 94142833 A TW94142833 A TW 94142833A TW 200625413 A TW200625413 A TW 200625413A
Authority
TW
Taiwan
Prior art keywords
epitaxial layer
epitaxial
thickness
epitaxial wafer
substrate
Prior art date
Application number
TW094142833A
Other languages
English (en)
Inventor
Shoichi Takamizawa
Ryuji Sayama
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Publication of TW200625413A publication Critical patent/TW200625413A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Chemical Vapour Deposition (AREA)
TW094142833A 2004-12-28 2005-12-05 Epitaxial wafer and method for manufacturing epitaxial wafer TW200625413A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004381493A JP2006190703A (ja) 2004-12-28 2004-12-28 エピタキシャルウェーハの製造方法及びエピタキシャルウェーハ

Publications (1)

Publication Number Publication Date
TW200625413A true TW200625413A (en) 2006-07-16

Family

ID=36614681

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094142833A TW200625413A (en) 2004-12-28 2005-12-05 Epitaxial wafer and method for manufacturing epitaxial wafer

Country Status (5)

Country Link
JP (1) JP2006190703A (zh)
KR (1) KR20070094904A (zh)
CN (1) CN100541727C (zh)
TW (1) TW200625413A (zh)
WO (1) WO2006070556A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9340900B2 (en) 2006-09-06 2016-05-17 Sumco Corporation Epitaxial wafer and method of producing same

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5040814B2 (ja) * 2008-05-30 2012-10-03 株式会社デンソー 炭化珪素半導体装置の製造方法
JP2010028011A (ja) * 2008-07-24 2010-02-04 Sumco Corp エピタキシャル層の膜厚測定方法、エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ製造工程管理方法
JP5795461B2 (ja) 2009-08-19 2015-10-14 株式会社Sumco エピタキシャルシリコンウェーハの製造方法
JP2011091143A (ja) * 2009-10-21 2011-05-06 Sumco Corp シリコンエピタキシャルウェーハの製造方法
JP2011187887A (ja) * 2010-03-11 2011-09-22 Toyota Motor Corp エピタキシャルウエハの製造方法
JP5644401B2 (ja) 2010-11-15 2014-12-24 株式会社Sumco エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ
JP2012174935A (ja) * 2011-02-22 2012-09-10 Shin Etsu Handotai Co Ltd エピタキシャルウェーハの製造方法
JP5479390B2 (ja) 2011-03-07 2014-04-23 信越半導体株式会社 シリコンウェーハの製造方法
CN103354242B (zh) * 2013-06-17 2016-09-14 上海晶盟硅材料有限公司 高压功率器件用极厚外延片及其制造方法
US10490437B2 (en) 2015-04-07 2019-11-26 Sumco Corporation Susceptor, vapor deposition apparatus, vapor deposition method and epitaxial silicon wafer
JP6485327B2 (ja) * 2015-04-07 2019-03-20 株式会社Sumco サセプタ、気相成長装置および気相成長方法
JP6515866B2 (ja) * 2016-05-09 2019-05-22 信越半導体株式会社 エピタキシャルウェーハの評価方法
DE102018200415A1 (de) 2018-01-11 2019-07-11 Siltronic Ag Halbleiterscheibe mit epitaktischer Schicht
JP6919579B2 (ja) * 2018-01-17 2021-08-18 株式会社Sumco 貼り合わせウェーハの製造方法、貼り合わせウェーハ
JP2018121070A (ja) * 2018-03-23 2018-08-02 富士通セミコンダクター株式会社 半導体装置の製造方法
JP7151688B2 (ja) * 2019-11-01 2022-10-12 三菱電機株式会社 炭化珪素エピ基板の製造方法及び半導体装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2759594B2 (ja) * 1993-01-30 1998-05-28 信越半導体株式会社 エピタキシャル基板の製造方法
JP4470231B2 (ja) * 1999-03-31 2010-06-02 株式会社Ｓｕｍｃｏ 半導体シリコンウェーハの製造方法
DE19956250C1 (de) * 1999-11-23 2001-05-17 Wacker Siltronic Halbleitermat Kostengünstiges Verfahren zur Herstellung einer Vielzahl von Halbleiterscheiben
JP4182323B2 (ja) * 2002-02-27 2008-11-19 ソニー株式会社 複合基板、基板製造方法
JP4248804B2 (ja) * 2002-05-08 2009-04-02 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 半導体ウェーハおよび半導体ウェーハの製造方法
JP4042618B2 (ja) * 2003-04-25 2008-02-06 株式会社Ｓｕｍｃｏ エピタキシャルウエーハ製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9340900B2 (en) 2006-09-06 2016-05-17 Sumco Corporation Epitaxial wafer and method of producing same

Also Published As

Publication number Publication date
CN101091237A (zh) 2007-12-19
WO2006070556A1 (ja) 2006-07-06
JP2006190703A (ja) 2006-07-20
CN100541727C (zh) 2009-09-16
KR20070094904A (ko) 2007-09-27

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