TW200619956A - Data buffer circuit, interface circuit and control method therefor - Google Patents

Data buffer circuit, interface circuit and control method therefor

Info

Publication number
TW200619956A
TW200619956A TW094110246A TW94110246A TW200619956A TW 200619956 A TW200619956 A TW 200619956A TW 094110246 A TW094110246 A TW 094110246A TW 94110246 A TW94110246 A TW 94110246A TW 200619956 A TW200619956 A TW 200619956A
Authority
TW
Taiwan
Prior art keywords
circuit
control method
method therefor
port ram
address
Prior art date
Application number
TW094110246A
Other languages
English (en)
Other versions
TWI313818B (en
Inventor
Kazuya Taniguchi
Toshiyuki Nishii
Hiromichi Mizuno
Tsutomu Terazawa
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of TW200619956A publication Critical patent/TW200619956A/zh
Application granted granted Critical
Publication of TWI313818B publication Critical patent/TWI313818B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
  • Image Input (AREA)
TW094110246A 2004-12-09 2005-03-31 Data buffer circuit, interface circuit and control method therefor TWI313818B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004357165A JP4502792B2 (ja) 2004-12-09 2004-12-09 データバッファ回路

Publications (2)

Publication Number Publication Date
TW200619956A true TW200619956A (en) 2006-06-16
TWI313818B TWI313818B (en) 2009-08-21

Family

ID=36585380

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094110246A TWI313818B (en) 2004-12-09 2005-03-31 Data buffer circuit, interface circuit and control method therefor

Country Status (4)

Country Link
US (1) US7454589B2 (zh)
JP (1) JP4502792B2 (zh)
KR (1) KR100631778B1 (zh)
TW (1) TWI313818B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112860174A (zh) * 2019-11-27 2021-05-28 瑞昱半导体股份有限公司 数据写入系统与方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5354427B2 (ja) 2006-06-28 2013-11-27 アクロニクス セミコンダクター コーポレイション 集積回路のための再構成可能論理ファブリックおよび再構成可能論理ファブリックを構成するためのシステムおよび方法
US7900078B1 (en) * 2009-09-14 2011-03-01 Achronix Semiconductor Corporation Asynchronous conversion circuitry apparatus, systems, and methods
CN103026349B (zh) * 2010-07-16 2016-04-06 拉迈亚高级研究院 数据接口电路
KR102251241B1 (ko) * 2013-11-29 2021-05-12 삼성전자주식회사 재구성 가능 프로세서의 레지스터를 제어하는 방법 및 장치와 재구성 가능 프로세서의 레지스터를 제어하는 명령어를 생성하는 방법 및 장치
US10505704B1 (en) * 2015-08-02 2019-12-10 Wave Computing, Inc. Data uploading to asynchronous circuitry using circular buffer control
CN109857342B (zh) * 2019-01-16 2021-07-13 盛科网络（苏州）有限公司 一种数据读写方法及装置、交换芯片及存储介质
CN114489233A (zh) * 2022-01-24 2022-05-13 上海华力集成电路制造有限公司 一种相位可调任意波形发生器

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02155061A (ja) * 1988-12-07 1990-06-14 Toshiba Corp データ通信方式
JPH02196364A (ja) * 1989-01-26 1990-08-02 Nec Corp 数値制御装置の外部データ記憶装置接続方式
JPH0573510A (ja) 1991-09-11 1993-03-26 Fujitsu Ltd レジスタフアイルのリードライト方式
JPH05224920A (ja) 1992-02-14 1993-09-03 Hitachi Ltd データ処理装置
CN1125491A (zh) 1993-04-16 1996-06-26 数据翻译公司 计算机的视频外围设备
JP3490131B2 (ja) * 1994-01-21 2004-01-26 株式会社ルネサステクノロジ データ転送制御方法、データプロセッサ及びデータ処理システム
JPH09305562A (ja) * 1996-05-14 1997-11-28 Murata Mach Ltd データ転送装置
JPH11133936A (ja) 1997-10-31 1999-05-21 Mitsubishi Electric Corp 画像合成装置
JP2000228083A (ja) 1999-02-05 2000-08-15 Matsushita Electric Ind Co Ltd データ出力バッファ
JP2000305895A (ja) 1999-04-22 2000-11-02 Matsushita Electric Ind Co Ltd 非同期インターフェース
JP4119582B2 (ja) 1999-09-28 2008-07-16 富士通株式会社 転送制御方法及び情報処理装置
CA2329287A1 (en) 2000-01-21 2001-07-21 Symagery Microsystems Inc. Host interface for imaging arrays
JP3815948B2 (ja) * 2000-04-20 2006-08-30 シャープ株式会社 Ｆｉｆｏメモリ制御回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112860174A (zh) * 2019-11-27 2021-05-28 瑞昱半导体股份有限公司 数据写入系统与方法

Also Published As

Publication number Publication date
TWI313818B (en) 2009-08-21
US7454589B2 (en) 2008-11-18
JP2006164070A (ja) 2006-06-22
JP4502792B2 (ja) 2010-07-14
US20060129720A1 (en) 2006-06-15
KR100631778B1 (ko) 2006-10-11
KR20060065462A (ko) 2006-06-14

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees