DE60216803D1 - Fifo als übergang von taktregionen - Google Patents

Fifo als übergang von taktregionen

Info

Publication number
DE60216803D1
DE60216803D1 DE60216803T DE60216803T DE60216803D1 DE 60216803 D1 DE60216803 D1 DE 60216803D1 DE 60216803 T DE60216803 T DE 60216803T DE 60216803 T DE60216803 T DE 60216803T DE 60216803 D1 DE60216803 D1 DE 60216803D1
Authority
DE
Germany
Prior art keywords
clock
data
processing circuit
domain
clock domain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60216803T
Other languages
English (en)
Other versions
DE60216803T2 (de
Inventor
A Pontius
L Payne
R Evoy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of DE60216803D1 publication Critical patent/DE60216803D1/de
Application granted granted Critical
Publication of DE60216803T2 publication Critical patent/DE60216803T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/005—Correction by an elastic buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
    • G06F2205/102—Avoiding metastability, i.e. preventing hazards, e.g. by using Gray code counters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Static Random-Access Memory (AREA)
  • Information Transfer Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Communication Control (AREA)
DE60216803T 2001-10-31 2002-10-02 Fifo als übergang von taktregionen Expired - Lifetime DE60216803T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US999007 1992-12-31
US09/999,007 US7187741B2 (en) 2001-10-31 2001-10-31 Clock domain crossing FIFO
PCT/IB2002/004076 WO2003039061A2 (en) 2001-10-31 2002-10-02 Clock domain crossing fifo

Publications (2)

Publication Number Publication Date
DE60216803D1 true DE60216803D1 (de) 2007-01-25
DE60216803T2 DE60216803T2 (de) 2007-11-15

Family

ID=25545764

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60216803T Expired - Lifetime DE60216803T2 (de) 2001-10-31 2002-10-02 Fifo als übergang von taktregionen

Country Status (6)

Country Link
US (1) US7187741B2 (de)
EP (1) EP1442550B1 (de)
JP (1) JP4042856B2 (de)
AT (1) ATE348455T1 (de)
DE (1) DE60216803T2 (de)
WO (1) WO2003039061A2 (de)

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US7269754B2 (en) * 2002-12-30 2007-09-11 Intel Corporation Method and apparatus for flexible and programmable clock crossing control with dynamic compensation
US7366935B1 (en) 2003-04-01 2008-04-29 Extreme Networks, Inc. High speed bus with alignment, re-timing and buffer underflow/overflow detection enhancements
US7272672B1 (en) 2003-04-01 2007-09-18 Extreme Networks, Inc. High speed bus with flow control and extended burst enhancements between sender and receiver wherein counter is maintained at sender for free buffer space available
KR100522433B1 (ko) 2003-04-29 2005-10-20 주식회사 하이닉스반도체 도메인 크로싱 회로
US7698588B2 (en) * 2003-05-15 2010-04-13 International Business Machines Corporation Circuit and related method for synchronizing data signals to a core clock
CN100588149C (zh) * 2003-06-25 2010-02-03 Nxp股份有限公司 将目标时钟域中发生的目标事件传递到监控时钟域的电路
US7248661B1 (en) 2003-08-26 2007-07-24 Analog Devices, Inc. Data transfer between phase independent clock domains
TWI267871B (en) 2004-01-10 2006-12-01 Hynix Semiconductor Inc Domain crossing device
US7376855B1 (en) * 2004-05-20 2008-05-20 Sun Microsystems, Inc. Fully stable clock domain synchronization technique for input/output data transmission
JP4291225B2 (ja) * 2004-06-30 2009-07-08 富士通株式会社 パラレルデータを受信する装置および方法
US7084680B2 (en) * 2004-08-31 2006-08-01 Micron Technology, Inc. Method and apparatus for timing domain crossing
US7380229B2 (en) * 2005-06-13 2008-05-27 Lsi Corporation Automatic generation of correct minimal clocking constraints for a semiconductor product
KR100670654B1 (ko) * 2005-06-30 2007-01-17 주식회사 하이닉스반도체 도메인 크로싱 마진을 증가시키기 위한 반도체메모리소자
ATE496469T1 (de) 2005-11-04 2011-02-15 Nxp Bv Ausrichtung und entzerrung für mehrfache spuren einer seriellen verbindung
US8015382B1 (en) * 2007-02-28 2011-09-06 Altera Corporation Method and apparatus for strobe-based source-synchronous capture using a first-in-first-out unit
US8775701B1 (en) 2007-02-28 2014-07-08 Altera Corporation Method and apparatus for source-synchronous capture using a first-in-first-out unit
US7594047B2 (en) * 2007-07-09 2009-09-22 Hewlett-Packard Development Company, L.P. Buffer circuit
US8584067B2 (en) * 2010-11-02 2013-11-12 Advanced Micro Devices, Inc. Clock domain crossing buffer
US8949448B1 (en) 2011-01-27 2015-02-03 Integrated Device Technology, Inc. System and method for improving the timestamp precision in a precision time protocol (PTP) device
TWI462493B (zh) * 2011-02-17 2014-11-21 Realtek Semiconductor Corp 跨時脈域之干擾消除裝置及方法
TWI437411B (zh) * 2011-03-14 2014-05-11 Realtek Semiconductor Corp 用於時脈樹轉換處的先入先出（ｆｉｆｏ）裝置與方法
US8918666B2 (en) * 2011-05-23 2014-12-23 Intel Mobile Communications GmbH Apparatus for synchronizing a data handover between a first and second clock domain through FIFO buffering
US8826062B2 (en) 2011-05-23 2014-09-02 Intel Mobile Communications GmbH Apparatus for synchronizing a data handover between a first clock domain and a second clock domain through phase synchronization
US8898502B2 (en) * 2011-07-05 2014-11-25 Psion Inc. Clock domain crossing interface
CN102880441B (zh) * 2011-07-12 2015-06-10 瑞昱半导体股份有限公司 先入先出装置及其实现方法
US8904221B2 (en) * 2011-12-22 2014-12-02 Lsi Corporation Arbitration circuitry for asynchronous memory accesses
US9330740B1 (en) 2013-12-18 2016-05-03 Altera Corporation First-in first-out circuits and methods
US11128742B2 (en) 2019-03-08 2021-09-21 Microsemi Storage Solutions, Inc. Method for adapting a constant bit rate client signal into the path layer of a telecom signal
US10972084B1 (en) 2019-12-12 2021-04-06 Microchip Technology Inc. Circuit and methods for transferring a phase value between circuits clocked by non-synchronous clock signals
US11323123B2 (en) 2019-12-20 2022-05-03 Microchip Technology Inc. Circuit to correct phase interpolator rollover integral non-linearity errors
US10917097B1 (en) 2019-12-24 2021-02-09 Microsemi Semiconductor Ulc Circuits and methods for transferring two differentially encoded client clock domains over a third carrier clock domain between integrated circuits
US11239933B2 (en) 2020-01-28 2022-02-01 Microsemi Semiconductor Ulc Systems and methods for transporting constant bit rate client signals over a packet transport network
US11424902B2 (en) 2020-07-22 2022-08-23 Microchip Technology Inc. System and method for synchronizing nodes in a network device
CN112965689B (zh) * 2021-02-26 2023-05-09 西安微电子技术研究所 一种基于源同步的分布式异步fifo数据交互方法及fifo结构
US11838111B2 (en) 2021-06-30 2023-12-05 Microchip Technology Inc. System and method for performing rate adaptation of constant bit rate (CBR) client data with a variable number of idle blocks for transmission over a metro transport network (MTN)
US11916662B2 (en) 2021-06-30 2024-02-27 Microchip Technology Inc. System and method for performing rate adaptation of constant bit rate (CBR) client data with a fixed number of idle blocks for transmission over a metro transport network (MTN)
US11736065B2 (en) 2021-10-07 2023-08-22 Microchip Technology Inc. Method and apparatus for conveying clock-related information from a timing device
US11799626B2 (en) 2021-11-23 2023-10-24 Microchip Technology Inc. Method and apparatus for carrying constant bit rate (CBR) client signals

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4873703A (en) * 1985-09-27 1989-10-10 Hewlett-Packard Company Synchronizing system
US5452434A (en) * 1992-07-14 1995-09-19 Advanced Micro Devices, Inc. Clock control for power savings in high performance central processing units
US6209053B1 (en) * 1998-08-28 2001-03-27 Intel Corporation Method and apparatus for operating an adaptive multiplexed address and data bus within a computer system
US6370600B1 (en) * 1999-05-25 2002-04-09 Advanced Micro Devices, Inc. Staging buffer for translating clock domains when source clock frequency exceeds target clock frequency

Also Published As

Publication number Publication date
US20030081713A1 (en) 2003-05-01
WO2003039061A2 (en) 2003-05-08
JP2005507608A (ja) 2005-03-17
ATE348455T1 (de) 2007-01-15
EP1442550B1 (de) 2006-12-13
WO2003039061A3 (en) 2003-10-23
JP4042856B2 (ja) 2008-02-06
EP1442550A2 (de) 2004-08-04
US7187741B2 (en) 2007-03-06
DE60216803T2 (de) 2007-11-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL

8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN