TW200529374A - CMOS structure and related method - Google Patents

CMOS structure and related method Download PDF

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TW200529374A
TW200529374A TW093124575A TW93124575A TW200529374A TW 200529374 A TW200529374 A TW 200529374A TW 093124575 A TW093124575 A TW 093124575A TW 93124575 A TW93124575 A TW 93124575A TW 200529374 A TW200529374 A TW 200529374A
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TWI251902B (en
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Kuan-Lun Cheng
Huan-Tsung Huang
Shui-Ming Cheng
ying-pin Wang
Kahing Fung
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Taiwan Semiconductor Mfg
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    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
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    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
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    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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Description

200529374 玖、發明說明 【發明所屬之技術領域】 本發明是有關於一種含有氮化矽層之CMOS結構， 且更一般地關於一種製造此一結構及其所含的氮化石夕層 之方法。更特別地，本發明關於一種含有p-MOS(或p-FET) 及n-MOS(或n-FET)區之CMOS結構，於其上方形成一受 應力的接觸蝕刻終止層，其中於層中之應力被限制於載流 子遷移率和驅動電流依此增強之區域中，且於載流子遷移 率和驅動電流依此降低之區域中被避免或消除。 【先前技術】 已知CMOS或M0SFET裝置之閘極下方通道區域中 之機械應力控制對於縮小元件而言是具決定性的。機械應 力一拉伸及壓縮—可提高電子及電洞於通道中之遷移 率。一般而言，拉伸應力改良電子遷移及降低電洞遷移， 且壓縮應力降低電子遷移及改良電洞遷移。請參照由
ShimizU 等人所著，於 2001 IEDM technical Digest，第 433 頁以下（Shimizu )’，，L〇cal Mechanical Stress Control (LMC): A New Technology f〇r CMOS Performance
Enhancement (局部機械應力控制（LMC) : CMOS效能增強 之新技術）”。 一種於通道中產生應力之方法為在應變矽上製造 MOSFET。此可藉蟲晶成長石夕於緩和的層上而達成。 口月蒼知由 Yee-Chia Yeo 等人所著，於 2〇〇〇 iedm technical 200529374
Digest，第 753 頁以下（“Ye〇”），，，Enhanced Performance in
Sub-1 OOnm CMOSFETs Using Strained Epitaxial
Silicon-Germanium (於次 loo 奈米 CMOSFETs 中使用應變 蠢晶矽-鍺之增強效能），，。依此方式施應力於矽稍微複 雜。再者，已發現就n-FET區（為了增強電子遷移）而言不 易製造拉伸應力矽，且就p-FET區而言不易製造壓縮應 力矽，其中二者係如上述存在於單一結構中。 亦已發現通道應力係由淺溝絕緣所產生。請參照例如 由 Ootsuka 等人所著，於 2000 IEDm technical Digest，第 575 頁以下（“Ootsuka”），，，A Highly Dense，High Performance 13〇nm Node CMOS Technology for Large Scale System-On_Chip Application (用於大尺寸系統晶片 應用之高密度、高效能13〇奈米Node CMOS技術），，，係 引用由 Scott 等人所著，於 1999 IEDM technical Digest， 苐 827 頁以下 ’ ”NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress (由電晶體佈局及溝渠絕緣引起之應力所造成的NMOS驅 動電流減少）’。請亦參照由]yjin-Hwa Chi及Wai-Yi Lien 於2003年11月21日申請之共同讓渡的美國專利申請案 序就 10/718,928’ 標題為”Modification of Carrier Mobility in a Semiconductor Device (於半導體裝置中之載體遷移 之修飾）”。 最近的研究已顯示，當氮化矽（通稱” SiN”）之接觸蝕 刻終止層存在時，亦產生機械應力。請參照Shimizu、 200529374
Ootsuka 以及由 lt0 等人所著，於 2〇〇〇 IEDM technical
Digest，第 247 頁以下（“It〇，，），，，Mechanicai 以代“以以以 〇f
Etch-Stop Nitride and its Impact on Submicro Transistor
Design (蝕刻終止氮化物之機械應力效應及其對於次微米 電晶體設計之影響）’，。 >儿積的氮化矽或SiN接觸姓刻終止層可具有固有的 拉伸應力或壓縮應力。舉例來說，經由熱化學蒸氣沉積 (“TCVD”）而形成於矽上之SiN層具有拉伸應力，而經由 電漿增強化學蒸氣沉積（“PECVD”）而形成於矽上之siN層 係受壓縮應力（請參照Ootsuka)。
Ootsuka揭示藉由佈植鍺離子於其中而緩和siN蝕刻 終止層中之應力。鍺離子於PECVD SiN層中之佈植緩和 了其中之壓縮應力。鍺離子於TCVD SiN層中之佈植緩和 了其中之拉伸應力。 【發明内容】 本發明之較佳實施力包含一種應力緩和的氮化矽或 SiN層之CMOS結構，其中應力係受到含氧或含碳離子佈 植於其中而緩和。應力可於SiN層之選擇區中藉由阻止離 子佈植於除該選擇區外之全部（例如藉由適當的遮蔽作用） 而緩和，其中鍺離子佈植會破壞鍵結，而含氧或含碳離子 佈植可改變化學組成成分。當SiN層係經由TCVD形成 時’應力可為拉伸的，或當SiN層係經由pECVD形成時， 應力可為壓縮的。一般而言，PMOS及NMOS裝置將形成 200529374
於基板中或基板上，之後，此等元件及基板將覆蓋SiN 層。倘若SiN層中之應力是拉伸的，則氧或碳離子之佈植 係於NMOS裝置上方之層區中受到阻止。倘若siN層中 之應力是壓縮的，則佈植係於PM〇s裝置上方之層區中 受到阻止。 本發明之其他實施例包含製造上述實體例結 法。藉遮蔽該層，例如藉施用及顯影一光阻塗層於siN 層，可於SiN層之選擇區中阻止離子佈植。 【實施方式】 先财之較佳實施例將更詳細地討論如下。然而，應可 理解，本發明提供許多可於廣泛類型特殊範圍中具體實施 的發明概念。所討論之特殊實施例僅為製造及使用本發明 之特f方法之料，並^會_本發明之範圍。 第1圖顯示-先前技藝CM〇s結構1〇，其包含一或 夕個電晶體或其他裝置（通當俨 擴充積體電路或‘二：？1)。結構10,通常為 MM M i ,，係包含—基板12。 =展置u為CM0S/M0SFET電晶體，則每—者 極16間。^及極16。閑極18係位於源極η與沒 貝20，例如使閘極電極22盥 电 16與其延伸部分之 ”古、（位於源極14/汲極 汲極16形成期門⑼石曰、、、巴、、之鬲K電介質。於源極14/ ㈣㈣晶形成及/或離子佈峨蔽閑極18 200529374 側之絕緣間隔侔％ _ ^ t 、n 件26，通常於此形成後保留於適當位置。 泪 刀（）區28(包含填充形成於基板12卡之溝 =32之絕緣㈣3〇)係與相連㈣晶體或其 件11彼此電絕緣。 衣置次兀 34 ^ :本毛月之目的，左側裝置11為PM〇S電晶體 ’且右側裝置11為NM〇s電晶體36。 接觸钱刻終止層50係形成於基板12、源極Μ〆汲極 閘極18及siTs 28上方。於較後時間點，個別的開 孔（未顯不）係形成於層5〇令，且填充與相關源極、汲 極16及閘極電極22電連續之金屬或其他導電材料（未顯 不)/於開孔中之金屬$其他導電材料適用&使其他元件 及裝置（未顯示）電連接於源極14/汲極16/閘極電極22之 電接點。此等元件及裝置可存在於具有結構1〇之較高階 1C 〇 如早先所注意，倘若基板12為矽且層50為藉熱化學 蒸氣沉積（“CVD”）而形成之氮化石夕，則於I 5G中將有殘 餘的拉伸應力（亦將於通道24中產生拉伸應力）。於通道 24中之拉伸應力提高其中之電子遷移率（如同於nm〇s電 晶體36之通道24中），但降低其中之電洞遷移率（如同於 PMOS電晶體34之通道24中）。 因此，倘若裝置34為所描述之pM〇；§電晶體且裝置 36為所描述之NMOS電晶體，則藉熱CVD而形成之SiN 層50將增進裝置36之操作，但將降低裝置34之操作。 倘若層50係藉電漿增強化學蒸氣沉積（“pECVD，，）而形 10 200529374 成，則層50及通道24受到壓縮應力，因而造成裝置 中之電洞遷移率增加，但造成裝置36中之電子遷移率降 低。 於第1圖中，先前技藝結構1 〇受到本發明之方法， 以製得本發明之產物（後者係顯示於第2圖中）。 特別地，倘若SiN層50具有拉伸應力，則NM〇s裝 置36上方之層50區域受到適當地施用及顯影的光阻塗層 6〇或其他不透氧及/或碳離子佈植之材料而遮蔽。光阻 未遮蔽PMOS裝置34上方之層50區域。之後，如箭號 7〇之示意顯示，進行氧或碳離子佈植。光阻6〇阻止離子 達到覆蓋於NMOS裝置36上方之層50區域。 佈植於覆蓋於PMOS裝置34上方之層50區域之氧 或碳離子緩和了其中的拉伸應力。此拉伸應力之緩和，造 成PMOS裝置34之通道中少許或無電洞遷移率降低之拉 伸應力。第2圖係藉由顯示改良的結構1〇〇闡明，其中 ▲置34上方之層5〇之未施應力區被遮蔽，而 凌置36上方之層5〇區域未被遮蔽，亦即，其保留其拉伸 應力以增進其通道24中之電子遷移率。 倘若SiN層50經施加壓縮應力，則當藉由pecvd 而形成時，則施用及顯影光阻60，以遮蔽PMOS裝置34， 及谷許氧或碳離子佈植於NMOS裝置36上方之SiN層50 區域。 就一實施例而言，可採用之蝕刻終止層50係藉CVD 而形成至厚度為介於100埃至1000埃間，較佳至厚度為 200529374 約150-300埃。為了緩和裝置34上方之層中的拉伸應力， 則將氧佈植至濃度範圍為2\1〇14至5χ1〇16原子/平方公 分，更佳為至約lxl0i5S 6χ1〇β原子/平方公分。氧較佳 佈植至深度為蝕刻終止層厚度之約5〇-8〇0/〇。 可使用本發明之方法取代或結合其他應力產生技 術，以便定做及調整CM〇s裝置34、36之通道24中之 應力類型及數量。再者，明顯地，可使用本發明以選擇性 地影響含於積體電路中之複合CM〇s裝置34、36之應力。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限疋本發明，任何熟習此技藝者，在不脫離本發明之精 神和耗圍内，當可作各種之更動與潤飾，因此本發明之保 濩乾圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一起q土每 牛 孕乂佺κ軛例，並配合所附圖式，作詳 細說明如下： -第1圖,兒明種藉由根據本發明方法所修飾之先前 技藝產品的斷面側視圖。 第2圖說明一種因實施第i圖中示意表示之方法而根 據本發明所修飾之第1 «產品的斷面側視圖。 12 200529374 元件代表符號簡單說明】 10 :先前技藝CMOS結構 12 :基板 16 :汲極 20 :電介質 24 :通道 28 :淺溝渠絕緣區 36 : NMOS電晶體 60 :光阻塗層 100 :改良的結構 11 :電晶體或其他裝置 14 :源極 1 8 :閘極 22 :閘極電極 26 :絕緣間隔件 34 : PMOS電晶體 5 0 :接觸钱刻終止層 7 0 :氧或碳離子佈植
13

Claims (1)

  1. 200529374 拾、申請專利範圍 L 一種具有氮化矽層之CMOS結構，其中應力係受 到含氧或含碳離子佈植於其中而緩和。 2·如申請專利範圍第1項所述之結構，其中應力係 於一選擇區中藉由阻止離子佈植於除該選擇區外之全部 而緩和。 3 ·如申請專利範圍第2項所述之結構，其中該阻止 步驟係經由遮蔽除該選擇區外之全部而進行。 4·如申請專利範圍第丨項所述之結構，其中於該層 中之該應力為拉伸的。 5·如申請專利範圍第4項所述之結構，進一步包含 PMOS I置及一 NMQS裝置，二者皆受該層覆蓋，且 其中含氧或含碳離子之佈植係於該NMOS裝置上方之層 區中受到阻止。 6·如申請專利範圍第丨項所述之結構，其中於該層 中之該應力為壓縮的。 7 ·如申凊專利範圍第6項所述之結構，進一步包含 14 200529374 —PMOS P w u 、 芸 ^ 一 NM〇s裝置，二者皆受該氮化矽層覆 八中3氧或含碳離子之佈植係於該pM〇s裝置上 方之層區中受到阻止。 牙CM〇S結構，其係於-或多個NMOS裝置及 一或多個PMOS步罟μ七曰 > 斤 其包含· ^置上方具有氮化矽接觸蝕刻終止層， 卜第一層區，係位於一類型裝置上方，且且 氮離子佈植其中；以及 ”有3乳或各 第二層區，係位於另一 或含氮離子佈植其中。社衣置上方’且不具有含氧 該層係 10.如申請專利範圍第8 藉熱化學蒸氣沉積作用而形成。-構’其中顯 :如申請專利範圍第10項所述之結構，立中： 該第-區係位於該PM0S裝置上方；以及 该第二區係位於該NM0S裝置上方。 精電叛增強化學蒸氣沉積作用而形成 1 2 ·如申請專利範圍第δ 項所述之結構，其中該層係 15 200529374 .如申請專利範圍第12項所述之結構，其中 第一區係位於該NMOS裝置上方；以 該第二區係位於該PMOS裝置上方。 14· 一種緩和CMOS結構之新脊功麻山士 僻心虱化矽層中應力之方 法’其包含佈植含氧或含碳離子於該層中。 15.如申請專利範圍第14項所述之方法進一步包 含阻止含氧或含碳離子佈植於除該層之選擇區外之全部 中 〇 Μ·/如申請專利範圍第15項所述之方法，其中該阻 止步驟係經㈣蔽除該選#區外之全部而進行。 1 7·如申凊專利範圍第丨4項所述之方法，其中於該 層中之該應力為拉伸的。 。 18.如申請專利範圍第17項所述之方法，置中該層 係覆蓋於- m0Sm_ NM〇s裝置上方，且進;^ 包含阻止含氧或含碳離子佈植於該NMOS裝置上方之声 區中。 € 19·如申睛專利範圍第18項所述之方法，其中該阻 16 200529374 止步驟係經由遮蔽除該PMOS上方層區外之全部而進行。 20·如申請專利範圍第19項所述之方法，其中該遮 蔽步驟係選擇性地施用及顯影一光阻塗層於該層上而進 行。 21.如申請專利範圍第14項所述之方法，其中於該 層中之該應力為壓縮的。 22·如申請專利範圍第2 1項所述之方法，其中該層 係覆蓋於一 PMOS裝置及一 NMOS裝置上方，且進一步 包含阻止含氧或含碳離子佈植於該PM〇s裝置上方之層 區中。 23. 如申請專利範圍第22項所述之方法，其中該阻 止步驟係經由遮蔽除該NM〇s上方層區外之全部而進行。 24. 如中請專利範圍第23項所述之方法，其中該遮 蔽步驟係選擇性地施用及顯影一光阻塗層於該層上而進 行0 25· i緩和一或多個Ν_裝置及—或多個膚s 、置^方氮切接㈣刻終止層中應力之方法，其包含： 4擇性地佈植3氧或含氮離子於—類型裝置上方之 17 200529374 層區中；以及 同時阻止佈植離子於另一類型裝置上方之層區中。 26.如申請專利範圍第25項所述之方法，盆 止步驟係經由遮蔽除該另一類型裝置上方之層區而進行 27·如申請專利範圍第26項所述之方法，其中哼 蔽步驟係選擇性地施用及顯影一光阻塗層&該層上:進 行。 進 28.如申請專利範圍第25項所述之方法，其中該層 係藉化學蒸氣沉積作用而形成。 曰 …29. #申請專利範圍第25項所述之方法，其中該層 係藉熱化學蒸氣沉積作用而形成。 曰 30·如申請專利範圍第29 影之光阻塗層遮蔽該NMOS裝 項所述之方法，其中經顯 置 μ.如申請專利範圍第2 係藉電锻增強化學蒸氣沉積作用而形成。 中 影之光阻月專利乾圍第31項所述之方法，其中經顯 之光阻塗層遮蔽該PMOS裝置。 18
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