CN101796641B - 场效应晶体管中的沟道应变设计 - Google Patents

场效应晶体管中的沟道应变设计 Download PDF

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CN101796641B
CN101796641B CN2008800160183A CN200880016018A CN101796641B CN 101796641 B CN101796641 B CN 101796641B CN 2008800160183 A CN2008800160183 A CN 2008800160183A CN 200880016018 A CN200880016018 A CN 200880016018A CN 101796641 B CN101796641 B CN 101796641B
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grid
fet
stressed liner
opening
drain region
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CN101796641A (zh
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T·迪勒
R·克里希纳萨米
J-P·韩
E·德姆
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I C Com Ltd
International Business Machines Corp
Morphics Technology Inc
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Abstract

公开了一种向场效应晶体管的栅极之下的沟道区域施加应力的方法，所述场效应晶体管包括所述栅极、源极区域与漏极区域。所述方法包括以下步骤：在所述FET的所述源极与漏极区域中嵌入应力源；形成应力衬里以覆盖所述栅极以及所述源极和漏极区域；去除所述应力衬里的一部份，所述应力衬里的所述部分位于所述栅极的顶部上；去除第一栅极材料的所述栅极的至少实质的部分，由此在其中产生开口；以及用第二栅极材料填充所述开口。

Description

场效应晶体管中的沟道应变设计
相关申请的交叉引用
本申请要求在2007年6月8日提交的名称为“CHANNEL STRAINENGINEERING IN FIELE-EFFECT-TRANSISTOR”的美国专利申请11/760056的优先权，在此引入其全部内容作为参考。
技术领域
本发明涉及半导体器件制造领域。具体地，本发明涉及通过栅极替换(replacement)和/或选择性使用栅极材料而进行的对场效应晶体管中的沟道应变的设计。
背景技术
在半导体器件制造领域中，例如，诸如晶体管的有源半导体器件通常由前段制程(front end of line；FEOL)技术制造或产生。例如，晶体管包括诸如互补金属氧化物半导体(CMOS)FET的场效应晶体管(FET)。FET晶体管可为p型掺杂FET(PFET)或n型掺杂FET(NFET)。可以在半导体芯片的公共衬底或公共半导体结构上形成或制造不同类型的FET晶体管。
为了通过提高FET沟道中的载流子迁移率来改善诸如操作速度的器件性能，在形成FET的栅极结构之后，通常可通过例如施加应力衬里将应力导入FET的沟道区域中。由于载流子类型不同，通常对PFET晶体管施加压缩应力衬里，而对NFET晶体管施加拉伸应力衬里，两种应力衬里都可以通过传统的双应力衬里(DSL)工艺、或近来的自对准双应力衬里工艺(SADSL)形成。用于设计FET沟道中的应变的其它技术包括：例如，在PFET晶体管的源极/漏极区域中嵌入硅锗(SiGe)，以更有效地向PFET晶体管的沟道施加应力。
基于对高性能半导体器件的持续需求，需要进一步改善在场效应晶体管的沟道区域中的应变设计。这包括，例如，改善应力衬里的有效性，以及在某些情况下甚至不具有这样的应力衬里。
发明内容
本发明的实施例提供一种向场效应晶体管的栅极之下的沟道区域施加应力的方法，所述场效应晶体管包括所述栅极、源极区域以及漏极区域。所述方法包括：在所述源极和漏极区域中嵌入应力源(stressor)；形成应力衬里以覆盖所述栅极以及所述源极和漏极区域；去除所述应力衬里的一部份，所述应力衬里的所述部分位于所述栅极的顶部上；去除第一栅极材料的所述栅极的至少实质的部分(substantial portion)，由此在其中产生开口；以及用第二栅极材料填充所述开口。
本发明的实施例还提供一种在用所述第二栅极材料填充所述开口之后去除覆盖所述源极与漏极区域的所述应力衬里的方法；以及一种在去除覆盖所述源极与漏极区域的所述应力衬里之后形成覆盖所述第二栅极材料的所述栅极以及所述FET的所述源极与漏极区域的新应力衬里的方法。
根据一个实施例，所述第一栅极材料所具有的杨氏模数值小于130GPa，优选小于115GPa，且最优选小于100GPa。所述第一栅极材料选自Si0.8Ge0.2、Si0.5Ge0.5、Ge、GaP、GaAs、Al0.5Ga0.5As、AlAs、InP、InAs、ZnO、ZnS、ZnSe、CdS与CdTe。根据另一实施例，所述第二栅极材料所具有的杨氏模数值等于或大于130GPa。
本发明的实施例提供了一种向场效应晶体管的栅极之下的沟道区域施加应力的方法，所述场效应晶体管包括所述栅极、源极区域以及漏极区域。所述方法包括：使用栅极材料形成所述FET的所述栅极，所述栅极材料具有的杨氏模数值小于130GPa，优选小于115GPa，更优选小于100GPa；以及形成覆盖所述FET的所述栅极和所述源极与漏极区域的应力衬里。
本发明的实施例提供了一种向场效应晶体管的栅极之下的沟道区域施加应力的方法。所述方法包括：在所述FET的源极和漏极区域中嵌入应力源；形成应力衬里以覆盖所述FET的栅极以及所述源极与漏极区域；去除所述应力衬里的位于所述栅极的顶部上的一部份；去除第一栅极材料的所述栅极和其下的第一栅极氧化物层，由此在其中产生开口；用第二栅极氧化物层填充所述开口；以及在所述第二栅极氧化物层上填充第二栅极材料。
附图说明
通过结合附图进行的对本发明的以下详细说明，将更完全了解和理解本发明，其中：
图1-8为根据本发明的实施例的利用栅极替换形成场效应晶体管的方法的示意性示例；以及
图9-13为根据本发明的实施例的形成场效应晶体管的方法的可替换的步骤的示意性示例。
应该理解，为了说明的简单和清楚，附图中的部件不必按比例绘制。例如，为了清楚，相对于其它部件放大了某些部件的尺寸。
具体实施方式
在以下详细说明中阐述了多种特定细节，以提供对本发明的实施例的全面了解。然而，本领域的技术人员应了解，可实施本发明的实施例而没有这些特定的细节。为了不使本发明的本质和/或实施例的表示模糊，在以下详细说明中，为了表示和/或示例的目的，本领域中公知的处理步骤和/或操作被组合在一起，并且在某些情况下甚至没有对其进行详细描述。在其它情况下，本领域中公知的处理步骤和/或操作完全未加以说明。本领域的技术人员将理解下列描述更关注本发明的实施例的区别特征和/或部件。
在半导体制造业中，各种类型的有源半导体器件(例如晶体管，包括n型(NFET)和p型(PFET)的CMOS FET)为可通过应用公知的FEOL处理技术而产生或形成于单一的半导体衬底上。公知的FEOL技术包括的处理步骤和/或操作有：例如，盖层沉积、光致抗蚀剂掩模形成、光刻、硬掩模形成、湿法蚀刻、反应离子蚀刻(RIE)、离子注入以及化学机械抛光(CMP)等等。在晶体管形成期间和/或形成后，可对晶体管(即NFET和PFET)施加相同或不同的应力衬里，以改善器件的性能。器件性能的改善可源于由应力衬里诱导的应变所引起的NFET的沟道区域中电子的改善迁移率和/或PFET的沟道区域中空穴的改善的迁移率。
在以下详细说明中将不详细说明公知的器件处理技术和/或步骤，且在某些实例中，可以参照其它公开文献或专利申请，以避免使以下将更详细说明的本发明的本质的描述模糊。
图1-8为根据本发明的实施例的利用栅极替换形成场效应晶体管的方法的示意性示例。例如，图1示例出在半导体衬底101上形成场效应晶体管(FET)100的步骤。FET 100可以通过嵌入在衬底101中的浅沟槽隔离(STI)例如STI 102而与其它FET或半导体器件电隔离。FET 100的形成可包括：在衬底101的顶面上形成或沉积介电层103(例如，氧化物)；构图在介电层103的顶部上的栅极导体201(例如，多晶硅)；以及在与栅极导体201相邻的源极和漏极区域中嵌入应力源104(例如，硅锗(SiGe)或硅碳(SiC))。
虽然未在图1中具体示例，但根据本发明的某些实施例，FET 100的形成还包括了其它公知的步骤，例如，在栅极导体201的两侧形成隔离物(spacer)，形成由隔离物限定的源极与漏极，在源极、漏极与栅极的顶面形成硅化物以用于接触等。根据某些其它实施例，隔离物、源极与漏极、和/或硅化物的形成可在以下更详细说明的栅极替换工艺之后的随后的阶段进行。在任何情况下，为了不模糊本发明的本质，本领域技术人员可参照其它公开文献和/或专利申请来了解形成FET的这些步骤的细节。
图2示例出在图1所示的步骤之后的形成FET 100的步骤。具体而言，随后，在FET 100的顶部上形成应力衬里202，该衬里202可对栅极导体201下方的FET 100的沟道区域施加应力。应力衬里202为压缩应力衬里、拉伸应力衬里或双应力衬里。在p型掺杂的FET(PFET)100的情况下，可通过应力衬里202施加压缩应力，其中通过在例如等离子体增强化学气相沉积(PECVD)工艺中的沉积，将应力衬里202形成在PFET 100的顶部上。也可以使用PECVD以外的其它公知方法来形成应力衬里202。应力衬里202可为压缩的氮化物衬里或压缩的氧化物衬里。然而，本领域技术人士应理解，压缩应力衬里并不限于氮化物衬里或氧化物衬里，也可使用其它的压缩应力衬里材料。
根据一个实施例，在n型掺杂的FET(NFET)的情况下，通过应力衬里202施加拉伸应力。根据另一实施例，应力衬里202具有的应力基本上接近于零。换言之，也可以在下面更详细描述的栅极替换工艺中使用非应力衬里202。
在不丧失一般性的条件下，假设FET 100为PFET，为了增强压缩应力衬里202在FET 100的沟道区域中施加应力时的有效性，根据本发明的某些实施例，在形成栅极导体201(其可以称为替换栅极或虚栅极)的前一步骤(图1)中，可使用杨氏模数低的导体材料。例如，公知多晶硅(Si)适合作为栅极导体，且其具有约130Gpa的杨氏模数标称值。然而，由硅(Si)与锗(Ge)的化合物所制成的栅极导体材料所具有的杨氏模数值小于Si的值，其典型地在103与130Gpa之间。例如，Si0.8Ge0.2的杨氏模数为约124，Si0.5Ge0.5为约116，而锗(Ge)具有约103的杨氏模数值。
表1列出了一些可用于栅极导体的可能的备选材料。对于每一种备选材料，除了其杨氏模数值之外，表1还给出了其各自的熔点、迁移率因子以及带隙值。
表1：栅极导体的备选材料
  材料   杨氏模数(GPa)   熔点(℃)   迁移率因子   带隙(eV)
  Si   130   1412   1   1.12
  Si0.8Ge0.2   124   1275   1.05   1.03
  Si0.5Ge0.5   116   1109   1.12   0.891
  Ge   103   938   1.26   0.661
  GaP   103   1457   1.26   2.26
  GaAs   85.3   1240   1.52   1.424
  Al0.5Ga0.5As   84.4   1351   1.54   1.8
  AlAs   83.5   1740   1.56   2.168
  InP   61.1   1062   2.13   1.344
  InAs   51.4   942   2.53   0.354
  ZnO   108   1975   1.20   3.2
  ZnS   74.4   1718   1.75   3.54
  ZnSe   70   1525   1.86   3.10
  CdS   50   1750   2.6   2.42
  CdTe   52   1041   2.5   1.56
本领域技术人员应理解，表1中所列的大部分材料具有的杨氏模数都小于硅(130GPa)。具体地，所列出的材料包括了Si0.8Ge0.2、Si0.5Ge0.5、Ge、GaP、GaAs、Al0.5Ga0.5As、AlAs、InP、InAs、ZnO、ZnS、ZnSe、CdS与CdTe。一旦杨氏模数较小的材料被用于替换栅极201，其将对施加于其上的外力呈现较小的抵抗，因此通过应力衬里202施加的压缩应力会更有效地传递至FET 100的沟道区域。
图3示例出在图2所示的步骤之后形成FET 100的步骤，以进一步加强由应力衬里202所产生的应变效果。更具体而言，可去除应力衬里202的顶部部分以暴露其下方的栅极导体或替换栅极201。通过在应力衬里202的顶部和栅极导体201的顶部201a处产生共面表面202a、202b的诸如化学机械抛光(CMP)工艺的公知工艺，去除栅极导体201的顶部处的应力衬里202。对替换栅极201顶部处的应力衬里202的选择性去除可以导致至少部分地释放沿该方向的由应力衬里202引起的应力，从而加强在替换栅极201下方的沟道区域中的应变效果。根据本发明实施例，在下文中更详细描述的栅极替换处理中，获得进一步释放。
图4示例出在图3所示的步骤之后、在暴露了栅极导体201的顶部之后形成FET 100的步骤。随后，通过例如RIE蚀刻工艺，去除暴露的栅极导体201，其中在RIE蚀刻工艺中可选择所使用的一种或多种蚀刻剂，以使蚀刻工艺对栅极导体材料具有选择性。换言之，栅极导体201的蚀刻会留下基本上完整的氮化物应力衬里202a与202b。对用于进行选择性RIE蚀刻的蚀刻剂的选择是本领域中的公知技术，因而没有进一步详细描述。在去除栅极导体201之后，介电氧化物103的因栅极导体201的去除而暴露的部分也被选择性去除，从而暴露下方的FET 100的沟道区域，仅留下在衬里202a之下的层103a和在衬里202b之下的层103b。然而，本发明的实施例并不限于此。例如，根据某些实施例，在栅极导体201下方的介电氧化物层103可以保持完整或基本上完整，在该情况下，便不必在开口的栅极区域(如以下所详细描述的)中再次生长介电氧化物层。在一个实施例中，层103a与103b是在源极和漏极区域104上方的硅化物以作为FET100的电接触。
根据一个实施例，栅极导体或替换栅极201的去除使应力衬里202进一步弛豫，导致应力从沟道的两侧(包括从应力衬里202与应力源104及任何其它可能来源)更有效地传递至FET 100的沟道区域。即使在非应力衬里202的情况下，替换栅极201的去除仍使来自应力源104的应力传递至沟道区域。应注意，本领域技术人员可以理解：应力源104可包括嵌入的SiGe、嵌入的SiC或可由任何未来技术形成的任何其它类型的应力源。
图5示例出在图4所示的步骤之后、在栅极导体201与下方的介电层103都已去除后的形成FET 100的步骤。在沟道区域的顶部正上方的开口中形成新的介电层211，介电层211可以为栅极氧化物层。
图6示例出在图5所示的步骤后、在形成栅极氧化物层211后的形成FET 100的步骤。直接在栅极氧化物层211的顶部上，通过例如在应力衬里202之间的开口中沉积，形成新的栅极212。在沉积栅极212之后，进行诸如CMP工艺的平面化处理，以形成可以与表面202a与202b共面的表面。栅极212可以为弛豫的栅极导体，其材料为例如多晶硅、钨(W)、或金属硅化物。然而，本发明并不限于此，也可使用其它类型的栅极材料，包括置于栅极与下方的栅极氧化物层211之间以保护栅极氧化物的任何适当的薄层。
图7示例出在图6所示的步骤后、在形成栅极212后的形成FET 100的步骤。可选地，可以在应力衬里202与栅极212的顶部上形成弛豫的氮化物扩散阻挡层213，在其上形成本领域公知的层间介电层(ILD)214。扩散阻挡层213保护ILD层214免于受到氮化物应力衬里202的沾污。在图8所示的下一步骤中，通过公知的蚀刻与沉积工艺，形成金属接触215与216。例如，形成金属接触215以接触栅极212，形成金属接触216以接触在嵌入的SiGe区域104中的源极/漏极，该金属接触216可能穿过硅化物103a与103b。
根据本发明的可替代的实施例，如图2-6所述的栅极替换工艺可以应用于形成FET 100的较早阶段，并可以应用于在源极/漏极区域中没有形成嵌入的硅锗的情况。例如，如图9所示，可以在经由栅极介电层103在半导体衬底101的顶部上形成替换栅极201之后，实施上述处理步骤。根据该实施例，在去除替换栅极201的材料以在应力衬里202内部形成开口(如图4所示)之后，来自应力衬里202的应力可有效地传递至在开口之下的衬底中的沟道区域。然而，本发明并不限于此，在去除了栅极材料201之后，由应力源(例如，应力衬里、eSiGe等)所施加的任何其它类型的应力都可以从替换栅极201的两侧有效地传递至FET 100的沟道区域。
在作为栅极替换工艺的一部分的图2中，在栅极201(虚栅极或替换栅极)的顶部上形成应力衬里202，在该步骤之后为平面化(CMP)步骤以对栅极201的顶部开口来为虚栅极201的去除作准备。然而，本发明并不限于此。例如，如图10所示，在氮化物应力衬里202的厚度小于栅极201的高度的情况下，可以形成附加的一个或多个层(例如，氧化物层203)，直到覆盖栅极201的顶部从而可以在随后执行CMP工艺为止。这里，技术人员将理解，应力衬里202并不限于氮化物应力衬里，只要已经在替换栅极201的两侧形成了应力源(例如图10所示的eSiGe 104)，应力衬里202甚至可以不是应力衬里，并可以为常规非应力衬里。根据一个实施例，应力衬里202的形成是可选的。
根据一个实施例，在如图4去除了替换栅极201之后并依赖于形成FET 100的阶段，可以在开口中的应力衬里202的侧壁上形成隔离物204a与204b，如图11所示。可修整隔离物204a与204b以限定在其中形成的栅极导体的宽度并使栅极导体远离源极/漏极及其延伸区域。在形成隔离物204a与204b之后，可以在隔离物204a与204b之间如图5-6所示地形成介电氧化物层211和栅极导体212。
根据另一实施例，在图6所示的步骤之后，选择性地去除该至少部分弛豫(由于开口所致)的应力衬里202，如图12所示。在该情况下，可将在图6的步骤中用于形成栅极导体212的材料选择为具有相对高的杨氏模数(例如，等于或高于多晶硅的杨氏模数)，以使栅极导体212能够在栅极导体212之下的沟道区域中保持或维持由应力衬里202的压缩应力所引起的应变(至某种程度)。换言之，可在去除应力衬里202时，将FET 100的沟道区域中的应力(如果有的话)弛豫至较低程度。根据又一实施例，在源极/漏极区域处形成源极/漏极以及硅化物时，如果需要并且先前没有形成，可以在FET 100的顶部上形成新的应力衬里205，如图13所示。应力衬里205可进一步加强施加到在栅极导体212和栅极电介质211之下的沟道区域的应变。
虽然在这里已示例和描述了本发明的特定特征，但是本领域的技术人员很容易想到多种修改、取代、改变以及等效例。因此，应理解，所附的权利要求旨在涵盖落入本发明的精神内的所有这样的修改和改变。

Claims (23)

1.一种向场效应晶体管(100)的栅极之下的沟道区域施加应力的方法，所述场效应晶体管(FET)包括所述栅极、源极区域以及漏极区域，所述方法包括以下步骤：
在所述FET的所述源极和漏极区域中嵌入应力源(104)；
形成应力衬里(202)以覆盖所述FET的所述栅极以及所述源极和漏极区域；
去除所述应力衬里的一部份，所述应力衬里的所述部分位于所述栅极的顶部上；
去除第一栅极材料(201)的所述栅极的至少实质的部分，由此在其中产生开口；以及
用第二栅极材料(212)填充所述开口。
2.根据权利要求1的方法，还包括：在用所述第二栅极材料填充所述开口之后，去除覆盖所述FET的所述源极和漏极区域的所述应力衬里。
3.根据权利要求2的方法，还包括：在去除了覆盖所述源极和漏极区域的所述应力衬里之后，形成新的应力衬里(205)以覆盖所述第二栅极材料的所述栅极以及所述FET的所述源极与漏极区域。
4.根据权利要求1的方法，其中所述第一栅极材料具有的杨氏模数值小于130GPa。
5.根据权利要求4的方法，其中所述第一栅极材料具有的杨氏模数值小于115GPa。
6.根据权利要求5的方法，其中所述第一栅极材料具有的杨氏模数值小于100GPa。
7.根据权利要求1的方法，其中所述第一栅极材料选自Si0.8Ge0.2、Si0.5Ge0.5、Ge、GaP、GaAs、Al0.5Ga0.5As、AlAs、InP、InAs、ZnO、ZnS、ZnSe、CdS、以及CdTe。
8.根据权利要求1的方法，其中所述第二栅极材料具有的杨氏模数值等于或大于130GPa。
9.根据权利要求1的方法，其中所述栅极为栅极导体，还包括去除所述第一栅极材料的所述栅极导体以及其下的栅极氧化物层(103)，还包括在用所述第二栅极材料填充所述开口之前，在所述开口中形成新的栅极氧化物层(211)。
10.根据权利要求1的方法，其中所述去除所述栅极的所述实质部分包括：
通过应用化学机械抛光技术，暴露所述栅极的顶部(201a)；以及
相对于所述应力衬里的材料选择性地蚀刻所述第一栅极材料的所述栅极。
11.根据权利要求1的方法，其中所述去除所述栅极的所述实质部分包括：
用介电材料(203)覆盖所述应力衬里；
通过应用化学机械抛光技术，暴露所述栅极的顶部；以及
相对于所述介电材料选择性地蚀刻所述第一栅极材料的所述栅极。
12.根据权利要求1的方法，还包括：在用所述第二栅极材料填充所述开口之前，在所述开口的侧壁上形成隔离物(204a，204b)。
13.根据权利要求1的方法，其中所述应力衬里为具有基本上接近于零的应力值的非应力衬里。
14.一种向场效应晶体管(100)的栅极之下的沟道区域施加应力的方法，所述场效应晶体管(FET)包括所述栅极、源极区域以及漏极区域，所述方法包括以下步骤：
使用栅极材料(201)形成所述FET的所述栅极，所述栅极材料具有的杨氏模数值小于130GPa，其中所述栅极材料为第一栅极材料(201)；以及
在所述栅极的两侧形成应力源(202)，其中所述应力源包括覆盖所述FET的所述栅极以及所述源极与漏极区域的应力衬里(202)；
去除所述应力衬里的一部分，所述应力衬里的所述部分位于所述栅极的顶部(201a)上；
去除所述第一栅极材料的所述栅极的至少实质部分，由此在其中产生开口；以及
用第二栅极材料(212)填充所述开口。
15.根据权利要求14的方法，其中所述栅极材料具有的杨氏模数值小于115GPa。
16.根据权利要求15的方法，其中所述栅极材料具有的杨氏模数值小于100GPa。
17.根据权利要求14的方法，还包括：在用所述第二栅极材料填充所述开口之后，去除覆盖所述FET的所述源极和漏极区域的所述应力衬里。
18.根据权利要求14的方法，其中所述栅极材料选自Si0.8Ge0.2、Si0.5Ge0.5、Ge、GaP、GaAs、Al0.5Ga0.5As、AlAs、InP、InAs、ZnO、ZnS、ZnSe、CdS、以及CdTe。
19.根据权利要求14的方法，其中所述栅极为栅极导体(201)，还包括：去除所述第一栅极材料的所述栅极导体以及其下的栅极氧化物层(103)，还包括在用所述第二栅极材料填充所述开口之前，在所述开口中形成新的栅极氧化物层(211)。
20.根据权利要求14的方法，其中所述去除所述栅极的所述实质部分包括：
通过应用化学机械抛光技术，暴露所述栅极的顶部(201a)；以及
相对于所述应力衬里的材料选择性地蚀刻所述第一栅极材料的所述栅极。
21.一种向场效应晶体管(100)的栅极之下的沟道区域施加应力的方法，所述场效应晶体管(FET)包括所述栅极、源极区域以及漏极区域，所述方法包括以下步骤：
在所述FET的所述源极和漏极区域中嵌入应力源(104)；
形成应力衬里(202)以覆盖所述FET的所述栅极以及所述源极与漏极区域；
去除所述应力衬里的一部份，所述应力衬里的所述部分位于所述栅极的顶部(201a)上；
去除第一栅极材料(201)的所述栅极和其下的第一栅极氧化物层(103)，由此在其中产生开口；
用第二栅极氧化物层(211)填充所述开口；以及
在所述第二栅极氧化物层上填充第二栅极材料(212)。
22.根据权利要求21的方法，还包括：在用所述第二栅极材料填充所述开口之后，去除覆盖所述FET的所述源极与漏极区域的所述应力衬里。
23.根据权利要求22的方法，还包括：在去除所述应力衬里之后，形成新的应力衬里(205)以覆盖所述第二栅极材料以及所述FET的所述源极和漏极区域。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8404538B2 (en) * 2009-10-02 2013-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Device with self aligned stressor and method of making same
US8313990B2 (en) * 2009-12-04 2012-11-20 International Business Machines Corporation Nanowire FET having induced radial strain
US8309991B2 (en) * 2009-12-04 2012-11-13 International Business Machines Corporation Nanowire FET having induced radial strain
US20110215376A1 (en) 2010-03-08 2011-09-08 International Business Machines Corporation Pre-gate, source/drain strain layer formation
US8421132B2 (en) 2011-05-09 2013-04-16 International Business Machines Corporation Post-planarization UV curing of stress inducing layers in replacement gate transistor fabrication
CN103187308B (zh) * 2011-12-29 2015-06-03 中芯国际集成电路制造(上海)有限公司 结型场效应管及其形成方法
US9577035B2 (en) * 2012-08-24 2017-02-21 Newport Fab, Llc Isolated through silicon vias in RF technologies
US9368626B2 (en) * 2013-12-04 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with strained layer
US10079208B2 (en) * 2016-07-28 2018-09-18 Globalfoundries Inc. IC structure with interface liner and methods of forming same
JP7367527B2 (ja) * 2019-12-27 2023-10-24 株式会社オートネットワーク技術研究所 コネクタ
CN115440815A (zh) * 2021-06-01 2022-12-06 长鑫存储技术有限公司 一种半导体器件及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6225173B1 (en) * 1998-11-06 2001-05-01 Advanced Micro Devices, Inc. Recessed channel structure for manufacturing shallow source/drain extensions
CN1956222A (zh) * 2005-10-27 2007-05-02 松下电器产业株式会社 半导体装置及其制造方法
CN1976033A (zh) * 2005-12-02 2007-06-06 富士通株式会社 半导体器件及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060160317A1 (en) * 2005-01-18 2006-07-20 International Business Machines Corporation Structure and method to enhance stress in a channel of cmos devices using a thin gate
US7687861B2 (en) * 2005-10-12 2010-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Silicided regions for NMOS and PMOS devices
US7939413B2 (en) * 2005-12-08 2011-05-10 Samsung Electronics Co., Ltd. Embedded stressor structure and process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6225173B1 (en) * 1998-11-06 2001-05-01 Advanced Micro Devices, Inc. Recessed channel structure for manufacturing shallow source/drain extensions
CN1956222A (zh) * 2005-10-27 2007-05-02 松下电器产业株式会社 半导体装置及其制造方法
CN1976033A (zh) * 2005-12-02 2007-06-06 富士通株式会社 半导体器件及其制造方法

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