TW200522171A - Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films - Google Patents
Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films Download PDFInfo
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- TW200522171A TW200522171A TW093124979A TW93124979A TW200522171A TW 200522171 A TW200522171 A TW 200522171A TW 093124979 A TW093124979 A TW 093124979A TW 93124979 A TW93124979 A TW 93124979A TW 200522171 A TW200522171 A TW 200522171A
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- gate
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- sacrificial
- stop layer
- etch stop
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
200522171 九、發明說明: 【發明所屬之技術領域】 本發明係關於半導體及半導體製造領域;更特定言之, 本發明係關於電晶體閘極及其製造、減少缺陷及提高效能 之方法。 【先前技術】 在努力建造具更高效能及提高的良率之積體電路之過程 中已經出現了汗多加工技術。一種此技術改良係如下之革 新:利用一犧牲閘極來改良閘極結構之幾何形狀及可製造 性及效能。提高積體電路效能之第二種改良涉及包括一底 層應變半導體層之多種製程。 形成元件之一般製程可由不同步驟組成。已知及相關技 術可包括以下步驟。利用一起始晶圓或基板,用二氧化矽 薄膜層初步形成(develop)用於加工之矽表面。接下來,使 用遮罩(通常為氮化矽)來製造多個層。可用化學氣體沈積法 或其等效方法來界定及形成開關元件之主動區域,且濕式 蝕刻階段可利用磷酸來隨後移除非吾人所欲之沈積物。 對於MOS元件,在矽基底或基板上形成一閘極介電層及 (接著)形成一閘極。首先,準備好用於加工之基板表面,且 在該基板裏形成一阱區域。接著,形成包括閘極介電質、 側壁及側壁間隔物之閘極結構。隨後,一般使用植入及氧 化物生長步驟來生成元件内不同區域之電特徵。在閘極形 成後通常藉由在石夕基板之上表面中進行植人或擴散而形成 源極及汲極區域。可移除犧牲閘極為沈積永久閘極材料作 95558.doc 200522171 準備。可執行改進電晶體幾何形狀及電特徵之進一步步驟 以及開啓接觸窗之隨後步驟及互連結構之生成。 形成犧牲閘極結構之一缺點存在於執行金屬研磨加工過 程中,於該過程中可引入許多缺陷或高缺陷率。可能的缺 陷保留於剩餘閘極結構及層間介電層(inter level dielectric layer)中及周圍。 關於增強矽開關元件之效能,新近創新之一包括在形成 任何開關元件之前在底層基板上形成一應變基板層。通 书在氣、弛的層上製造薄的應變矽層。然後在底層應變矽 層上製造MOS元件。該應變矽層係藉由結晶失配而建立, 該結晶失配係透過利用一種具有比矽晶格常數更大或與其 不同之晶格常數之材料(如矽鍺)而達成。鍺之晶格常數約比 矽的b曰格吊數大4%。結果,當矽晶體沈積在含鍺之基板頂 郤時又到張力的作用。結晶失配導致上部矽層發生應變, 其造成在所形成之矽開關内電洞及電子遷移率增大。穿過 5亥張力⑪之電子流4加大,導致於該等張力㈣上形成之 開關元件之效能增高。 r、、、;而張力石夕技術之難點係:在該張力石夕層下存在著鬆 弛的#鍺層’其中該秒鍺層可受MOS元件製造期間之不同 加工步驟(諸如熱氧化、㈣準石夕化物(salicide)形成及退火) 的影響。形成應變矽層之另一問題係··隨後在以後的加工 步驟期間曝露於高溫中可能實際上移除在底層石夕層中形成 的一些或所有的結晶張力。 【發明内容】 95558.doc 200522171 本發明描述了一種新穎的電晶體結構及其製造方法。在 形成源極、汲極及通道之植入過程期間,通常在半導體製 程中使用犧牲閘極。本發明性製程包括··形成一犧牲閘極 結構,整合-替代閘極;及在沈積餘刻停止及/或張力誘導 層之前使用研磨及濕式蝕刻步驟來減少缺陷。並且,替代 閘極係建構金屬閘極之可能的選擇物。本發明之電晶體包 括在電晶體結構之上形成一在底層結構中產生張力之層。 【實施方式】 θ 在一實施例中,用犧牲閘極建構電晶體。圖丨闡明一具有 犧牲閘極結構之電晶體結構。犧牲閘極結構形成於基板2〇5 之上。該基板通常係矽晶圓。在基板205之上形成閘極介電 質215及犧牲閘極210。藉由熱氧化該基板、化學氣體沈積 (CVD)或其它技術,可在基板2〇5上生長閘極介電質215。犧 牲閘極210可由包括多晶石夕或二氧化石夕(Si〇2)在内的多種材 料製成。 在基板上形成一犧牲閘極結構之後,使用摻雜或植入步 驟以形成電晶體内不同區域之電特徵。形成源極及汲極延 伸或尖端242以加強電晶體崩潰電壓,從而近似地在閘極及 源極/汲極區域之間界定一通道區域250。 形成延伸區域242之後,在犧牲閘極21〇之側面上形成側 壁間隔物220,其與犧牲閘極210之剖面高度一致。側壁間 隔物一般為氮化物或氧化物,且係藉由熱氧化或藉由化學 氣體沈積(CVD)法形成。側壁間隔物材料之實例係氮化矽、 掺碳氮化物或無氧化物組份之摻碳氮化物。 95558.doc 200522171 源極及汲極區域240/241之剩餘部分係藉由植入或高度 摻雜該區域而形成,同時閘極及側壁間隔物充當障壁。在 植入後,應用一退火過程以激活所植入的摻雜物及修復任 何植入損傷。可在低熱預算(thermal budget)(例如,短時高 溫)下執行該退火過程以避免摻雜物重新分佈。 接著,執行一犧牲層間介電膜之毯覆沈積,繼之以一研 磨過程以平面化及曝露閘極。圖1中,在已形成閘極介電質 2 15、犧牲閘極2 1 〇、閘極側壁間隔物220、源極/汲極區域 240/241及通道250之後,將一犧牲層間介電層(ILD〇) 230毯 覆沈積於基板及閘極結構之上。可用化學或機械研磨技術 進一步加工犧牲ILD0層230以平面化該犧牲ILD0層及曝露 犧牲閘極210之上表面。 接著,如圖2所示蝕刻掉犧牲閘極堆疊。移除犧牲閘極以 為沈積永久閘極做準備。該蝕刻過程應提供使閘極側壁間 隔物220及犧牲層間介電層(ILD〇)23〇保持完整之選擇率。 選擇蝕刻材料,以比蝕刻側壁間隔物高得多的速度選擇性 地蝕刻該犧牲閘極材料。蝕刻選擇率較佳應在約ι〇:ι或更 高之範圍Μ。在一實施例中,為獲取最大選擇率,採用室 溫(攝氏20到30度)下約30分鐘之蝕刻時間。 a)在-實施例中’藉由一濕式蝕刻過程來移除犧牲閘 極,例如,當犧牲閘極2_多晶料,可❹諸如氯氧化 銨或HF/硝酸混合物之蝕刻劑。 w在另-實施例中’當犧牲閘極21()係氮切時,可使用 諸如雄酸钱刻劑之韻刻劑。 95558.doc 200522171 C)在另一貫施例中,當犧牲閘極210係氧化物時,可使用 諸如氫氟酸之蝕刻劑。 ° 蝕刻過轾移除犧牲閘極,並在側壁間隔物220 —邊下溝槽305 ’其隨後將由一替代閘極所填充。在一 只施例中,閘極介電質215將保留。 在另一貫施例中,如圖3所示,當移除犧牲閘極時,亦可 移綠於側壁間隔物22Q之間的閘極介電質(氧化物)215。在 /實知例中’替代閘極製程將包括對溝槽共形沈積一新 間極介電質216’諸如(但不限於)包括Hf〇2、ΖΚ)2、Al2〇3、 =2〇5、Tl〇2、La"3之高k材料。可藉由熱氧化基底基板、 藉由諸如化學氣體沈積(CVD)或原子層沈積(ALD)之其它 技術來生長該替代閘極介電質。在已沈積新閘極介電層之 後,其可視情況進行退火或經受遠端電漿氮化㈣ Plasma nitddization)(RPN)或其它後氧化物生長處理。接著 如下文進一步描述而加工該結構。 接著,執行一替代閘極沈積。圖4闡明了 一替代閘極製 程。沈積替代閘極410以填充凹陷或溝槽,並亦在犧牲層間 介電層(ILD0)230之上沈積該替代閘極。可使用多種過程(例 如熱氧化、化學氣體沈積、原子層或多晶矽沈積)來生長該 替代閘極。替代閘極材料可以係多晶矽、矽化物、氧化物、 金屬或其它導電材料。而且,替代閘極可為單一金屬或多 種金屬。可使用(但不限於)鋁(A1)、鈦(Ti)、鉬(M〇)、鎢(w) 作為替代閘極金屬,且亦可使用金屬氮化物及金屬碳化 物’例如鈥的氮化物及碳化物(TiN,TiC)或钽的氮化物及 95558.doc -10- 200522171 碳化物(TaN,TaC)。 接著,執行研磨過程。圖5闡明了在已研磨閘極後的結 構。在圖5中,替代閘極結構之頂部經受一研磨過程,以平 面化表面及曝露閘極。在將替代閘極沈積於凹陷或溝槽之 上後,執行研磨來移除任何非吾人所欲之金屬,同時使該 溝槽充滿、閘極510曝露出來且該結構經平面化。該研磨過 私般對側壁間隔物及犧牲層間介電質(ild〇)具有選擇性 以維持閘極之垂直尺寸。對犧牲層間介電層及替代閘極之 研磨一般會從替代閘極移除掉不到5〇埃的高度。然而,對 金屬閘極510之研磨及平面化能導致表面凹陷或會留下細 紋之其它研磨非均衡性,其可對良率產生重大影響。圖5 闡明了由研磨過程引起的可能缺陷模式,其包括金屬污點 5 90、犧牲ILD0 530之凹坑或凹陷區域591中的沈積物。這 些缺陷可由刮擦、擊擦(div〇t)或構形(歸因於在最初的犧牲 ILD平面化期間過度研磨直至閘極5丨〇及側壁間隔物)所引 起。 接著’然後用I虫刻過程移除研磨缺陷。利用一犧牲層間 介電層減少了由研磨過程引起的缺陷。現藉由使用一濕式 飯刻過程來選擇性地移除犧牲ILD〇層及剩餘的研磨缺陷。 移除研磨缺陷提供了更高的總體良率。 前述研磨過程曝露了犧牲層間介電質(ILD0),使得蝕刻 過程可生效。圖6中,對犧牲層間介電(ILD0)層之濕式蝕 刻,藉此移除曝露了電晶體結構610,且亦具有起離 (lifting-off)諸如圖5所示之非吾人所欲之金屬細紋或缺陷 95558.doc 200522171 之頟外盈處。對於金屬填充之凹坑、凹陷區域及金屬污點, 對犧牲ILD0之濕式蝕刻移除充當一起離層,以移除該等非 吾人所欲之金屬缺陷,為下一層之沈積做準備。 述擇蝕刻材料,以便用高於蝕刻其它特徵的速率來蝕刻 該犧牲ILD0。使用對該犧牲ILD〇具選擇性而不蝕刻該等間 隔物、金屬閘極及(另外)表體基板、諸如淺溝槽隔離(STI) 區域或自對準矽化物覆蓋擴散區(diffusi〇n)之其它特徵的 濕式蝕刻過程。蝕刻選擇率較佳在約1〇:1或更高的範圍 内。該濕式蝕刻移除過程從替代閘極移除掉不到丨〇埃的高 度。在一實施例中,為獲取最大選擇率,採用在室溫(攝氏 20至30度)下約2至5分鐘之蝕刻時間。 a) 在一實施例中,配合不含氧化物組份之摻碳氮化物間 隔物一同使用化學計量的氮化矽犧牲ILD〇。 b) 在另一實施例中,配合氮化矽或摻碳氮化物間隔物一 同使用溫和化學氣體沈積(CVD)氧化物犧牲ILD〇。 c) 在使用摻碳氮化物間隔物之實施例中,可用經調節的 麟酸來移除犧牲ILD0層。 d) 在使用氮化石夕或摻碳氮化物間隔物之實施例中,可用 經緩衝氫氟酸(HF)溶液(或與諸如乙二醇之界面活性劑一 起使用)來移除犧牲ILD0層。 e) 亦可使用其它各向同性或各向異性钱刻過程。 在一替代實施例中,可使用非常短的金屬蝕刻以沿著閘 極堆疊頂部而移除剩餘的羽狀缺陷(feather defects),例 如,在攝氏70度下,在硫酸及過氧化氫混合物中的氮化鈦 95558.doc 12 200522171 餘刻將以每分鐘約60埃之蝕刻速率進行。 在移除了犧牲層間介電質後,電晶體現在曝露出來且從 忒結構起離了金屬缺陷,如圖6所說明。現在將氮化物蝕刻 停止層(NESL)及/或張力誘導膜層添加在該電晶體之上。在 一貫施例中’如圖所示,閘極介電質215保留下來。在圖3 所示之實施例中,繼續對該結構進行相似之加工。圖7闡明 了包含應變NESL層710之發明性結構之一實施例。該neSL 7 10係形成於電晶體結構750之上。 氮化物#刻停止層(NESL)710在電晶體之通道250、源極 240及沒極241部分產生張力。利用電晶體75〇(如圖所示, 但包括隨後形成之特徵),當將正確極性之電荷施加至閘極 210時’通道區域250電反轉(invert)且變成源極240及汲極 241區域之間的導電路徑。形成於閘極結構21〇之上的nesl 710在底層電晶體中產生會提高電子及/或電洞遷移率之張 力,從而導致約10%至2〇%之效能提升。 在一實施例中,藉由使用矽烷及氮之化學氣體沈積法來 執行氮化物蝕刻停止層(NESL)之沈積。亦可使用其它等效 沈積過程。NESL層可為在整個基板之上的毯覆沈積物,或 者’ NESL可選擇性地形成於個別元件或電晶體之上。nesl 沈積亦可在接近或低於攝氏400度之溫度下於相對較短的 時期(例如約1分鐘)中形成,從而允許與任何熱敏金屬替代 閘極選擇物成功地進行整合。 在一實施例中,氮化物蝕刻停止層(NESL)之厚度約為500 埃。然而,100埃至1200埃之範圍亦將在底層電晶體内誘發 95558.doc -13- 200522171 張力,以便提高效能。在另一實施例中,NES]L由氮化矽 (Si3N4)組成。亦可使用用以形成NES]L之多種不同材料,諸 如鍺、矽鍺(SiGe)、其它氧化物(諸如摻碳二氧化矽)、或摻 碳氮化石夕。 接著,如圖8所示,在已沈積氮化物蝕刻停止層(NESl)71〇 後,隨後沈積一,,合乎標準,,的層間介電(11^)層83()。該ILD 層可為二氧化矽或低k介電質。然後可繼續進一步加工(例 如)來改進電晶體之幾何形狀或電特徵及/或開啓用於形成 互連結構之接觸窗。在替代實施例中,可使用額外的應變 層。在一實施例中,可使用一蝕刻過程來移除第一 NESL之 部分以形成與隨後沈積之額外NESL的互體。 此外,在一實施例中,可沈積NESL以隨後允許形成如圖9所 不之非著陸接觸(un-landed contact)。展示了 一淺溝槽隔離 (STI)區域920及非著陸接觸窗91〇。可形成曝露STI之部分 的接觸窗,為隨後在該等元件之上形成互連之進一步加工 做準備。 應注意的係,本文描述之加工步驟及結構並未形成一用 於製造積體電路之完整加工流程。可與多種積體電路製造 技術(包括此項技術中當前使用的該等技術)相結合來實踐 本發明。同樣地,僅在常用加工步驟對於理解本發明為必 要之情況下,才會將其包括於本說明中。 對於熟習此項技術者為顯而易見的是:可進行多種變化 而不偏離本發明之範疇,不應認為本發明之範疇侷限於本 說明書中所述之内容。應瞭解可利用其它實施例且可進行 95558.doc •14- 200522171 邏輯、機械及電變化而不偏離本發明之轉 ^炙積神及範疇。在諸 圖式中’貝穿纟玄專右干視圖’相同數字> 双子彳田述大體上類似的 組件。 【圖式簡單說明】 圖1闡明已形成閘極介電質及閘極後之犧牲閘極堆疊。 圖2闡日月在已移除犧牲閘極並留下一用於隨後問極且加工 之溝槽後的圖1所示之結構。犧牲層間介電質仍舊保留。 圖3闡明在已移除犧牲閘極及閘極介電質並留下一用於 隨後閘極加工之溝槽後的圖丨所示之結構。已經沈積了一替 代閘極介電質。犧牲層間介電質仍舊保留。 圖4闡明在研磨之前沈積替代閘極後的圖3所示閘極堆 疊。 圖5闡明研磨之後之圖4所示閘極堆疊,闡明了研磨非均 衡性。 圖6闡明在餘刻移除掉犧牲層間介電層之後之圖5所示閘 極堆疊。 圖7闡明在沈積一氮化物蝕刻停止層(NESL)後之閘極結 構。 圖8闡明在沈積一層間介電層後之圖7所示閘極結構。 圖9闡明一加工中之電晶體結構、一非著陸接觸窗及淺溝 槽隔離區域。 【主要元件符號說明】 2〇5 基板 210 犧牲閘極/閘極 95558.doc -15- 200522171 215 220 230 240 241 242 250 305 216 410 510 530 590 591 610 710 750 830 910 920 閘極介電質 閘極側壁間隔物 犧牲層間介電層 源極 汲極 源極延伸區域及汲極延伸區域 通道 溝槽 φ 新閘極介電質 替代閘極 閘極 犧牲層間介電層 金屬污點 凹陷區域 電晶體結構 氮化物#刻停止層 _ 電晶體結構 ”合乎標準’’的層間介電層 非著陸接觸窗 淺溝槽隔離區 95558.doc -16-
Claims (1)
- 200522171 十、申請專利範圍: 1· 一種方法,包含·· 在一基板上形成一犧牲閘極; 在该犧牲閘極之側面上形成側壁間隔物; 形成一犧牲層間介電層; 移除該犧牲閘極; 沈積一替代閘極; 研磨該犧牲層間介電層及該替代閘極;及 對該層間介電層執行一濕式蝕刻移除。 2.如請求項丨之方法,其中該等側壁間隔物係氮化矽或摻碳 氮化物。 3. 4. 5. 6. 8. 月长項1之方法,其中該犧牲層間介電層係溫和化學氣 體沈積氧化物或化學計量的氮化矽。 如請求項1之方法,其中對該犧牲層間介電層及該替代閘 極之研磨從該替代閘極移除不到50埃的高度。 、'員1之方法,其中執行該濕式蝕刻移除 對該犧鉍Μ Μ人;β ^ ^ S H丨電層及該替代閘極之該研磨的剩餘缺 1¾ 〇 凊求項5之方法’其中使用磷酸、經調節的磷酸、含水 的氫氟岐溶㈣連料面㈣劑—起使用 =虱黾來執行該濕式蝕刻移除。 如明求項6之方法,其中連同該氫氟酸 活性劑係乙二醇。 、便用之该界面 之 如β求項5之方法’其中在約攝氏2。度至約攝氏%度 95558.doc 200522171 /皿度下執行該濕式蝕刻移除過程。 9. 如㈤求項5之方法’其中該濕式㈣移 2分鐘至5分鐘之時間週期。 、釭持續—為約 10. ::”項5之方法,其中該濕式敍 10:1或更大的近似選擇率。 八有—為 如請求項1之方法,其中該 除不到!。埃的高度。 ^移除從该替代閉極移 Ι2.:;;ίΓ之方法,其中執行對該殘留開極材料之該" :移除過程包含於攝氏7。度下在硫酸及過氧化氣二 物中使用一氮化鈦蝕刻。 13. 如π求項12之方法,其中該氮化鈦㈣以每分鐘約6〇埃 的一速率移除該層間介電層。 、 14. 如請求们之方法,其進一步包含沈積—氮化物_停止 15. 如請求項14之方法,其中該氮化物蝕刻停止層在—底層 結構中產生張力。 一 16. 如叫求項丨之方法,其進一步包含沈積一於一底層結構中 產生張力之氮化物蝕刻停止層。 17 · —種方法,包含·· 在一基板上形成一犧牲閘極·, 在該犧牲閘極之側面上形成側壁間隔物; 形成一犧牲層間介電層; 移除該犧牲閘極; 沈積一替代閘極; 95558.doc 200522171 研磨該犧牲層間介電層及該替代閘極;及 在該層間介電層上執行一濕式餘刻移除;以及 沈積-於該底層結構中產生張力之氮化物㈣停止 層。 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 如請求項17之方法,其中將該氮化物_停止層之該沈 積作為-整個基板之上的一毯覆式沈積而形成。 士叫求項17之方法,其中選擇性地在個別元件或電晶體 之上形成該氮化物蝕刻停止層之該沈積。 士”月求項17之;Jr法’其巾使帛—使⑨烧及氮或氨之化 學氣體沈積過程來執行該氮化物蝕刻停止層之該沈積。 如明求項17之方法,其中該氮化物蝕刻停止層由氮化矽 (Si3N4)組成。 如μ求項17之方法,其中該氮化物蝕刻停止層係選自由 夕錯摻故一氧化石夕及摻碳氮化^夕所組成之群。 如明求項17之方法,其中該氮化物蝕刻停止層之該沈積 厚度在100埃到1200埃之間。 如睛求項17之方法,其中該氮化物蝕刻停止層之該沈積 厚度為約500埃。 如4求項17之方法,其中在接近或低於攝氏4〇〇度之一溫 H於不到—分鐘之期間中形成該氮化物蝕刻停止層沈 積。 如4求項25之方法,其中該氮化物蝕刻停止層係相容於 感溫金屬閘極選擇物。 如請求項17之方法,其中在已沈積該氮化物蝕刻停止層 95558.doc 200522171 之後沈積一層間介電層。 28· —種形成於一基板上之電晶體,包含: 一金屬閘極; 形成於該閘極之侧面上的側壁間隔物; 一沈積於該閘極及該等側壁間隔物之上的氮化物>1 虫刻 停止層,該氮化物触刻停止層在底層電晶體結構中產生 張力;及 一形成於該等側壁間隔物、該閘極、及氮化物餘刻停 止層之上的層間介電層。 29·如請求項28之方法,其中該金屬閘極包含選自由鋁(A1)、 鈦(Ti)、鉬(Mo)、鎢(W)、鈦(TiN、TiC)及钽(TaN、TaC) 所組成之群的一或多個材料。 30·如請求項28之方法,其中該替代閘極材料包含多種金屬。 95558.doc
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