JP4843498B2 - 半導体デバイス構造を製造する方法 - Google Patents
半導体デバイス構造を製造する方法 Download PDFInfo
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- JP4843498B2 JP4843498B2 JP2006539779A JP2006539779A JP4843498B2 JP 4843498 B2 JP4843498 B2 JP 4843498B2 JP 2006539779 A JP2006539779 A JP 2006539779A JP 2006539779 A JP2006539779 A JP 2006539779A JP 4843498 B2 JP4843498 B2 JP 4843498B2
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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Description
Claims (7)
- 半導体デバイス構造を製造する方法であって、
基板を設けるステップと、
前記基板上のn型FETおよびp型FETを形成する領域上に、それぞれ、パターニングされた第1のゲート電極および第2のゲート電極を形成するステップと、
前記第1のゲート電極および第2のゲート電極の周囲に絶縁膜を形成し、該絶縁膜を平坦化することにより、前記第1のゲート電極および第2のゲート電極の上面を露出するステップと、
前記露出した第1のゲート電極および第2のゲート電極を、一部、または、全部分をエッチング除去して、それぞれ、第1のくぼみおよび第2のくぼみを形成するステップと、
前記第1のくぼみおよび第2のくぼみを、細粒ポリシリコンによって埋め込み、前記エッチング除去された第1のゲート電極および第2のゲート電極の領域を細粒ポリシリコンによって置換するステップと、
前記第1のくぼみ内に形成されたn型FETの前記細粒ポリシリコンの上面を覆うようにSiN膜を形成し、次いで前記n型FETおよび前記p型FETの前記細粒ポリシリコンを加熱して、前記p型FETの前記細粒ポリシリコンのポリシリコン粒を成長させるとともに、前記n型FETの前記細粒ポリシリコンのポリシリコン粒の再成長を防止して、前記n型FETの前記ポリシリコン粒の平均直径が前記p型FETの前記ポリシリコン粒の平均直径未満になるようにする、ステップと、を含み、
前記p型FETには、前記ポリシリコン粒の再成長により、チャネル領域に圧縮応力を印加する方法。 - 前記加熱するステップが、500℃から600℃の範囲内の温度で1時間、前記n型FETおよび前記p型FETを加熱することを含む、請求項1に記載の方法。
- 前記細粒ポリシリコンが5nmから30nmの範囲の平均粒径を有する、請求項1に記載の方法。
- 前記置換するステップが、前記第1のゲート電極および第2のゲート電極の前記一部を除去して、前記第1のくぼみおよび第2のくぼみを形成し、次いで前記第1のくぼみおよび第2のくぼみ内に前記細粒ポリシリコンを配置することを含む、請求項1に記載の方法。
- 前記置換するステップが、前記第1のゲート電極および第2のゲート電極の全部分を除去して、前記第1のくぼみおよび第2のくぼみを形成し、次いで前記第1のくぼみおよび第2のくぼみ内に前記細粒ポリシリコンを堆積することを含む、請求項1に記載の方法。
- 前記第1のゲート電極および第2のゲート電極の側面にスペーサを形成するステップを更に含み、前記第1のゲート電極の側面に設けられたスペーサと前記第2のゲート電極の側面に設けられたスペーサとが異なる高さを有する、請求項1に記載の方法。
- 前記第1のゲート電極および第2のゲート電極の側面にスペーサを設けるステップを更に含み、前記第2のゲート電極の側面に設けられたスペーサの高さが、前記第1のゲート電極の側面に設けられたスペーサの高さ未満である、請求項1に記載の方法。
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US10/707,018 US7122849B2 (en) | 2003-11-14 | 2003-11-14 | Stressed semiconductor device structures having granular semiconductor material |
PCT/US2004/037434 WO2005050701A2 (en) | 2003-11-14 | 2004-11-09 | Stressed semiconductor device structures having granular semiconductor material |
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WO2005050701A2 (en) | 2005-06-02 |
EP1683187A4 (en) | 2008-08-27 |
US7122849B2 (en) | 2006-10-17 |
WO2005050701A3 (en) | 2006-01-05 |
KR20070015499A (ko) | 2007-02-05 |
JP2007511909A (ja) | 2007-05-10 |
EP1683187A2 (en) | 2006-07-26 |
KR100946038B1 (ko) | 2010-03-09 |
CN100468785C (zh) | 2009-03-11 |
US20080064172A1 (en) | 2008-03-13 |
WO2005050701A8 (en) | 2005-11-03 |
ATE512465T1 (de) | 2011-06-15 |
CN1879227A (zh) | 2006-12-13 |
US7488658B2 (en) | 2009-02-10 |
EP1683187B1 (en) | 2011-06-08 |
US20050106799A1 (en) | 2005-05-19 |
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