TW200518470A - Delay locked loop - Google Patents

Delay locked loop

Info

Publication number
TW200518470A
TW200518470A TW093119279A TW93119279A TW200518470A TW 200518470 A TW200518470 A TW 200518470A TW 093119279 A TW093119279 A TW 093119279A TW 93119279 A TW93119279 A TW 93119279A TW 200518470 A TW200518470 A TW 200518470A
Authority
TW
Taiwan
Prior art keywords
clock
delay
locked loop
delay locked
supplied
Prior art date
Application number
TW093119279A
Other languages
English (en)
Other versions
TWI287359B (en
Inventor
Young-Jin Jeon
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200518470A publication Critical patent/TW200518470A/zh
Application granted granted Critical
Publication of TWI287359B publication Critical patent/TWI287359B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
TW093119279A 2003-11-20 2004-06-30 Delay locked loop TWI287359B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2003-0082457A KR100514414B1 (ko) 2003-11-20 2003-11-20 지연 동기 루프

Publications (2)

Publication Number Publication Date
TW200518470A true TW200518470A (en) 2005-06-01
TWI287359B TWI287359B (en) 2007-09-21

Family

ID=34587922

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093119279A TWI287359B (en) 2003-11-20 2004-06-30 Delay locked loop

Country Status (4)

Country Link
US (1) US7061287B2 (zh)
KR (1) KR100514414B1 (zh)
CN (1) CN100411057C (zh)
TW (1) TWI287359B (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100810070B1 (ko) * 2005-09-29 2008-03-06 주식회사 하이닉스반도체 지연고정루프
US7449930B2 (en) * 2005-09-29 2008-11-11 Hynix Semiconductor Inc. Delay locked loop circuit
KR100722775B1 (ko) * 2006-01-02 2007-05-30 삼성전자주식회사 반도체 장치의 지연동기루프 회로 및 지연동기루프제어방법
KR100838375B1 (ko) * 2006-04-28 2008-06-13 주식회사 하이닉스반도체 반도체 메모리 장치
KR100832021B1 (ko) 2006-06-29 2008-05-26 주식회사 하이닉스반도체 반도체 메모리 소자 및 그 구동방법
US7492199B2 (en) * 2006-07-28 2009-02-17 International Business Machines Corporation Fully synchronous DLL with architected update window
KR100803370B1 (ko) * 2006-12-27 2008-02-13 주식회사 하이닉스반도체 Ｄｌｌ 회로의 리셋 장치 및 방법
US7831855B2 (en) * 2007-04-12 2010-11-09 Harris Corporation System and method for generating a reset signal for synchronization of a signal
KR101022669B1 (ko) * 2008-12-02 2011-03-22 주식회사 하이닉스반도체 지연고정루프회로
KR101551774B1 (ko) 2009-02-25 2015-09-10 삼성전자 주식회사 코아스 록킹 페일을 방지하기 위한 지연 고정 루프 회로
KR101190683B1 (ko) * 2010-10-29 2012-10-12 에스케이하이닉스 주식회사 반도체 장치, 그의 신호 지연 방법, 적층 반도체 메모리 장치 및 그의 신호 생성 방법
KR101297413B1 (ko) 2012-02-24 2013-08-19 고려대학교 산학협력단 적응형 클럭 생성 장치 및 방법
JP5976392B2 (ja) * 2012-05-16 2016-08-23 ルネサスエレクトロニクス株式会社 半導体集積回路およびその動作方法
KR102013840B1 (ko) 2013-03-15 2019-08-23 삼성전자주식회사 다중 위상 생성기
KR102384959B1 (ko) * 2015-10-30 2022-04-11 에스케이하이닉스 주식회사 저장 장치, 이를 포함하는 메모리 시스템 및 이의 동작 방법
CN115765728B (zh) * 2022-11-29 2023-07-04 芯动微电子科技(武汉)有限公司 一种鉴频鉴相器及锁相环

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01146426A (ja) * 1987-12-02 1989-06-08 Mitsubishi Electric Corp Ｐｌｌ回路
FR2669966B1 (fr) * 1990-11-30 1993-03-26 Europ Propulsion Procede de fabrication de paroi de chambre de combustion, notamment pour moteur-fusee, et chambre de combustion obtenue par ce procede.
US5223755A (en) * 1990-12-26 1993-06-29 Xerox Corporation Extended frequency range variable delay locked loop for clock synchronization
WO1995022206A1 (en) * 1994-02-15 1995-08-17 Rambus, Inc. Delay-locked loop
US5815016A (en) * 1994-09-02 1998-09-29 Xilinx, Inc. Phase-locked delay loop for clock correction
KR0157952B1 (ko) * 1996-01-27 1999-03-20 문정환 위상 지연 보정 장치
US5757238A (en) * 1996-08-19 1998-05-26 International Business Machines Corporation Fast locking variable frequency phase-locked loop
US5933058A (en) * 1996-11-22 1999-08-03 Zoran Corporation Self-tuning clock recovery phase-locked loop circuit
JP3281306B2 (ja) * 1996-12-18 2002-05-13 三星電子株式会社 メモリ装置のディジタル遅延同期回路
US5940608A (en) * 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
JPH1168559A (ja) * 1997-08-20 1999-03-09 Nec Corp 位相同期ループ回路
JPH11163696A (ja) * 1997-11-26 1999-06-18 Fujitsu Ltd 周波数比較器及びこれを用いたクロック再生回路
US6154508A (en) * 1998-03-23 2000-11-28 Vlsi Technology, Inc. Method and system for rapidly achieving synchronization between digital communications systems
US6470060B1 (en) * 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
JP2000286703A (ja) * 1999-03-30 2000-10-13 Fujitsu Ltd リセット回路及びｐｌｌ周波数シンセサイザ
KR100311046B1 (ko) * 1999-05-15 2001-11-02 윤종용 시간/디지털 변환기, 이를 이용하는 동기 회로 및 동기 방법
US6326826B1 (en) * 1999-05-27 2001-12-04 Silicon Image, Inc. Wide frequency-range delay-locked loop circuit
AU2001275503A1 (en) * 2000-05-31 2001-12-11 Broadcom Corporation Multiprotocol computer bus interface adapter and method
US20020130691A1 (en) * 2001-03-15 2002-09-19 Silvestri Paul A. Method and apparatus for fast lock of delay lock loop
US6504408B1 (en) * 2001-07-09 2003-01-07 Broadcom Corporation Method and apparatus to ensure DLL locking at minimum delay
US6876239B2 (en) * 2001-07-11 2005-04-05 Micron Technology, Inc. Delay locked loop “ACTIVE command” reactor
US6556489B2 (en) * 2001-08-06 2003-04-29 Micron Technology, Inc. Method and apparatus for determining digital delay line entry point
KR100446291B1 (ko) * 2001-11-07 2004-09-01 삼성전자주식회사 카스 레이턴시를 이용하여 락킹 레졸루션 조절이 가능한지연동기 루프 회로
US6657463B2 (en) * 2001-12-14 2003-12-02 Thomson Licensing S.A. System for maintaining the stability of a programmable frequency multiplier
US6859413B2 (en) * 2002-09-27 2005-02-22 International Business Machines Corporation Method and apparatus for DLL lock latency detection
KR100510063B1 (ko) * 2002-12-24 2005-08-26 주식회사 하이닉스반도체 레지스터 제어 지연고정루프
US6839301B2 (en) * 2003-04-28 2005-01-04 Micron Technology, Inc. Method and apparatus for improving stability and lock time for synchronous circuits
US7071745B2 (en) * 2004-02-11 2006-07-04 Promos Technologies, Inc. Voltage-controlled analog delay locked loop

Also Published As

Publication number Publication date
CN100411057C (zh) 2008-08-13
CN1619698A (zh) 2005-05-25
US20050110541A1 (en) 2005-05-26
KR20050048755A (ko) 2005-05-25
US7061287B2 (en) 2006-06-13
KR100514414B1 (ko) 2005-09-09
TWI287359B (en) 2007-09-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees