TW200412673A - Buffer layer capable of increasing electron mobility and thin film transistor having the buffer layer - Google Patents

Buffer layer capable of increasing electron mobility and thin film transistor having the buffer layer Download PDF

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TW200412673A
TW200412673A TW092100245A TW92100245A TW200412673A TW 200412673 A TW200412673 A TW 200412673A TW 092100245 A TW092100245 A TW 092100245A TW 92100245 A TW92100245 A TW 92100245A TW 200412673 A TW200412673 A TW 200412673A
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buffer layer
electron mobility
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TW092100245A
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TW573364B (en
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Long-Sheng Liao
Kun-Chih Lin
Chia-Tien Peng
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Au Optronics Corp
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Priority to TW92100245A priority Critical patent/TW573364B/zh
Priority to US10/754,060 priority patent/US6984848B2/en
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Publication of TW200412673A publication Critical patent/TW200412673A/zh
Priority to US11/254,303 priority patent/US7608475B2/en
Priority to US12/557,131 priority patent/US8178882B2/en

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Description

200412673 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關於 _ 十 .+ π 於—種溥膜電晶體（thm fi im transistor ; TFT)之 n & 111 電子遷移率提升之緩^::，且特別是有關於-種可促進 丁層與具有该緩衝層之薄膜電晶體。 【先前技術】 白，，，液晶顯示裝置的方法中’主要 主要有非晶石夕每二…，而目前常見的薄膜電晶體 體（poly-Si TFT)、^^晶體（a-Sl:H TFT)及多晶矽薄膜電晶 tempeatiii'e DQi 、種。多晶矽又可分為高溫多晶矽（high emperature poly SiUc〇n;HTps)與低溫多 temperature poly siUc〇n;LTps)兩種。 ㈣習m多晶矽薄膜電晶體是利用準分子雷射作為 ‘、'、。二田、、，I過投射系統後，會產生能量均勻分布的雷 1 t f 4才又射於非晶矽結構的玻璃基板上，當非晶矽結構 土反吸收準分子雷射的能量後，會轉變成為多晶矽結 構。低溫多晶矽薄膜電晶體之結構於非晶矽活性層與玻璃 f板之間通常會設置一緩衝層（buffer)，緩衝層的主要功 月b不僅在於增加玻璃基板與其表面之各作用層之間的附著 性，更可提供阻擋玻璃基板内部之雜質於製程中擴散進入 各，用層的功用。傳統之緩衝層通f係以厚度約為3〇〇〇人 的氧化矽（S 1 0X)所構成，但是由於如此厚 必需耗費相當多的時間，會造成元件成本的；：〈曰因：， 一種具有SiOx/SiNx雙層材質的緩衝層被提出來，該雙層材
第5頁 200412673 五、發明說明（2) 質緩衝層係以S i Nx取代部分S i 0X，減少緩衝層的厚度，以 減少製造時間，降低成本，其中S i 0X之厚度約為1 5 0 0 A， 而S i Nx之厚度約為5 0 0 A。 然而，西元2002年Naoya等人於期刊（Active-Matrix Liquid-Crystal Displays-TFT)發表"Crystal Growth Mechanism of Polystri cal 1ine Si by Exc i mer Laser Anneal i ng Considering hydrogen Molecule and Thermal Conductance”指出在針對形成於緩衝層表面的非 晶質石夕層進行雷射退火結晶（excimer laser annealing; EL A)製程時，S i Nx缓衝層内部所含有的氫氣會穿過S丨0χ緩 衝層進入設置於緩衝層上方的非晶質矽半導體層中，產生 一應力（stress)而阻礙晶粒成長（grain growth)，使得晶 粒尺寸縮小，進而降低元件的電子遷移率。 有鑑於此，為了解決上述問題，本發明主要目的在於 提供一種可促進電子遷移率提升之緩衝層，可適用於薄膜 電晶體（TFT)。 ' 【發明内容】 本發明之目的之一在於提供一種可促進電子遷移率提 升之緩衝層與具有該緩衝層之薄膜電晶體，以阻擋薄膜電 晶體（TFT)之玻璃基板中的雜質擴散進入各作用層。 本發明之目的之二在於接报 ^ / K 杜y、杈i、一種可促進電子遷移率提 升之緩衝層與具有該绣種f屏夕π Ώ 1 …、,a、後衝層之溥朕電晶體，該緩衝層具有
200412673 五、發明說明（3) 高熱導係數（thermal C〇ndUCt1Vlty c〇enicient)，可促 使非晶質矽半導體層轉變成結晶矽時之晶粒均勾成長，進 而提升元件之電子遷移率。 i ^ 為獲致上述之目的，本發明提出一種可促進電子 率提升之缓衝層，適用於一薄膜電晶體平面顯示器之基板 表面，上述緩衝層包括··一設置於上述基板表面之1^非晶^質 石夕層（a-Si );以及一設置於上述非晶質矽層（a — Si )面3之 氧化層。 ^ 根據本發明，上述氧化層之材質可包括.氧彳匕$ (SiOx)，其厚度大體為1 0 0 0〜2 0 0 0 A，其密度:體^2 〇〜2 2 g/cm3，熱導係數（Thermal Conductivity)大體為/n· 4 Wnri Κ—1，並且可利用電漿增進式化學氣相沉2法·〜· (plasma enhanced chemical vap〇]r depositiQn ;pECVD) 形成。 本發明之特徵在於上述非晶質矽層（a —Sl)，由於 質石夕不僅具有相當高的密度，可用以阻擋上述玻璃芙s a 的雜質於後續製程中擴散進入元件的作用層（例如：$ 活性層），而且非晶質矽尚具有高熱導係數的特點·，可 後續進行雷射退火結晶（ELA)製程使非晶質矽轉變為:曰 矽時，改變散熱的狀態，使得結晶的均勻性得以又提^夕，曰曰如 此一來，便可提升電子遷移率。根據本發明，上述=曰= 石夕層（a-Si)之厚度大體為2 5 0〜1 0 0 0 A，其密度大體為^曰〜2貝 3g/cm3，再者，其氫含量大體為卜5%，並且， =二 · 矽層（a-Si)可利用電漿增進式化學氣相沉積、 a专关他方法
〇632-8725TWf(nl);AU91182;Felicia.ptd 第7頁 200412673 五、發明說明（4) 行成（plasma enhanced chemical vapor deposition ; PECVD)形成。 ’ 如前所述，本發明之緩衝層更可包括：一氮化物缓衝 層，例如：氮化矽S i Nx，設置於上述基板與上述非晶質矽層 (a - S i )之間。 本發明之可促進電子遷移率提升的緩衝層可適用於習 知之薄膜電晶體。 為使本發明之上述目的、特徵和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如 ❶ 下： 【實施方式】 以下請配合參考第1圖與第2圖之結構剖面圖，以說明 根據本發明之一較佳實施例。 首先，請參閱第1圖，本發明之緩衝層2 〇 2、2 0 4，可 適用於一薄膜電晶體平面顯示器之基板2 〇 〇表面，通常係 以玻璃作為基板200。本發明之緩衝層2 0 2、204可包括： 一非晶質矽層（a-Si) 2 0 2與一氧化層2 04。非晶質矽層 (a-Si)202設置於基板2〇〇表面，且氧化層2 04設置於非晶 質石夕層（a-Si) 2 0 2表面。本發明之緩衝層2 0 2、2 04表面可 設置一非晶質矽活性層2 〇 6。 非晶質矽層2 0 2可利用電漿增進式化學氣相沉積法 (plasma enhanced chemical vapor deposition ； PECVD)
〇632-8725TWf(nr);AU91182;Felicia.ptd 第8頁 200412673 五、發明說明（5) 形成。並且，非晶質矽層2 〇 2之厚度大體為2 5 〇〜丨0 〇 〇 A， 其密度大體為2〜2. 3g/cm3。再者，非晶質矽層2 0 2之氫含量 大體為1〜5% ’熱導係數（Thermal Conductivity)大體為 8 0〜1 5 G Wnr1 P，較少於習知s i Nx缓衝層之氫含量，可避 免習知來自於s 1 Nx緩衝層之氫氣於後續進行雷射退火結晶 (excimer laser annealing;ELA)製程時進入多晶細活性 層而阻礙其晶粒成長的問題。 氧化層204可利用電漿增進式化學氣相沉積法（plasma enhanced chemical vapor deposition ;PECVD)形成，其
月ίι驅物包括四乙烷基氧矽酸鹽（tei：raethy 1 ^讣031110^6 Sl(〇C2H5)4 ;TE0S)。並且，氧化層 204 之材 貝可包括··氧化石夕（Si〇x)，其厚度大體為1000〜2000A，其 始、度大體為2.0〜2. 2 g/cm3。 該非晶質矽緩衝層2〇2係本發明之主 相當高的密度，提供阻撞玻璃基板中、二 Hrr擴散進入元件作用層（例如：半導體活性 :可=續再進V:/非晶質w ^
變為多晶晶(關製程使非晶議 提昇，便可叫使得結晶的均勻性“ 以下請參閱第3 A圖至第 歧# 口口上 之非晶彻電晶體的早說明採用本發明 在基板20G表面依序例如/ = °百，，圖所示， 成非晶質矽緩衝層2 02、巧=*方法形 訂、虱化矽層2〇4以及非晶質矽活性層
200412673 五、發明說明（6) 2 0 6。其中，非晶質矽層2 〇 2可利用電漿增進式化學氣相沉 積法（plasma enhanced chemical vapor deposition ; PECVD)形成，其前驅物包括矽烷氣體，例如：以屯、SiA， 其氫含量約為卜5%。接著，如第3B圖所示，實施一雷射退 火結晶（E L A)程序，瞬間照射並且加熱非晶質石夕活性層 206 ’此時，非晶質矽活性層2〇6會再結晶（recrystaU ize )。由於非晶質矽緩衝層2 0 2具有高熱導係數的特點，使 得進行雷射退火結晶程序時熱能於非晶質矽活性層2 〇 6可 快速散去，便使非晶質石夕活性層2 〇 β所轉變成的多晶矽 2 0 6 a時，改變散熱的狀態，使得結晶的均勻性得以提昇， 如此一來，便可形成具有均勻性較佳的多晶矽活性層 2 0 6a，因此，可提升電子遷移率。然後，如第％圖所示， 圖案化非晶質矽緩衝層20 2、氧化矽層2 04以及多晶矽活性 層2 0 6a，以形成所需之圖案。為增加後續各層的披覆黏著 性，可將非晶質矽緩衝層2 0 2、氧化矽層2〇4以及多晶矽活 性層20 6a分別圖案化成階梯狀堆疊。然後，如第3D圖所 示，在多晶矽活性層2 0 6a上沉積一氧化層2〇8，然後在氧 化層208上沉積-金屬|，並且對金屬層圖案化以形成閘 極2 1 0。然後，如第1 E圖所示，先利用離子佈值程序在上 述多晶石夕活性層2 0 6a未被閘極214遮蓋的部分分別形成源 極S與没極區域D。最後，&在氧化層⑽及閘極21〇表面形 成一介電層212，並且利用”的技術在上述源極S與沒極 D區域上形成接觸孔，填入導電插塞（Plug)214於接觸孔 中，以便與其他部分的電路相連接。
0632-8725TWf(nl);AU9n82;Feiicia.ptd 第10頁 200412673 五、發明說明（7) 如前所述，請參照第2圖，本發明也可視需求而定增 加設置一 ll化物緩衝層3 0 2 (例如：氮化石夕S i Nx)於玻璃基板 3 0 0與非晶質矽層（a - S i ) 3 0 4之間，其他各部分皆與第1圖 所顯示之結構相同◦ 本發明雖以較佳實施例揭露如上，然其並非用以限定 本發明的範圍，任何熟習此項技藝者，在不脫離本發明之 精神和範圍内，當可做各種的更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。
0632-8725Wf(nl);AU91182;Felicia.ptd 第11頁 200412673 圖式簡單說明 第1圖係顯示根據本發明之緩衝層之一較佳實施例之 結構剖面圖。 第2圖係顯示根據本發明之緩衝層之另一較佳實施例 之結構剖面圖。 第3A圖至第3E圖係顯示根據本發明之緩衝層製作薄膜 電晶體之一較佳實施例之製程剖面圖。 符號說明： 2 0 0、3 0 0〜基板； 2 0 2、3 0 4〜非晶質矽層； 2 0 4、3 0 6〜氧化矽緩衝層； 2 0 6、3 0 8〜非晶質矽活性層； 2 0 6 a〜多晶矽活性層； 2 0 8〜氧化層； 2 1 0〜閘極； S〜源極； D〜汲極； 2 1 2〜介電層； 2 14〜導電插塞。
0632-8725TWf(nlj;AU91182;Felicia.ptd 第12頁

Claims (1)

  1. 200412673
    六、申請專利範圍 1 · 一種可促進電子遷移率提升之缓衝層’適用於一薄 膜電晶體平面顯示器之基板表面，上述缓衝層包括： 一非晶質矽層（a-Si )，設置於上述基板表面；以及 一氧化層，設置於上述非晶質矽層表面。 2 ·如申請專利範圍第1項所述之玎促進電子遷移率提 升之緩衝層，其中上述氧化層包括：氧化矽（s i )。 3 ·如申請專利範圍第1項所述之可促進電子遷移率提 升之缓衝層，其中上述氧化層之厚度大體為1000〜2〇〇〇 Α 。 4 ·如申請專利範圍第1項所述之可促進電子遷移率提 升之缓衝層，其中上述氧化層係利用電漿增進式化學氣相 沉積法（plasma enhanced chemical vapor depositi〇n . PECVD)形成。 ’ 5 ·如申請專利範圍第1項所述之可促進電子遷移率提 升之缓衝層，其中上述氧化層之密度大體為 2· 0 〜2· 2g/cm3。 可促進電子遷移率提 a-Si)之厚度大體為 6.如申請專利範圍第1項所述之 升之緩衝層，其中上述非晶質石夕層（ 2 5 0 〜1〇〇〇 A。 如甲請寻
    g民疋电于遷移i 升之缓衝層，其中上述非晶質矽層（sn _ ^ 〇 / 3 曰以61)之岔度大體 2 〜2. 3g/cm3。 8·如申請專利範圍第1項所述之 升之缓衝層，其中上述非晶質石夕声^ ς.進电子遷移率棱 •智U —Sl)之氫含量大體為
    〇632-8725TWf(nl)；AU91182;Felicia.ptd 第13頁 200412673
    9. 升之緩 式化學 depos i 10 升之緩 設置於 11 升之緩 12 薄膜電 如申請專利範圍第丨項所述之 衝層，其中上述非晶質矽層（a 電子遷移率提 氣相、V笋、、Μ 1 曰^匕1 )你利用電漿增進 虱相"L f貝法（Plasma enhanced Uon ; PECVD)形成。 vapor ‘ ㈣S$1項所述之可促進電子遷移率提 七、a ，/、中上述緩衝層更包括：一氮化物緩衝層， 上述基板與上述非晶質石夕層（a — S丨）之間。 •如申請專利範圍第1項所述之可促進電子遷移率提 衝層，其中上述氮化物缓衝層包括氮化矽Si Nx ◦ •一種可促進電子遷移率提升之緩衝層，適用於一 晶體之基板表面，上述缓衝層包括： 一非晶質層，設置於上述基板表面；以及 一結晶層，設置於上述非晶質層表面。 1 3 ·如申請專利範圍第丨2項所述之邛促進電子遷移率 k升之緩衝層，其中上述結晶層包括：氧化物。 1 4.如申請專利範圍第1 2項所述之 < 促進電子遷移率 提升之緩衝層，其中上述结晶層之厚度大體為1 0 0 0〜2 0 0 0 A 。 、。曰曰s 15.如中請專利範圍第12項戶斤述之W足進曰電所子遷移率 提升之緩衝層，其中上述非晶質層包栝：彝晶質矽 (a-Si)。 1 6如申續直刹— /夕奵促進電子遷移率 戈τ σ月專利乾圍第1 2項所述之J a 提升之緩衝層，其中上述非晶質層之厚度大體為2 5 0〜1000
    第14頁 200412673 六、申請專利範圍 A 〇 .、 、 1 7 ·如申請專利範圍第1 2項所述之，可促進電子遷移率 提升之缓衝層，其中上述非晶質層之氫含量小於1 〇 %。 1 8.如申請專利細圍第1 2項所述之可促進電子遷移率 提升之緩衝層，其中上述緩衝層更包括··一氮化矽S: Nx緩衝 層，設置於上述基板與上述非晶質層之間。 1 9· 一種具有吁促進電子遷移率提升之緩衝層的薄膜 電晶體，包括： 一基底， 一缓衝層，設置於上述基底表面，上述緩衝層包括： 一非晶質層’設置於上述基板表面；以及 —纟士晶層，設置於上述非晶質層表面； 一活性層’設置於上述、结晶層表面； 曰曰 一絕緣層，順應性覆蓋於上述活性層表面與上述非 質石夕層\上述結晶層以及上述活性層之侧壁； 一導電層，設置於部分上述活性層上方之上述絕緣層 表面；以及 一介電層，全面性覆蓋於上述結晶層與上述導電層表 面； 其中，未被上述導電層遮蔽之上述活性層分別被摻雜 成一没極與一源極。 2〇如申請專利範圍第19項所述之具有可促進電子遷 移率提升之缓衝層的薄膜電晶體，其中上述結晶層包括： 氧化物
    0632-8725Wf(nl);AU91182;Felicia.ptd 200412673 六、申請專利範圍 2 1 .如申請專利範圍第1 9項所述之具有可促進電子遷 移率提升之緩衝層的薄膜電晶體，其中上述結晶層之厚度 大體為1 0 0 0〜2 0 0 0 A。 2 2.如申請專利範圍第1 9項所述之具有可促進電子遷 移率提升之缓衝層的薄膜電晶體，其中上述非晶質層包 括：非晶質石夕（a-Si)。 2 3.如申請專利範圍第1 9項所述之具有可促進電子遷 移率提升之缓衝層的薄膜電晶體，其中上述非晶質層之厚 度大體為2 5 0〜1 0 0 0 A。 2 4.如申請專利範圍第1 9項所述之具有可促進電子遷 移率提升之緩衝層的薄膜電晶體，其中上述非晶質層之氫 含量小於1 0 %。 2 5.如申請專利範圍第1 9項所述之具有可促進電子遷 移率提升之緩衝層的薄膜電晶體，其中上述緩衝層更包 括：一氮化石夕S i Nx缓衝層，設置於上述基板與上述非晶質層 之間。
    0632-8725TWf(nlJ;AU91182;Felicia.ptd 第16頁
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KR100615229B1 (ko) * 2004-06-29 2006-08-25 삼성에스디아이 주식회사 박막 트랜지스터, 상기 박막 트랜지스터를 구비한 평판디스플레이 장치 및 상기 박막 트랜지스터의 제조방법
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US9257290B2 (en) 2013-12-25 2016-02-09 Shenzhen China Star Optoelectronics Technology Co., Ltd. Low temperature poly-silicon thin film transistor and manufacturing method thereof
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