TW200306652A - Ball grid array package with stacked center pad chips and method for manufacturing the same - Google Patents

Ball grid array package with stacked center pad chips and method for manufacturing the same Download PDF

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Publication number
TW200306652A
TW200306652A TW091137746A TW91137746A TW200306652A TW 200306652 A TW200306652 A TW 200306652A TW 091137746 A TW091137746 A TW 091137746A TW 91137746 A TW91137746 A TW 91137746A TW 200306652 A TW200306652 A TW 200306652A
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Taiwan
Prior art keywords
circuit board
package
ball
wafer
substrate
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TW091137746A
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English (en)
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TWI234251B (en
Inventor
Hyung-Gil Baik
Ki-I Moon
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Hynix Semiconductor Inc
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Publication of TW200306652A publication Critical patent/TW200306652A/zh
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Publication of TWI234251B publication Critical patent/TWI234251B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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Description

200306652 五、發明說明（1) 【本發明所屬之技術領域】 本發明係有關本道歸 以上的中心腳位型半：曰：2:言之’為有關將二個 列（fine baU grid 日日片予以疊層而實現微細球格式陣 位晶片的疊；;FBGA)形態之疊層封裝之中心腳 【先前技ς】球格式陣列封裝及其製造方法 在半導體產章φ > 倂，私也m汁 中之對積體電路晶片的封裝（Packaging)枚 π時T、因雷ϋ型化的要求及封裝可靠性而持續地發展著。 板的高性能化之推進，為了在尺寸大小受限 # 土 ρ Α r夕數的半導體封裝而持續地努力著。在此努力 :m案有所謂的"疊層封裝(s —ckage) 使記“量增i將= = :機能的記憶晶片予以疊層 = 2 一個封裝，以使製品的性能及效率性ί f· #彳3 # 1 ΐ a封裝係依欲適用的製品，製造會社等因 丨:二，多樣化。先行技術的疊㈣ package)類型。在第丨圖之疊 ' “ n small outlinii 1 1、1 ?粆枯田而甘士 且層封衣1 〇中，各自的個別封裝 :2係使用内藏有一個一個半導體晶片。的⑽ /a力-on - chlp)(在晶片上的弓丨腳）導線架（lead frame) ;ΐ:ϊ: :ΓΓ4係依枯著帶15枯著在半導體晶片13的上 屬vm6被電性連接。4層的個別封裝11、12係
200306652 五、發明說明（2) 使用另外的連接用引腳i 7而彼此電 腳17接合於各導線架的外部引腳18而=:此時，連接用弓丨 連接端子。 战為疊層封裝1 0的外部 但是’此種類型的疊層封裝u 度尚，對於在要求小型化，薄型化的二面積寬且高 的適用上係有其困難。且因使用導線‘通機器等之系統 不適合於高速元件製品，由於二、1 7、1 8，所以並 導體晶片14為止的路徑係較、=上部封裝12的半 導體晶片13為長之故、所以電氣點至下部封裝"之半 因此’以半導體封裝的表面封裝 ;連接之長度成為最小化以提升電氣特匕，且電 案出在外部連接端子上使用錫球（s〇ider “…，係提 列（ball grid array ;BGA)封裝。基 ^之球格式陣 列封裝之形態在封裝的内部疊層半$ 二糸按照球格式陣 的疊層球格式陣列封裝"係如第2圖所示曰。曰之所谓的”晶片 如第2圖所示般，晶片的疊層球格式陣 模27的内部將個別半導體晶片23，24予以疊声之：係在封. ’且利用印刷電路基板21和錫球28，以取代‘：曰）晶片 有配線22的印刷電路基板21上，使用粘著劑2心莫在形成 導體晶片23，且在下部半導體晶片23上係部：部半 片24。各半導體晶片23、24係依金屬導 =?晶 板的配線22作電性連接’在印刷電路基板21以：：基 錫球28而與配線22作電性連接，成為封裝2。的外^ 第8頁 200306652 —---- 五、發明說明（3) 但是 j 此錄来5
使用所謂的” ^痛型之晶片的疊層球格式陣列封裝2 0係僅能 之丰邕:曰侧腳位（side PW)型半導體晶片π。在如同DRAM 〜卞守脰晶片的士叙 個擔任與外部你私動面（active surface)上，雖然形成多數 作县^曰u 剧入輸出的晶片腳位（chip pad)23a、24a， 侧腳位型丰遂2的部形成有晶片腳位（23a、24a)者係為 、卞等體晶片23、24 〇 腳位普5成ΐ Ϊ來高速元件之落實具有其優點，所以晶片 位型半導體t =明沿著晶片主動面中央所形成之"中心腳 長的問題，所以π 片的疊層困難及金屬導線的長度變 晶片的缺點。曰具有不能使用此類型的中心腳位型半導體 的上部侧”，而產生的類型係因熱應力集中在封裝 因此，在先page)現象。 導體晶片來實現U: ’實際上係僅利用1個中心腳位型」 式陣列封裝；2:3式Λ列封裝。有關中心腳位晶片的球格 ^ ^ # ί ® 2 Si 3^2 t! ^p* "j " ^ 3 〇 # ^ 基板31後，透過冬厘片32的主動面予以粘著在電； 電性連接。半導酽曰3 ::導體晶片32和電路基板31作 護，作成在金屬導線33係受封裝模34所保 球格式陣列封裝2形離形成㈣為外部連接端子之錫球35的 【本發明之内容】 f ^球格式陣列封裝，以及中心
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如以上之說明，疊層封I 五、發明說明（4) 腳位型半導體晶片雖各自具有自身的優點，日 以上3個要求之封裝 構造上疋在同時滿^ 工程安全性士二十+ 傅乂方面或製造成本 方面來考量係具有相當程度的困難。 ’本發明之目的為提供一可產生， 和微細球格式陣列封裝的優點以及中心腳的優點 及其製造方=之中心腳位晶片的疊層球格式陣列封裝 自晶？ ί::二：2之本發明係提供-種，疊層包含有沿名 半導體晶；腳位之二個中心腳位： 腳位晶片的疊層球格式陣列封裝本發明之中心 晶片主動面彼此相互面對般地 導體晶片係以 基板，上下部電路基板係 ^性連接至上下部電路 作電性連接，上部電路基板伏勺二=透過形成在其間的凸塊 板之兩側端部分係露出：封J二；裝模内’下部電路基 在本發明之中心腳位為其特徵。 :電路基板係以具柔軟性之絕緣；；：：：陣：封裳中， ;;:出的兩侧端部分可形成複數個錫ΐ且在：部電路 基板之兩側端部分接合印 且在下部電 部面可形成複數個錫球。又，2，，在印刷電路基板之 成。 下部電路基板係可以導線架 又，本發明係提供一種，疊層包含右、VL夂 中央所形成的複數晶片腳位 _ ’口各自晶片主動 、 之一個中心腳位型半導體晶片 200306652 五、發明說明（5) 以實現微細球 係具有：使晶 晶片各自枯著 數個晶片腳位 凸塊而被電性 以及，上部電 兩側端部分露 構成。 又，本發 板帶片之步驟 以一定間隔形 的圖案形成， 伸至該下部電 接腳位形成有 粘著步驟 於該電路基板 依金屬導 複數個基板腳 電性連接 土下部電路基 作電性連接； 格式陣列 片主動面 至上下部 各自電性 連接般地 路基板為 出於封裝 明之製造 ，該上下 成，基板 且形成多 路基板之 凸塊； ，係該複 帶片之各 線將露出 位的步驟 步驟，係 板彼此粘 =裝之製造方法。本發明之製造方法 二彼此相互面對般地將複數個半導體 ，路基板之步驟；透過金屬導線將複 連接至上下部電路基板之步驟；透過 使上下部電路基板彼此接合之步驟； ^含在封裝模内，且下部電路基板在 莫的下#側般地形成封裝模等步驟所 f法係包含有.提供一上下部電路基 部電路基板帶片係，各個介層孔和窗 腳位、配線、以及連接腳位係以一定 ;個上下部電路基板，而該配線係延 "層孔内部，且形成球陸，且在該連 數個晶片腳位透過該窗被露出般地， 電路基板钻著該半導體晶片· 之複數個晶片腳位予以電性連接至該 =半導體晶片彼此相互面對般地使該 者’且依該凸塊將該上下部電路基板 形成步驟，係透過該介層孔按壓該下部電敗盆λ -Ss彳之該玉求^ 陸，而延伸至該下部電路基板的介層孔内之配線朝下 般地使該球陸露出以形成封褒模； ~
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五、發明說明（6) 在該球陸形成複數個錫 由該電路基板帶片 個【上以及 、此時，形成封裝模之= 以分離的步驟。 模製裝置的鑄孔内般地，；；=’使該各自的電路基板位在 上下部鑄模所構成之模製電路基板帶片提供於以 球陸抵接該下部鑄模般^v驟，該下部電路基板的 透過該電路美板嫌M沾入，使形成在該上部鑄模之加壓部、 過該模製農it:: 孔來按壓該球陸之步驟；以及透 其硬；等製樹脂注入該禱孔内，使 、y取邊封1模荨之步驟為較佳。 考針發明的目的和其他特徵以及優點等等係可夾 佳實施例的說明而更明確。 例。二牛地說明本發明之較佳實施 解，係多少將圖味昧从主_成要素中，為了有助於明確理 其實際大小 表示且概略地圖示，並未全部反映 (第1實施例） 於式Γ列圖封係,表示本發明第1實施例之中心腳位晶片的疊層球 型半導體曰：二剖面圖。茶考第4圖，其係將二個中心腳位 1〇〇。 阳片102、104予以疊層以實現微細球格式陣列封裝 t導體晶片1 0 2、1 0 4的晶片腳位1 0 6、1 0 8係沿著晶κ 士 Us:而形▲，二個半導體晶片102、104係以晶片主動面 ^ 目互面對般地各自被粘著在上下部電路基板11 2、
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五、發明說明（7) 122。半導體晶片1〇2、1〇4的晶片腳位1〇6、ι〇8係透過金 導線130而各自被電性連接至上下部電路基板丨丨？ 'Μ?。 此被接合的上下部電路基板丨12、i 22係透過形成在其間的 塊140而被電性連接。上部電路基板112係具有盥半 ，板122係，其兩側端部分被露出於封裝模15()的下部側。在 路出的下部電路基板122上形成複數個錫球16〇以 100的外部連接端子來作用。 裝 …、本貫施例之封裝1 0 0係依如下之方法所製造。由以下所 說明之製造方法可使封裝的構造更加明確。第5圖至第8圖係 表不第4圖所圖示之中心腳位晶片的疊層球格式陣列封 製造方法之工程圖。 首先，如第5圖的剖面圖所示，在上下部電路基板丨丨2、 2 2上枯著各自半導體晶片1 〇 4、1 〇 2之後，與金屬導線1 3 〇連 接。如第6圖之平面圖所示般，上下部電路基板丨丨2、1 22係 各自以電路基板帶片（s t r i p ) i ；[ 〇、1 2 〇形態形成。 “電路基板帶片110、120係，在捲筒（reei)形態的絕緣薄 膜以一定間隔形成介層孔（h 〇 1 e ) 1 1 11 2 1及窗 (wind〇w)ll3、123，基板腳位114、124，配線115、125、 l28 ’連接腳位11 6、126，以及球陸（bal 1 land) 127係一定 圖案形成，以形成各自的電路基板丨丨2、1 2 2。不同於上部電 路基板帶片110，下部電路基板帶片12〇之特徵為，配線128 延伸至介層孔121的内部且球陸127被形成。絕緣薄膜係以具 柔軟性之聚合物（Polymer)材質所成，基板腳位1 14、124，
200306652 五、發明說明（8) 配線1 1 5、125、1 28，連接腳位11 6、126，以及球陸127係以 銅所構成。 在電路基板帶片110、12〇之各電路基板112、i22上粘著 有半導體晶片104、102，各半導體晶片1〇4、1〇2的晶片腳位 1〇β、108係，透過電路基板帶片11〇、ι2〇的窗113、ι23而露 出於外部。露出的晶片腳位1〇6、1〇8係依金屬導線13〇而與 基板腳位1 1 4、1 2 4作電性連接。此外，在第5圖及第6圖並未 圖不’在上下部電路基板112、122之任一單方或兩側的連接 腳位11 6、1 2 6上，形成有使上下部電路基板丨丨2、1 2 2作電性 連接的凸塊（第7圖的1 4 0 )。可在連接腳位丨丨6、j 2 6上鍍錫以 取代凸塊。 然後’如第7圖之剖面圖所示，半導體晶片丨〇 2、1 〇 4係 彼此相互面對般地使上下部電路基板丨丨2、1 22彼此粘著。上 下。卩％路基板1 1 2、1 2 2係，藉由施加熱及壓力而彼此粘接且 依凸塊140作電性連接。第7圖係僅圖式了】個上下部電路基 板112、122，而在第6圖所圖示之電路基板帶片11〇、12〇的 狀態下作粘接為較佳。 赤占著，一邊按壓下部電路基板一邊進行模製工程。如第 8圖所示，彼此粘著的上下部電路基板帶片11〇、12〇係，被 ^於以上下部鑄模220、210所構成的模製裝置内，此時，粘 著有半導體晶片102、104之各自的電路基板丨12、122係，位 在模製裝置之鑄孔（cavity )23〇内。且，由於形成在上部鑄 模220的加壓部222係透過電路基板帶片11〇、12〇的介層孔 111、1 21而按壓下部電路基板丨22之球陸127，所以延伸至下
第14頁 200306652 五、發明說明（9) 部$路基板122的介層孔121内之配線128係成為朝下方彎曲 且球陸1 2 7成為抵接下部鑄模2 1 〇。 入譆種：態7 ’透過注入口（未圖示)將液狀模製樹脂注 内之後使其硬化，則形成如第4圖所示之封裝模 邱側且垃下部产電路基板122之球陸127係露出於封裝模150的下 。f者在露出於外部的球陸127上形成錫球16〇，且由電 =9反/片110、120，將各自複數個個別封裝100作分離。 (弟2實施例） ?圖係表示本發明第2實施例之中心腳位晶片的叠層球 :陣列封裝3 0 0的剖面圖。在第9圖中，與前述第i實施例 相冋之構成要素係使用同一參考符號。參考第9圖，其為使 ^程性優㉟’係使用另外的印刷電路基板17〇，使下部電路 An反。丨ΐ t兩侧端部分接合至印刷電路基板170以形成封裝模 无1 6 〇係形成在取代球陸之印刷電路基板1 7 0的下部 面。 (第3貧施例） ，1 0圖係表示本發明第3實施例之中心腳位晶片的疊層 ^ 。式陣列封裝40 0之剖面圖。在第丨〇圖中，在與前述第1實 相同的構成要素上係使用同—參考符號。依據第1 〇圖， :㊉用導線条1 8 〇來取代以絕緣薄膜所成之下部電路基板， 封裝模150外面之導線架18〇的兩側端部分係，以透 賞（solder paste)l90的方式來取代錫球，而直接接合 炎1部基，5〇〇。外部基板5 0 0係組裝有封裝100、3 00、400 “ 4用之系統基板。使用在第3實施例之導線架1 $ 〇係，與半
第15頁 200306652 五、發明說明（ίο) 導體晶片102連結的部分 —~ 【發明之效果】 ⑪乍在上成型（up-set)加工 由以上所作說明可了 球格式陣列封裝係，可由本發明之中心腳位晶片的疊層 現晶片疊層球格式陣列封事 腳位型半導體晶片以具體實 本發明之封装係在單: 以上的疊層封裝，可產φ f裝内可使記憶容量增大為2倍 腳位型半導體晶片的全部j憂:球格式陣列封裝之優點及中心 又，因為封裝内部的半導曰、 成，所以可使溫度變化所造忐：為以上下對稱構造所形 特別是在第i實施例的封;裝/曲現象成為最小化， 導體晶片，所以具之=球的上侧不存在有半 α ^ ,、另物11接合之可靠性優越的優點。 以锡玫模製工程，且同時彎曲下部電路基板，所 以錫球之形成工程可容易實現，且在將上下部電路基板作電 't生連接時，透過形成在電路基板的凸塊，以熱壓搾方式使其 粘著，所以可確保充分的可靠性。 、 本說明書及圖面上係對本發明之最佳實施例加以揭示， 即便使用了多個特定用語，其只不過是使用了容易說明本發 明之技術内容且為有助益理解發明之一般意思，並非想對本 發明之範圍作限定。很明顯的，除在此所揭示之實施例以 外，對於在本發明之技術領域所屬之具有一般知識者，係可 依據本發明的技術思想而實施其他變形例。
200306652
圖式簡單說明 ^ 1圖為先行技術之一疊層封裝例之剖面圖。 第2圖為先行技術之晶片的疊層球格 圖。 千〜封裝的剖面 的球格式陣列封裝的 第3圖為先行技術之中心腳位晶片 剖面圖。 第4圖為本發明第1實 陣列封裝的剖面圖v 第5圖係第4圖所示之中心腳位晶片的疊層珑炊成 =製造方法之工程圖，係表示在上下部電； +導體晶片之後，以導線連結後之狀態的剖面圖。 自 壯第6圖係第4圖所示之中心腳位晶片的疊層球袼 農的製造方法之工程圖，係本實施例之製造方法所使卜 下電路基板帶片的概略平面圖。 第7圖係第4圖所示之中心腳位晶片的疊層球格式陣 參:的製造方法之工程圖，係表示上下部電路基板狀 .¾的剖面圖。 狀 第8圖係第4圖所示之中心腳位晶片的疊層球格式陣列封 裝的製造方法之工程圖，係表示一邊按壓下部電路基板一邊 進行模製工程的狀態之概略剖面圖。 第9圖為本發明第2實施例之中心腳位晶片的疊層球袼 陣列封裝的剖面圖。 曰 $ 、 第1 0圖為本發明第3實施例之中心腳位晶片的疊層球格 式陣列封裝的剖面圖。 ^
第17頁 200306652 圖式簡單說明 【符號說明 10 13 15 20 2 2 25 27 30 32 33 35 100 106 4 0 0 :玉电士々 23 26 28 31 32a 34 102 曰y 格式陣 晶片腳仇 列封裝 111、 k 1 2 1 :介層孑匕 110 〜120 : 電路基板帶片 113、 ' 123 :窗 112 、122 : 電路基板 115， 、125 ' 128 ·•配線 114 、124 : 基板腳位 127 球陸 116 、126 : 連接腳位 140 凸塊 130 •金屬導線 160 錫球 150 :封裝模 180 導線架 170 :基板 222 加壓部 210 ^ 22 0 ： 鑄模 500 外部基板 230 :鑄孔 疊層封裳 半導體晶片 粘著劑 疊層球格式陣列封 配線 乂 粘著劑 封裝模 球格式陣列封裝 半導體晶片 金屬導線 封裝模 ' 300 〜108 11、1 2 :個別封裝 14、1 7、1 8 :導線架 1 6 ··金屬導線 21 :印刷電路基板 24 :半導體晶片 金屬導線 錫球 電路基板 :晶片腳位 封裝模 、1 〇 4 :半導體晶片
第18頁

Claims (1)

  1. 200306652 六、申請專利範圍 1、一種中心腳位晶片的疊層球格式陣列封 包含有沿各自晶片主動面中央所形成的複數晶1糸疊層 中心腳位型半導體晶片，以實現微細球袼 之二個 徵為： 千幻封裝，其特 該複數個半導體晶片係，該晶片主動面以彼此 般地各自粘著在上下部電路基板，該複數個晶片 互面對 過金屬導線各自被電性連接在該上下部電路基板，透 電路基板係彼此相互接合，且透過其間所形成的凸=^下部 性連接，該上部電路基板係包含在封裝模内，該下破電 板之兩侧端部分係露出於該封裝模的下部側。 —路基 陣列V#如申Λ專利範圍第1項之中心腳位晶片的疊層埭格气 車歹丨封裝，其中，該下部電路基板係以具柔式 所構成者。 十平人丨王乏、、、邑緣薄膜 3、如申請專利範圍第2項之中心腳位晶片 :列封裝’其中，在該下部電路基板之露出的兩侧；=式 係’形成有複數個錫球。 而分 陣列V/申Λ專利範圍第2項之中心腳位晶片的疊層球袼式 、裝，/、中，该下部電路基板之兩側端部分係與印^ 路基板接合。 、1刹電 陣列5封、，，申Λ專利範圍第4項之中心腳位晶“疊層球格式 個錫球:巾，在的刷f路基板的下部面係形成有複數 κ 6、如申請專利範圍第2項之中心腳位晶片的疊層琰 陣列圭+ # 均％ ί谷式 '丁展’其中，該下部電路基板係以導線架所構成者。
    第19頁 200306652 六、申請專利範圍 7、* 一種中心腳位晶片的叠層純炊& 法，係叠層包含有沿各自晶片主動陣列封裝的製造方 之二個中心腳位型半導體晶片而製造微细晶片腳位 其特徵為具有： &、、、田球格式陣列封裝， 該晶片主動面係彼此相互面對舯 叔數個晶片腳位各自電性連接兮 钇金屬導線將該 透過凸塊而可電性連接般地將該：下部板之步驟； :驟；該上部電路基板係包含於封裝模内，合的 板係在兩側端的部分露出於該封裝模 忒下。卩電路基 裝模之步驟。 、的下°卩側般地形成該封 ^ 種中心腳位晶片的叠層跋；I：夂土 法，係疊層包含有沿各自晶片主動面。式:車列封裝之製造方 片腳位之二個中心腳位型半導體 數個晶 封裝’其特徵為包含有： a而I造微細球格式陣列 提供一上下部電路基板帶片之步驟 ^ 帶片係’各個介層孔和窗以一定間隔：nr部電路基板 線、以及連接腳位係以一定的圖案 4 ’基板腳位、配 :電路基板’而該配線係延伸至該；二電上下 且形成球陸’且在該連接腳 板之"層孔内 粘著步驟，係該複數個晶片， 於該；路基板帶片之各電路基板枯著；出般地， 依金屬導線將露出之複數個晶片 - 複數個基板腳位的步驟； 部位予以電性連接至該
    第20頁 200306652 六、申請專利範圍 _ 、電性連接步驟，係該半導體晶片彼此相 上下部電路基板彼此粘著，且依該凸塊將該 、：般地使該 作電性連接； 〜 下部電路基板 形成步驟，係透過該介層孔按壓該下部 陸，而延伸至該下部電路基板的介層孔内之:板之該球 般地使該球陸露出以形成封裝模； 、、泉朝下方彎曲 在該球陸形成複數個錫球之步驟；以及 由該電路基板帶片將各自的個別封裝 9、如申請專利範圍第8項之中心腳位曰刀的步驟。 的電路基板位在模製裝置的鑄孔内般地D.使該 :基板帶片提供於以上下部鑄模所構 下部電 該上邻：』 接該下部鑄模般地，使形“ σ卩綸模之加壓部透過該電路基板帶片的入s t使形成在 球陸之步驟；以及透過該模製裝、"孔來按壓該 y風邊对表模的步驟所構成。
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