TW432562B - Stacked chip package device using flip chip technology - Google Patents
Stacked chip package device using flip chip technology Download PDFInfo
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- TW432562B TW432562B TW89100695A TW89100695A TW432562B TW 432562 B TW432562 B TW 432562B TW 89100695 A TW89100695 A TW 89100695A TW 89100695 A TW89100695 A TW 89100695A TW 432562 B TW432562 B TW 432562B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Abstract
Description
鼷4325ο 2 五'發明說明（1) 發明領域： 本發明係有關於一種半導體晶片封裝構造，特別有關 於一種利用覆晶技術之晶片堆叠封裝體（stacked chip package device) 〇 先前技術： 隨著更輕更複雜電子裝置需求的日趨強烈，晶片的速 度及複雜性相對越來越高，因此需要更高之封裝效率 (packaging efficiency)。 習用堆疊封裝技術利用三度空間堆疊技術以將兩個以 上之晶片封裝於一單一封裝體中。堆叠封裝技術提供一有 效方法以增加動態隨機存取記憶體（DRAM)之記憶容量。 19 94年7月26日頒予歐古奇等人（(^11(；1^61：.&1.)之美 國專利第5, 33 2, 9 22號「多晶片半導體封裝裝置」，揭示 一 L0C堆疊式半導體封裝裝置。如第一圖所示，兩半導體 晶片’即下晶片1及上晶片2係呈相互面對面配置，導線架 之，聊3及4係由聚醯亞胺（Poly imide)膠帶5及6分別黏著 ;BB片表面β下晶片1及上晶片2之晶片焊塾分別以導線8 及7電性連接至對應之導線架之内腳。下晶片1，上晶片 2 ’腳3及4與導線8及7則由一樹脂封裝體9包覆保護。然 而’下晶片1及上晶片2間須具有足夠之空間，以防止導線 7及8相接觸產生短路。此一限制使其無法有效減少封裝半 導體裝置之厚度β 1998月8日頒予安等人（An et.al.)之美國專利第5, 8〇4, 874號「具有複數個L0C型態半導體晶X之堆疊式晶片鼷 4325ο 2 Five 'Description of the Invention (1) Field of the Invention: The present invention relates to a semiconductor chip package structure, and more particularly to a stacked chip package device using chip-on-chip technology. The demand for lighter and more complex electronic devices is increasing, and the speed and complexity of chips are relatively higher and higher, so higher packaging efficiency is required. Conventional stacked packaging technology uses three-dimensional space stacking technology to package two or more wafers in a single package. Stacked package technology provides an effective method to increase the memory capacity of dynamic random access memory (DRAM). 19 U.S. Patent No. 5, 33 2, 9 22 "(^ 11 (; 1 ^ 61:. &Amp; 1.)" "Multi-chip Semiconductor Packaging Device" issued on July 26, 1994, disclosed A L0C stacked semiconductor packaging device. As shown in the first figure, the two semiconductor wafers, namely the lower wafer 1 and the upper wafer 2 are arranged face to face, and the lead frame, chat 3 and 4 are made of polyimide (Poly imide ) Adhesive tapes 5 and 6 are respectively adhered; the wafer pads of the lower wafer 1 and the upper wafer 2 on the surface of the BB sheet are electrically connected to the corresponding inner legs of the lead frame with wires 8 and 7 respectively. 3 and 4 and wires 8 and 7 are covered and protected by a resin package 9. However, there must be sufficient space between the lower chip 1 and the upper chip 2 to prevent the short circuit between the wires 7 and 8. This limitation makes It cannot effectively reduce the thickness of a packaged semiconductor device. Β, US Patent No. 5,804,874 issued to An et.al. on August 8, 1998, "A stack with a plurality of L0C type semiconductor crystals X Chip
五、發明說明（2) 封裝裝置」，其揭示另一改良LOC型態之堆疊封裝半導體-裝置，可減少堆疊式晶片半導體封裝裝置之厚度並防止導 線間相接觸產生短路。如第二圖所示，該堆疊式晶片封裝 半導體裝置包含一上晶片1〇具有複數個晶片焊墊12位於該 上sh片10之上表面中央區域、一上導線架2〇之内腳21延伸 於上晶片10之上表面並由膠帶3〇黏著固定，内腳21藉由導 線40與相對應之晶片焊墊12電性連接、一下晶片5〇具有複 數個晶片焊墊52位於該下晶片50之上表面中央區域、一下 導線架60之内腳61延伸於下晶片50之上表面並由膠帶70黏 著固定’内腳61藉由導線80與相對應之晶片焊墊52電性連 接’下導線架60之外腳62延伸至封裝體外可與外界電路電 性連接。上導線架20之外端内腳22直接與下導線架60之内 脚61頂面接觸，俾使上晶片1〇及上導線架2〇與下晶片50及 下導線架60相互電性連接β —絕緣黏膠層90置於上晶片10 與下導線架60之内腳61間。 與美國專利第5，3 3 2 , 9 2 2號相比較，雖然美國專利第5， 804, 874號已大幅減少封裝半導體裴置之厚度，並使導線 架不須多次彎折而簡化封裝製程，但由於其係以線銲 (wire bonding)的方式連接晶片以及導線架，所以其仍然 無法有效降低封裝體之厚度。此外，美國專利第 5,804, 874號之堆疊式晶片封裝裝置仍需至少兩導線架以 將兩個以上之晶片封裝於一單一封裝體中，由於至少需使 用兩導線架所以會有因連接點增加而產生高頻雜訊問題。 發明概要：5. Description of the invention (2) Packaging device ", which reveals another stacked package semiconductor-device with an improved LOC type, which can reduce the thickness of the stacked chip semiconductor packaging device and prevent short circuits caused by contact between the conductors. As shown in the second figure, the stacked chip package semiconductor device includes an upper wafer 10 having a plurality of wafer pads 12 located in a central region above the upper surface of the upper wafer 10, and an inner leg 21 of an upper lead frame 20 extending. It is fixed on the upper surface of the upper wafer 10 with adhesive tape 30. The inner leg 21 is electrically connected to the corresponding wafer pad 12 through a wire 40. The lower wafer 50 has a plurality of wafer pads 52 on the lower wafer 50. In the central area of the upper surface, the inner leg 61 of the lower lead frame 60 extends on the upper surface of the lower chip 50 and is fixed by an adhesive tape 70. The inner leg 61 is electrically connected to the corresponding chip pad 52 through the wire 80. The lower wire The outer legs 62 of the frame 60 extend outside the package body and can be electrically connected to external circuits. The inner leg 22 at the outer end of the upper lead frame 20 directly contacts the top surface of the inner leg 61 of the lower lead frame 60, so that the upper chip 10 and the upper lead frame 20 are electrically connected to the lower chip 50 and the lower lead frame 60. β -The insulating adhesive layer 90 is placed between the upper chip 10 and the inner leg 61 of the lower lead frame 60. Compared with U.S. Patent No. 5, 3 3, 2 and 9 2 2, although U.S. Patent No. 5,804, 874 has greatly reduced the thickness of the packaged semiconductors, and has simplified the packaging without the need to bend the lead frame multiple times. Manufacturing process, but because it is connected to the chip and the lead frame by wire bonding, it still cannot effectively reduce the thickness of the package. In addition, the stacked chip packaging device of US Pat. No. 5,804,874 still requires at least two lead frames to package more than two chips in a single package. Since at least two lead frames are used, there will be an increase in connection points The problem of high-frequency noise occurs. Summary of the invention:
_4325βρ_ 五、發明說明（3) 本發明之主要目的係提供一種利用復晶技術之晶月堆 養封裝體’藉此增加該堆疊封裝體之封裝效率，使該堆疊 封裝體之厚度大幅減少。 本發明之次要目的係提供一種利用覆晶技街之晶片堆 叠封裝體’其僅需單一導線架以將兩個以上之晶片封裝於 一單一封裝體中。本發明之再一目的係提供一種利用覆晶 技術之晶片堆疊封裝體’其可增加其電性效能 (electrical performance) 根據本發明之利用覆晶技術之晶片堆疊封裝體主要包 含兩基板用以承載至少兩晶片、一導線架用以將該晶片電 性連接至外界以及一封膠體包覆該基板、晶片以及導線 架。該晶片係分別以覆晶的方式電性連接並且固定於兩基 板。覆晶技術是指直接在晶片表面之辑墊（die pad)上形 成錫球突起（solder bump)用以將其直接固定並電性連接 至一基板。該導線架包含複數條導線具有内腳部分、令間 部分以及外聊部分’該複數條導線之内腳部分係固設於該 兩基板之一。該導線架之複數條導線之内腳部分以及中間 部分係分別以複數條連接線電性連接兩基板，該複數條導 線之外腳部分係自該封膠艘向外延伸用以與外界電性溝 通。 在第一級封裝中，覆晶（flip chip)具有約9〇%之封裝 效率（以1 0 mm見方之晶片討算），而線銲（w i r e b〇nd i ng) 以及捲帶自動焊接（Tape Automated Bonding，TAB)之封 裝效率（以同樣大小晶片計算）則分別只有約7 5 %以及_4325βρ_ V. Description of the invention (3) The main purpose of the present invention is to provide a crystal moon stacking package using multi-crystal technology, thereby increasing the packaging efficiency of the stacked package, and greatly reducing the thickness of the stacked package. A secondary object of the present invention is to provide a chip stack package using flip chip technology, which requires only a single lead frame to package more than two chips in a single package. Another object of the present invention is to provide a chip stack package using flip-chip technology, which can increase its electrical performance. The chip stack package using flip-chip technology according to the present invention mainly includes two substrates for carrying At least two chips and a lead frame are used to electrically connect the chip to the outside and a gel coats the substrate, the chip and the lead frame. The wafers are electrically connected in a flip-chip manner and fixed to two substrates. The flip-chip technology refers to forming a solder bump directly on a die pad on the surface of a wafer to directly fix and electrically connect it to a substrate. The lead frame includes a plurality of wires having an inner leg portion, a ring portion, and an external chat portion. The inner leg portion of the plurality of wires is fixed to one of the two substrates. The inner leg portion and the middle portion of the plurality of wires of the lead frame are electrically connected to the two substrates by a plurality of connecting wires, respectively. The outer leg portions of the plurality of wires are extended outward from the sealing boat for electrical connection with the outside. communication. In the first-level package, flip chip has a packaging efficiency of about 90% (calculated on a chip of 10 mm square), while wire bonding (wire bonding) and tape auto bonding (tape) Automated Bonding (TAB) package efficiency (calculated with the same size chip) is only about 75% and
笫6頁 "4 325 6 2 五 '發明說明（4) 5 t) %。因此根據本發明之利用覆晶技術之晶片堆疊封裝 體，由於其晶片係利用覆晶的方式安裝於基板，因此可大. 幅增加其封裝效率。此外，根據本發明之晶片堆疊封裝 體，由於其只需要一導線架，所以不會因連接點增加而產 生高頻雜訊問題，因而可增進該封裝體之電性效能。 圖示說明： 為了讓本發明之上述和其他目的、特徵、和優點能更 明顯特徵，下文特舉本發明較佳實施例，並配合所附圖 示，作詳細說明如下。 第1圖：美國專利第5, 33 2, 9 2 2號「多晶片半導體封裝 裝置」之剖面圖； 第2圖：美國專利第5, 804, 874號「具有複數個LOC型 態半導體晶片之堆疊式晶片封裝裝置」之剖面圖； 第 3 圖 * 本 發 明第 一較 佳 實 施 例 之剖 面 圖 t 第 4 圖 本 發 明第 一較 佳 實 施 例 之上 視 圖 9 及 第 5 圖 ： 本 發 明第 二較 佳 實 施 例 之上 視 圖 〇 圖 號說明： 1 下 曰曰 片 2 上 晶 片 3 内 腳 4 内 腳 5 膠 帶 6 膠 帶 7 導 線 8 導 線 9 樹 脂 封 裝體 10 上 晶 片 12 晶 片 焊 墊 20 上 導 線 架 21 内 腳 30 膠 帶 40 導 線 50 下 a a曰 片 52 晶 片 焊 墊 60 下 導 線 架 61 内 腳 62 外 腳 70 膠 帶笫 Page 6 " 4 325 6 2 Five 'Explanation of invention (4) 5 t)%. Therefore, according to the present invention, the wafer stack package using the flip-chip technology, because the wafer is mounted on the substrate by a flip-chip method, can greatly increase its packaging efficiency. In addition, according to the chip stack package of the present invention, since it only requires a lead frame, high-frequency noise problems do not occur due to an increase in connection points, and thus the electrical performance of the package can be improved. Illustrative illustration: In order to make the above and other objects, features, and advantages of the present invention more obvious, the following describes the preferred embodiments of the present invention and the accompanying drawings in detail, as follows. Figure 1: Sectional view of US Patent No. 5,33 2, 9 2 2 "Multi-chip Semiconductor Packaging Device"; Figure 2: US Patent No. 5,804, 874 "Semiconductor Chip with Multiple LOC Type Semiconductor Chips" A cross-sectional view of a "stacked chip packaging device"; Fig. 3 * A cross-sectional view of the first preferred embodiment of the present invention t Fig. 4 A top view of the first preferred embodiment of the present invention 9 and 5: Top view of the preferred embodiment 0 Description of drawing number: 1 Next chip 2 Upper chip 3 Inner pin 4 Inner pin 5 Tape 6 Tape 7 Lead 8 Lead 9 Resin package 10 Upper chip 12 Wafer pad 20 Upper lead frame 21 Inner foot 30 Tape 40 Lead 50 Lower aa chip 52 Wafer pad 60 Lower lead frame 61 Inner foot 62 Outer foot 70 Tape
_4 32 5 6 2 五、發明說明 (5) 80 導 線 90 絕 緣 黏 膠層 100 晶 片堆 疊 封 裝體 110 基 板 112 基 板銲 塾 120 基 板 122 基 板 銲 墊 1 30 晶 片 140 晶 片 150 導 線 架 152 導 線 152b 中 間 部 分 152a 内 腳 部 分 152c 外 腳部 分 154 絕 緣 膠 層 156 金 線 158 金 線 170 封 膠 體 180 膠 層 200 晶 片堆 疊 封 裝體 230 晶 片 240 晶 月 232 晶 片 242 晶 片 發明 說明： 第三圖係為根據本發明第一較佳實施例之一晶片堆疊 封裝體100 ，其主要包含兩基板110、120 ，一對晶片130、 140、一導線架150以及一封膠體170。該兩基板110、120 係分別設有複數個基板銲墊1 12、122。該對晶片130、140 之正面係分別設有複數個錫球突起（未示於圖中），該對 晶片1 30、1 40之背面係以一膠層1 80彼此固定。該對晶片 130、140之複數個錫球突起係用以將其分別固定於基板 110、120並且形成電性連接。該導線架150係包含複數條 導線1 5 2具有内腳部分1 5 2 a、中間部分1 5 2 b以及外腳部分 1 5 2 c。該複數條導線1 5 2之内腳部分1 5 2 a係以一絕緣膠層 154固設於該基板110。該每一條導線152之内腳部分152a 係以一連接線例如金線1 5 6電性連接至相對應之基板銲墊 1 1 2。該每一條導線1 5 2之中間部分1 5 2 b係以一連接線例如 金線1 5 8電性連接至相對應之基板銲墊1 2 2。該封膠體1 7 0_4 32 5 6 2 V. Description of the invention (5) 80 Lead wire 90 Insulating adhesive layer 100 Wafer stack package 110 Substrate 112 Substrate soldering pad 120 Substrate 122 Substrate pad 1 30 Wafer 140 Wafer 150 Lead frame 152 Lead 152b Middle portion 152a Inner leg portion 152c Outer leg portion 154 Insulating adhesive layer 156 Gold wire 158 Gold wire 170 Sealing gel 180 Adhesive layer 200 Wafer stack package 230 Wafer 240 Crystal moon 232 Wafer 242 Wafer Description of the invention: The third figure is the first according to the present invention A chip stack package 100 according to a preferred embodiment mainly includes two substrates 110 and 120, a pair of chips 130 and 140, a lead frame 150, and a gel 170. The two substrates 110 and 120 are respectively provided with a plurality of substrate pads 12 and 122. The front surfaces of the pair of wafers 130 and 140 are respectively provided with a plurality of solder ball protrusions (not shown in the figure), and the back surfaces of the pair of wafers 130 and 140 are fixed to each other with an adhesive layer 180. The plurality of solder ball protrusions of the pair of wafers 130 and 140 are used to fix the solder balls to the substrates 110 and 120 and form electrical connections. The lead frame 150 includes a plurality of wires 1 5 2 having an inner leg portion 1 5 2 a, a middle portion 1 5 2 b, and an outer leg portion 1 5 2 c. The inner leg portions 15 2 a of the plurality of wires 15 are fixed to the substrate 110 with an insulating adhesive layer 154. The inner leg portion 152a of each of the wires 152 is electrically connected to the corresponding substrate pad 1 1 2 by a connecting wire such as a gold wire 1 5 6. The middle portion 15 2 b of each of the wires 1 5 2 is electrically connected to the corresponding substrate pads 1 2 2 by a connecting wire such as a gold wire 1 5 8. The sealing colloid 1 7 0
^4 325 6 2_ 五、發明說明（6) 係包覆該兩基板1 1 0、1 2 0，晶片1 3 0、1 4 0，複數條金線 156、158以及導線架150，其中該導線架150之複數條導線 1 52之外腳部分1 52c係自該封膠體1 70向外延伸用以與外界 電性溝通。 請再參照第三圖，該基板11 0、1 2 0 —般係以不導電材 質[例如FR-4玻璃環氧樹脂（glass-epoxy)或聚醯亞胺 (polyimide)]製成β該導線架150較佳係由銅、鐵、鎳或 其合金製成。此外該複數條導線152可以鍵上一層高導電 物質例如銀、鋼、金或鈀。該絕緣膠層1 5 4係為一熱可塑 (thermoplastic)膠層，其可事先藉由一熱壓機（heater press)加熱加壓後，再黏貼至該複數條導線152之内腳部 分152a以及該基板110之表面。該封膠體170之材質係為絕 緣材料，較佳之塑料（molding compound)為Hitachi Chemical Company 提供之 CEL-9 20 0 XU 塑料。 請再參照第三圖，該晶片堆叠封裝體100進行封膠製程 時，其厚度容許值（thickness tolerance)必須控制的很 小以免該晶片1 3 0、1 4 0受上下模具之擠壓而導致晶片破裂 (die crack)。因此該膠層180較佳係以彈性材料 (elastomeric material)例如矽樹脂橡膠（silicone rubber)製成。該彈性材料可先以液態的形式塗佈，再固 化成一彈性層。此外，該膠層1 8 0亦可使用具彈性之絕緣 薄膜。藉此，該膠層1 8 〇可增加晶片1 3 0、1 4 0間之厚度容 許值’以減少由於厚度不相容所產生之應力。因此，該彈 性層可增加該封裝體1〇〇之厚度容許值而提高封裝良率並^ 4 325 6 2_ 5. The description of the invention (6) is to cover the two substrates 1 1 0, 1 2 0, wafers 1 3 0, 1 4 0, a plurality of gold wires 156, 158, and a lead frame 150, where the wires The outer leg portions 1 52c of the plurality of wires 1 52 of the frame 150 extend outward from the sealing gel 1 70 for electrical communication with the outside world. Please refer to the third figure again. The substrate 110, 120 is generally made of non-conductive material [such as FR-4 glass-epoxy or polyimide]. The frame 150 is preferably made of copper, iron, nickel, or an alloy thereof. In addition, the plurality of wires 152 may be bonded to a layer of a highly conductive material such as silver, steel, gold, or palladium. The insulating adhesive layer 15 is a thermoplastic adhesive layer, which can be heated and pressurized by a heat press in advance, and then adhered to the inner leg portions 152a of the plurality of wires 152 and A surface of the substrate 110. The material of the sealing compound 170 is an insulating material, and a preferred molding compound is CEL-9 20 0 XU plastic provided by Hitachi Chemical Company. Please refer to the third figure again. When the wafer stack package 100 is subjected to the sealing process, its thickness tolerance must be controlled to be small to prevent the wafers 130 and 140 from being squeezed by the upper and lower molds. The die cracked. Therefore, the adhesive layer 180 is preferably made of an elastic material such as silicone rubber. The elastic material may be applied in a liquid form and then cured into an elastic layer. In addition, the adhesive layer 180 can also use an elastic insulating film. Thereby, the adhesive layer 180 can increase the thickness allowance value 'between the wafer 130 and 140 to reduce the stress caused by the thickness incompatibility. Therefore, the elastic layer can increase the thickness allowable value of the package body 1000 to improve the package yield and
43256 2 五、發明說明（7) 且降低生產成本。 該晶片130、140之複數個錫球突起可利用習知的C4 (Controlled Collapse Chip Connection)製程形成—（A) 在晶片之晶片銲墊（die pad)上形成一錫球突起下冶金 (under bump metallurgy, UBM) °(B)在UBM 上形成錫球突 起。該基板110、120於該對晶片130、140之安裝區域係設 有複數個錫球銲墊（未示於圖中），且其係分別電性連接 至相對應之基板銲墊112、122。該晶片130、140之複數個 錫球突起係先分別對正置於該基板110，120上的錫球銲 墊，然後進行迴銲製程例如紅外線輻射迴銲（I R reflow)。因此，該晶片130、140之複數個錫球突起不僅 將其分別固定於基板110、120，並且提供導電以及導熱的 途徑。該晶片與基板間較佳具有一底層填料（underfill) 用以密封該晶片與基板間之空隙。該底層填料可以減輕在 錫球連接上的應力（其係由於該晶片與基板間的熱膨脹係 數不一所致）。 第四圖係為根據本發明第一較佳實施例之一晶片堆疊 封裝體100之上視圖，其包含一對互相堆疊之晶片130、 140 〇 第五圖係為根據本發明第二較佳實施例之一晶片堆疊 封裝體2 0 〇之上視圖。該晶片堆疊封裝體2 〇 〇除了以兩對互 相堆疊之晶片230、240以及232、242取代該對互相堆疊之 晶片1 3 0、1 4 0外，其係相同於第三圓以及第四圖中晶片堆 疊封裝體1 0 0。43256 2 V. Description of invention (7) and reduce production cost. The solder bumps of the wafers 130 and 140 can be formed by the conventional C4 (Controlled Collapse Chip Connection) process— (A) forming an under bump on the die pad of the wafer. metallurgy, UBM) ° (B) forms solder ball protrusions on UBM. The substrates 110 and 120 are provided with a plurality of solder ball pads (not shown) in the mounting area of the pair of wafers 130 and 140, and they are electrically connected to the corresponding substrate pads 112 and 122, respectively. The plurality of solder ball protrusions of the wafers 130 and 140 are respectively aligned with the solder ball pads which are respectively disposed on the substrates 110 and 120, and then a reflow process such as infrared reflow (IR reflow) is performed. Therefore, the plurality of solder ball protrusions of the wafers 130 and 140 not only fix them to the substrates 110 and 120, respectively, but also provide a path for conducting electricity and heat. An underfill is preferably provided between the wafer and the substrate to seal a gap between the wafer and the substrate. The underfill can reduce the stress on the solder ball connection (this is due to the different coefficients of thermal expansion between the wafer and the substrate). The fourth diagram is a top view of a chip stack package 100 according to one of the first preferred embodiments of the present invention, which includes a pair of stacked wafers 130, 140. The fifth diagram is a second preferred embodiment according to the present invention. One example is a top view of a wafer stack package 200. The wafer stack package 2000 is the same as the third circle and the fourth figure except that the pair of stacked wafers 230, 240 and 232, 242 replaces the pair of stacked wafers 130, 140. Medium chip stack package 100.
醪4 3 2 5 6 2 五、發明說明（8) 根據本發明之利用覆晶技術之晶片堆疊封裝體，由於 其晶片係利用覆晶的方式安裝於基板，因此可大幅減小其 厚度而增加其封裝效率。此外，根據本發明之晶片堆疊封 裝體，由於其只需要一導線架，所以可避免因導線架間連 接點增加而產生高頻雜訊問題，因而可增進該封裝體之電 性效能。另外，本發明再兩堆疊晶片間加入一具彈性之膠 層，其不僅提供固定該兩晶片之功能，更能藉以吸收整體 架構在厚度上的變異，而大幅提昇本發明之可行性。本發 明可以在相同大小之封裝體内置入最多之晶片而充分將現 有封裝膠體發揮至最大效用。 雖然本發明已以前述較佳實施例揭示，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作各種之更動與修改。例如根據本發明之 晶片堆疊封裝體雖以封裝一對或兩對互相堆疊之晶片作為 較佳實施例，但根據本發明之晶片堆查封裝體係可用以封 裝兩對以上互相堆疊之晶片。因此本發明之保護範圍當視 後附之申請專利範圍所界定者為準。醪 4 3 2 5 6 2 V. Description of the invention (8) According to the present invention, the wafer stack package using flip chip technology is mounted on the substrate by flip chip, so its thickness can be greatly reduced and increased. Its packaging efficiency. In addition, according to the wafer stack package of the present invention, since only one lead frame is required, the problem of high-frequency noise caused by the increase in connection points between the lead frames can be avoided, and the electrical performance of the package can be improved. In addition, the present invention adds a flexible adhesive layer between the two stacked wafers, which not only provides the function of fixing the two wafers, but also can absorb variations in the thickness of the overall structure, thereby greatly improving the feasibility of the present invention. According to the present invention, the largest number of chips can be built into a package of the same size to fully utilize the existing packaging colloid to the maximum effect. Although the present invention has been disclosed by the aforementioned preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. For example, although the wafer stack package according to the present invention takes one or two pairs of stacked wafers as a preferred embodiment, the wafer stack inspection packaging system according to the present invention can be used to package two or more pairs of stacked wafers. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.
j谉Aj 谉 A
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| US7919873B2 (en) | 2001-09-17 | 2011-04-05 | Megica Corporation | Structure of high performance combo chip and processing method |
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| US7919873B2 (en) | 2001-09-17 | 2011-04-05 | Megica Corporation | Structure of high performance combo chip and processing method |
| US7960212B2 (en) | 2001-09-17 | 2011-06-14 | Megica Corporation | Structure of high performance combo chip and processing method |
| US7960842B2 (en) | 2001-09-17 | 2011-06-14 | Megica Corporation | Structure of high performance combo chip and processing method |
| US8124446B2 (en) | 2001-09-17 | 2012-02-28 | Megica Corporation | Structure of high performance combo chip and processing method |
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