TW200302569A - Transistor and semiconductor memory using the same - Google Patents

Transistor and semiconductor memory using the same Download PDF

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Publication number
TW200302569A
TW200302569A TW091133883A TW91133883A TW200302569A TW 200302569 A TW200302569 A TW 200302569A TW 091133883 A TW091133883 A TW 091133883A TW 91133883 A TW91133883 A TW 91133883A TW 200302569 A TW200302569 A TW 200302569A
Authority
TW
Taiwan
Prior art keywords
source
gate
insulating film
floating gate
transistor
Prior art date
Application number
TW091133883A
Other languages
English (en)
Chinese (zh)
Inventor
Takashi Miida
Original Assignee
Innotech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innotech Corp filed Critical Innotech Corp
Publication of TW200302569A publication Critical patent/TW200302569A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/687—Floating-gate IGFETs having more than two programming levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0491—Virtual ground arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
TW091133883A 2001-11-22 2002-11-20 Transistor and semiconductor memory using the same TW200302569A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001358308 2001-11-22
JP2002169749 2002-06-11
JP2002322905A JP2004072060A (ja) 2001-11-22 2002-11-06 トランジスタとそれを用いた半導体メモリ、およびトランジスタの駆動方法

Publications (1)

Publication Number Publication Date
TW200302569A true TW200302569A (en) 2003-08-01

Family

ID=27347866

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091133883A TW200302569A (en) 2001-11-22 2002-11-20 Transistor and semiconductor memory using the same

Country Status (7)

Country Link
US (1) US6944062B2 (enExample)
EP (1) EP1458032A1 (enExample)
JP (1) JP2004072060A (enExample)
KR (1) KR20040068147A (enExample)
CN (1) CN1589501A (enExample)
TW (1) TW200302569A (enExample)
WO (1) WO2003044869A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004072060A (ja) 2001-11-22 2004-03-04 Innotech Corp トランジスタとそれを用いた半導体メモリ、およびトランジスタの駆動方法
JP4472934B2 (ja) * 2002-03-27 2010-06-02 イノテック株式会社 半導体装置および半導体メモリ
US6795348B2 (en) * 2002-05-29 2004-09-21 Micron Technology, Inc. Method and apparatus for erasing flash memory
TWI233691B (en) * 2004-05-12 2005-06-01 Powerchip Semiconductor Corp Nonvolatile memory, nonvolatile memory array and manufacturing method thereof
JP4683457B2 (ja) * 2004-07-09 2011-05-18 ルネサスエレクトロニクス株式会社 不揮発性メモリ、データプロセッサ及びｉｃカード用マイクロコンピュータ
JP4632713B2 (ja) * 2004-07-28 2011-02-16 イノテック株式会社 並列データ書き込み方法
JP4628757B2 (ja) * 2004-11-26 2011-02-09 イノテック株式会社 半導体記憶装置
US8595459B2 (en) * 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
KR100776901B1 (ko) 2005-04-11 2007-11-19 주식회사 하이닉스반도체 Ｎａｎｄ형 플래쉬 메모리 소자의 리커버리 방법
US8599614B2 (en) 2009-04-30 2013-12-03 Powerchip Corporation Programming method for NAND flash memory device to reduce electrons in channels
CN103094283B (zh) * 2011-10-27 2015-11-25 中芯国际集成电路制造(上海)有限公司 8-bit半导体存储单元、制作方法及其存储单元阵列
TWI874071B (zh) * 2023-12-26 2025-02-21 華邦電子股份有限公司 半導體記憶體裝置及其形成方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02122674A (ja) * 1988-11-01 1990-05-10 Fujitsu Ltd 不揮発性半導体記憶装置
JPH03249811A (ja) * 1990-02-27 1991-11-07 Mitsubishi Electric Corp 受光増幅器
US5379255A (en) * 1992-12-14 1995-01-03 Texas Instruments Incorporated Three dimensional famos memory devices and methods of fabricating
US5973356A (en) * 1997-07-08 1999-10-26 Micron Technology, Inc. Ultra high density flash memory
JP3025485B2 (ja) * 1997-12-09 2000-03-27 松下電器産業株式会社 不揮発性半導体記憶装置およびその製造方法
US6051860A (en) * 1998-01-16 2000-04-18 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit
JP4367979B2 (ja) * 1998-01-27 2009-11-18 正気 小椋 不揮発性半導体記憶装置の製造方法
JP2000082752A (ja) 1998-09-07 2000-03-21 Matsushita Electronics Industry Corp 半導体記憶装置の書き込み及び消去方法
JP3973819B2 (ja) 1999-03-08 2007-09-12 株式会社東芝 半導体記憶装置およびその製造方法
US6534816B1 (en) * 1999-03-24 2003-03-18 John M. Caywood Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell
JP2001057394A (ja) * 1999-06-09 2001-02-27 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置及びその製造方法
JP4397491B2 (ja) 1999-11-30 2010-01-13 財団法人国際科学振興財団 １１１面方位を表面に有するシリコンを用いた半導体装置およびその形成方法
US6538925B2 (en) 2000-11-09 2003-03-25 Innotech Corporation Semiconductor memory device, method of manufacturing the same and method of driving the same
JP3283872B1 (ja) 2001-04-12 2002-05-20 イノテック株式会社 半導体記憶装置、その製造方法及び半導体記憶装置の駆動方法
JP3249811B1 (ja) 2000-11-09 2002-01-21 イノテック株式会社 半導体記憶装置、その製造方法及び半導体記憶装置の駆動方法
JP3249812B1 (ja) 2001-05-14 2002-01-21 イノテック株式会社 半導体記憶装置及びその製造方法
JP4191975B2 (ja) * 2001-11-01 2008-12-03 イノテック株式会社 トランジスタとそれを用いた半導体メモリ、およびトランジスタの製造方法
JP2003224215A (ja) * 2001-11-22 2003-08-08 Innotech Corp トランジスタとそれを用いた半導体メモリ、およびトランジスタの駆動方法
JP2004072060A (ja) 2001-11-22 2004-03-04 Innotech Corp トランジスタとそれを用いた半導体メモリ、およびトランジスタの駆動方法
US6861315B1 (en) * 2003-08-14 2005-03-01 Silicon Storage Technology, Inc. Method of manufacturing an array of bi-directional nonvolatile memory cells

Also Published As

Publication number Publication date
CN1589501A (zh) 2005-03-02
EP1458032A1 (en) 2004-09-15
JP2004072060A (ja) 2004-03-04
WO2003044869A1 (en) 2003-05-30
US20040196685A1 (en) 2004-10-07
US6944062B2 (en) 2005-09-13
KR20040068147A (ko) 2004-07-30

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