TNSN87107A1 - Procede et dispositif pour executer deux sequences d'instructions dans un ordre determine a l'avance - Google Patents

Procede et dispositif pour executer deux sequences d'instructions dans un ordre determine a l'avance

Info

Publication number
TNSN87107A1
TNSN87107A1 TNTNSN87107A TNSN87107A TNSN87107A1 TN SN87107 A1 TNSN87107 A1 TN SN87107A1 TN TNSN87107 A TNTNSN87107 A TN TNSN87107A TN SN87107 A TNSN87107 A TN SN87107A TN SN87107 A1 TNSN87107 A1 TN SN87107A1
Authority
TN
Tunisia
Prior art keywords
sequence
sequences
address
instructions
intermediately
Prior art date
Application number
TNTNSN87107A
Other languages
English (en)
Inventor
Bjorn Rutger Erik Jonsson
Sten Edvard Johnson
Lars-Orjan Kling
Oleg Avsan
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of TNSN87107A1 publication Critical patent/TNSN87107A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Communication Control (AREA)
  • Complex Calculations (AREA)
  • Electrotherapy Devices (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Image Input (AREA)
  • Multi Processors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

L'INVENTION CONCERNE L'INFORMATIQUE, ON AMELIORE LA CAPACITE DE TRAITEMENT D'UN SYSTEME INFORMATIQUE, EN CE QUI CONCERNE L'EXECUTION DE DEUX SEQUENCES D'INSTRUCTIONS DANS UN ORDRE DETERMINE A LAVANCE, EN PROCEDANT DE LA MANIERE SUIVANTE: ON COMMENCE PAR EXECUTER LES DEUX SEQUENCES (5) EN PARALLELE. ON ENREGISTRE DE FACON INTERMEDIAIRE UNE ADRESSE CONTENUE DANS UNE INSTRUCTION DE LECTURE ASSOCIEE A LA SECONDE SEQUENCE, SI CETTE ADRESSE N'A PAS ETE SELECTIONNEE PRECEDEMENT CONJOINTEMENT A UNE INSTRUCTION D'ECRITURE ASSOCIEE A LA SECONDE SEQUENCE (41, 42). ON COMPARE L'ADRESSE ENREGISTREE DE FACON INTERMEDIAIRE AVEC L'ADRESSE D'ECRITURE DE LA PREMIERE SEQUENCE, ET ON FAIT REDEMARRER L'EXECUTION DE LA PREMIERE SEQUENCE (56, 60, 61, 62) EN CAS DE COINCIDENCE ENTRE LES ADRESSES. APPLICATIONS AUX SYSTEMES MULTIPROCESSEURS
TNTNSN87107A 1986-10-03 1987-09-30 Procede et dispositif pour executer deux sequences d'instructions dans un ordre determine a l'avance TNSN87107A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE8604222A SE454920B (sv) 1986-10-03 1986-10-03 Sett och anordning for att i en pa forhand avgjord ordningsfoljd exekvera tva instruktionssekvenser medelst separatminnen

Publications (1)

Publication Number Publication Date
TNSN87107A1 true TNSN87107A1 (fr) 1990-01-01

Family

ID=20365823

Family Applications (1)

Application Number Title Priority Date Filing Date
TNTNSN87107A TNSN87107A1 (fr) 1986-10-03 1987-09-30 Procede et dispositif pour executer deux sequences d'instructions dans un ordre determine a l'avance

Country Status (17)

Country Link
US (1) US4985826A (fr)
EP (1) EP0287600B1 (fr)
JP (1) JPH01500936A (fr)
KR (1) KR920006768B1 (fr)
AU (1) AU589047B2 (fr)
BR (1) BR8707481A (fr)
DE (1) DE3774119D1 (fr)
DK (1) DK168415B1 (fr)
ES (1) ES2005371A6 (fr)
FI (1) FI93908C (fr)
GR (1) GR871512B (fr)
MX (1) MX168943B (fr)
NO (1) NO173718C (fr)
PT (1) PT85810B (fr)
SE (1) SE454920B (fr)
TN (1) TNSN87107A1 (fr)
WO (1) WO1988002514A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE454921B (sv) * 1986-10-03 1988-06-06 Ellemtel Utvecklings Ab Sett och anordning for att i en pa forhand avgjord ordningsfoljd exekvera tva instuktionssekvenser
US5280615A (en) * 1990-03-23 1994-01-18 Unisys Corporation Out of order job processing method and apparatus
JP2786574B2 (ja) * 1992-05-06 1998-08-13 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュータ・システムにおける順不同ロード動作の性能を改善する方法と装置
GB9305263D0 (en) * 1993-03-15 1993-05-05 Univ Westminster Parrallel computation
JPH07334372A (ja) * 1993-12-24 1995-12-22 Seiko Epson Corp エミュレートシステム及びエミュレート方法
JP4160705B2 (ja) * 1999-10-15 2008-10-08 富士通株式会社 プロセッサ及びプロセッサシステム
FI114428B (fi) * 2001-12-13 2004-10-15 Nokia Corp Menetelmä ja järjestelmä laskuridatan keräämiseksi verkkoelementissä
US20060036826A1 (en) * 2004-07-30 2006-02-16 International Business Machines Corporation System, method and storage medium for providing a bus speed multiplier

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1218656A (en) * 1968-03-27 1971-01-06 Int Computers Ltd Improvements in or relating to computer system
US3787673A (en) * 1972-04-28 1974-01-22 Texas Instruments Inc Pipelined high speed arithmetic unit
GB1441458A (en) * 1972-06-28 1976-06-30 Texas Instruments Inc Stored programme data processing for parallel processing of programme segment
IT991096B (it) * 1973-07-10 1975-07-30 Honeywell Inf Systems Calcolatore elettronico con reti funzionali indipendenti per l esecuzione simultanea di opera zioni diverse sugli stessi dati
SE378690B (fr) * 1973-12-13 1975-09-08 Ellemtel Utvecklings Ab
SE387763B (sv) * 1975-10-23 1976-09-13 Ellemtel Utvecklings Ab Anordning vid ett datorminne for att mojliggora en successiv forflyttning under drift av ett ledigt minnesfelt
JPS57162165A (en) * 1981-03-30 1982-10-05 Fanuc Ltd Re-editing system for storage area
US4466061A (en) * 1982-06-08 1984-08-14 Burroughs Corporation Concurrent processing elements for using dependency free code
JPS5932045A (ja) * 1982-08-16 1984-02-21 Hitachi Ltd 情報処理装置
US4720779A (en) * 1984-06-28 1988-01-19 Burroughs Corporation Stored logic program scanner for a data processor having internal plural data and instruction streams
US4703481A (en) * 1985-08-16 1987-10-27 Hewlett-Packard Company Method and apparatus for fault recovery within a computing system

Also Published As

Publication number Publication date
FI93908B (sv) 1995-02-28
EP0287600A1 (fr) 1988-10-26
PT85810B (pt) 1993-08-31
FI882469A0 (fi) 1988-05-25
AU8037087A (en) 1988-04-21
DK300888D0 (da) 1988-06-02
FI882469A (fi) 1988-05-25
DE3774119D1 (de) 1991-11-28
GR871512B (en) 1987-10-01
NO173718B (no) 1993-10-11
PT85810A (pt) 1988-11-30
AU589047B2 (en) 1989-09-28
ES2005371A6 (es) 1989-03-01
EP0287600B1 (fr) 1991-10-23
BR8707481A (pt) 1988-12-06
MX168943B (es) 1993-06-15
DK300888A (da) 1988-06-02
SE454920B (sv) 1988-06-06
KR920006768B1 (ko) 1992-08-17
DK168415B1 (da) 1994-03-21
NO173718C (no) 1994-01-19
FI93908C (fi) 1995-06-12
NO882196L (no) 1988-05-19
SE8604222L (sv) 1988-04-04
US4985826A (en) 1991-01-15
WO1988002514A1 (fr) 1988-04-07
JPH01500936A (ja) 1989-03-30
NO882196D0 (no) 1988-05-19
SE8604222D0 (sv) 1986-10-03
KR880701912A (ko) 1988-11-07

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