FR2413751A1 - Procede de traitement d'une memoire tampon - Google Patents

Procede de traitement d'une memoire tampon

Info

Publication number
FR2413751A1
FR2413751A1 FR7836527A FR7836527A FR2413751A1 FR 2413751 A1 FR2413751 A1 FR 2413751A1 FR 7836527 A FR7836527 A FR 7836527A FR 7836527 A FR7836527 A FR 7836527A FR 2413751 A1 FR2413751 A1 FR 2413751A1
Authority
FR
France
Prior art keywords
buffer memory
processing
information
transfer
blocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7836527A
Other languages
English (en)
Other versions
FR2413751B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of FR2413751A1 publication Critical patent/FR2413751A1/fr
Application granted granted Critical
Publication of FR2413751B1 publication Critical patent/FR2413751B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)

Abstract

L'INVENTION CONCERNE L'INFORMATIQUE. UNE MEMOIRE TAMPON INTERCALEE ENTRE UN PROCESSEUR ET UNE MEMOIRE CENTRALE ENREGISTRE DES DONNEES QUI SONT ORGANISEES EN BLOCS D'INFORMATION B, B, ETC. POUR ACCROITRE L'EFFICACITE DU TRANSFERT DE L'INFORMATION ENTRE LA MEMOIRE TAMPON ET LA MEMOIRE CENTRALE, CE TRANSFERT S'EFFECTUE PAR MODULES D'INFORMATION, FORMES PAR DEUX BLOCS, OU DAVANTAGE. APPLICATION AUX ORDINATEURS.
FR7836527A 1977-12-27 1978-12-27 Procede de traitement d'une memoire tampon Expired FR2413751B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15822377A JPS5489444A (en) 1977-12-27 1977-12-27 Associative memory processing system

Publications (2)

Publication Number Publication Date
FR2413751A1 true FR2413751A1 (fr) 1979-07-27
FR2413751B1 FR2413751B1 (fr) 1985-09-13

Family

ID=15666965

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7836527A Expired FR2413751B1 (fr) 1977-12-27 1978-12-27 Procede de traitement d'une memoire tampon

Country Status (5)

Country Link
US (1) US4244033A (fr)
JP (1) JPS5489444A (fr)
DE (1) DE2856133C2 (fr)
FR (1) FR2413751B1 (fr)
GB (1) GB2011137B (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0024721A2 (fr) * 1979-08-28 1981-03-11 Siemens Aktiengesellschaft Dispositif de mémoire
EP0090575A2 (fr) * 1982-03-25 1983-10-05 Western Electric Company, Incorporated Système de mémoire

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5567987A (en) * 1978-11-09 1980-05-22 Hitachi Ltd Memory control system
JPS57167188A (en) * 1981-04-06 1982-10-14 Nippon Telegr & Teleph Corp <Ntt> Buffer memory controlling system
US4491932A (en) * 1981-10-01 1985-01-01 Yeda Research & Development Co. Ltd. Associative processor particularly useful for tomographic image reconstruction
JPS618798A (ja) * 1984-06-21 1986-01-16 Nec Corp 不揮発性記憶装置
US4656626A (en) * 1984-12-14 1987-04-07 Itt Corporation Apparatus and method for providing dynamically assigned switch paths
JPS61148551A (ja) * 1984-12-24 1986-07-07 Hitachi Ltd アドレス変換方式
JPH0810553B2 (ja) * 1986-06-13 1996-01-31 松下電器産業株式会社 記憶回路
US4914582A (en) * 1986-06-27 1990-04-03 Hewlett-Packard Company Cache tag lookaside
EP0259967B1 (fr) * 1986-08-01 1994-03-23 Fujitsu Limited Mémoire répertoire
US5317708A (en) * 1990-06-29 1994-05-31 Digital Equipment Corporation Apparatus and method for an improved content addressable memory
US5279564A (en) * 1992-09-11 1994-01-18 Edward Weck Incorporated Cannula retention device
US5717895A (en) * 1994-12-01 1998-02-10 Cray Research, Inc. Associative scalar data cache with write-through capabilities for a vector processor
JP2710580B2 (ja) * 1995-04-14 1998-02-10 甲府日本電気株式会社 キャッシュメモリ装置
US6199140B1 (en) * 1997-10-30 2001-03-06 Netlogic Microsystems, Inc. Multiport content addressable memory device and timing signals
US6148364A (en) * 1997-12-30 2000-11-14 Netlogic Microsystems, Inc. Method and apparatus for cascading content addressable memory devices
US6219748B1 (en) 1998-05-11 2001-04-17 Netlogic Microsystems, Inc. Method and apparatus for implementing a learn instruction in a content addressable memory device
US6240485B1 (en) 1998-05-11 2001-05-29 Netlogic Microsystems, Inc. Method and apparatus for implementing a learn instruction in a depth cascaded content addressable memory system
US6381673B1 (en) 1998-07-06 2002-04-30 Netlogic Microsystems, Inc. Method and apparatus for performing a read next highest priority match instruction in a content addressable memory device
US6892272B1 (en) 1999-02-23 2005-05-10 Netlogic Microsystems, Inc. Method and apparatus for determining a longest prefix match in a content addressable memory device
US6460112B1 (en) 1999-02-23 2002-10-01 Netlogic Microsystems, Llc Method and apparatus for determining a longest prefix match in a content addressable memory device
US6574702B2 (en) 1999-02-23 2003-06-03 Netlogic Microsystems, Inc. Method and apparatus for determining an exact match in a content addressable memory device
US6539455B1 (en) 1999-02-23 2003-03-25 Netlogic Microsystems, Inc. Method and apparatus for determining an exact match in a ternary content addressable memory device
US6499081B1 (en) 1999-02-23 2002-12-24 Netlogic Microsystems, Inc. Method and apparatus for determining a longest prefix match in a segmented content addressable memory device
US6137707A (en) * 1999-03-26 2000-10-24 Netlogic Microsystems Method and apparatus for simultaneously performing a plurality of compare operations in content addressable memory device
US6944709B2 (en) * 1999-09-23 2005-09-13 Netlogic Microsystems, Inc. Content addressable memory with block-programmable mask write mode, word width and priority
US7487200B1 (en) 1999-09-23 2009-02-03 Netlogic Microsystems, Inc. Method and apparatus for performing priority encoding in a segmented classification system
US6687785B1 (en) 2000-06-08 2004-02-03 Netlogic Microsystems, Inc. Method and apparatus for re-assigning priority in a partitioned content addressable memory device
US6542391B2 (en) 2000-06-08 2003-04-01 Netlogic Microsystems, Inc. Content addressable memory with configurable class-based storage partition
US6751701B1 (en) 2000-06-14 2004-06-15 Netlogic Microsystems, Inc. Method and apparatus for detecting a multiple match in an intra-row configurable CAM system
US6934795B2 (en) * 1999-09-23 2005-08-23 Netlogic Microsystems, Inc. Content addressable memory with programmable word width and programmable priority
US6567340B1 (en) 1999-09-23 2003-05-20 Netlogic Microsystems, Inc. Memory storage cell based array of counters
US6795892B1 (en) 2000-06-14 2004-09-21 Netlogic Microsystems, Inc. Method and apparatus for determining a match address in an intra-row configurable cam device
US6324087B1 (en) 2000-06-08 2001-11-27 Netlogic Microsystems, Inc. Method and apparatus for partitioning a content addressable memory device
US6763425B1 (en) 2000-06-08 2004-07-13 Netlogic Microsystems, Inc. Method and apparatus for address translation in a partitioned content addressable memory device
US6757779B1 (en) 1999-09-23 2004-06-29 Netlogic Microsystems, Inc. Content addressable memory with selectable mask write mode
US6799243B1 (en) 2000-06-14 2004-09-28 Netlogic Microsystems, Inc. Method and apparatus for detecting a match in an intra-row configurable cam system
US7272027B2 (en) * 1999-09-23 2007-09-18 Netlogic Microsystems, Inc. Priority circuit for content addressable memory
US7143231B1 (en) 1999-09-23 2006-11-28 Netlogic Microsystems, Inc. Method and apparatus for performing packet classification for policy-based packet routing
US7110407B1 (en) 1999-09-23 2006-09-19 Netlogic Microsystems, Inc. Method and apparatus for performing priority encoding in a segmented classification system using enable signals
US7185141B1 (en) 2001-12-27 2007-02-27 Netlogic Microsystems, Inc. Apparatus and method for associating information values with portions of a content addressable memory (CAM) device
US7401180B1 (en) 2001-12-27 2008-07-15 Netlogic Microsystems, Inc. Content addressable memory (CAM) device having selectable access and method therefor
US7301961B1 (en) 2001-12-27 2007-11-27 Cypress Semiconductor Corportion Method and apparatus for configuring signal lines according to idle codes
US6754766B1 (en) * 2002-02-14 2004-06-22 Altera Corporation Emulation of content-addressable memories
JP5231867B2 (ja) * 2008-05-23 2013-07-10 株式会社東芝 キャッシュメモリシステム
US7848129B1 (en) 2008-11-20 2010-12-07 Netlogic Microsystems, Inc. Dynamically partitioned CAM array
US7920399B1 (en) 2010-10-21 2011-04-05 Netlogic Microsystems, Inc. Low power content addressable memory device having selectable cascaded array segments
US8467213B1 (en) 2011-03-22 2013-06-18 Netlogic Microsystems, Inc. Power limiting in a content search system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2151425A5 (fr) * 1971-08-25 1973-04-13 Ibm
FR2290710A1 (fr) * 1974-11-11 1976-06-04 Sperry Rand Corp Unite d'interface de memoire

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588829A (en) * 1968-11-14 1971-06-28 Ibm Integrated memory system with block transfer to a buffer store
BE788028A (fr) * 1971-08-25 1973-02-26 Siemens Ag Memoire associative
US4063081A (en) * 1976-06-08 1977-12-13 Honeywell Computer apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2151425A5 (fr) * 1971-08-25 1973-04-13 Ibm
FR2290710A1 (fr) * 1974-11-11 1976-06-04 Sperry Rand Corp Unite d'interface de memoire

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/71 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0024721A2 (fr) * 1979-08-28 1981-03-11 Siemens Aktiengesellschaft Dispositif de mémoire
EP0024721A3 (fr) * 1979-08-28 1982-09-01 Siemens Aktiengesellschaft Dispositif de mémoire
EP0090575A2 (fr) * 1982-03-25 1983-10-05 Western Electric Company, Incorporated Système de mémoire
EP0090575A3 (en) * 1982-03-25 1985-05-22 Western Electric Company, Incorporated Memory systems

Also Published As

Publication number Publication date
US4244033A (en) 1981-01-06
JPS5712222B2 (fr) 1982-03-09
DE2856133A1 (de) 1979-06-28
JPS5489444A (en) 1979-07-16
DE2856133C2 (de) 1987-02-12
GB2011137B (en) 1982-05-12
FR2413751B1 (fr) 1985-09-13
GB2011137A (en) 1979-07-04

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Legal Events

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