JPS56156979A - Information processor - Google Patents

Information processor

Info

Publication number
JPS56156979A
JPS56156979A JP5753180A JP5753180A JPS56156979A JP S56156979 A JPS56156979 A JP S56156979A JP 5753180 A JP5753180 A JP 5753180A JP 5753180 A JP5753180 A JP 5753180A JP S56156979 A JPS56156979 A JP S56156979A
Authority
JP
Japan
Prior art keywords
memory
cash
address
bus
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5753180A
Other languages
Japanese (ja)
Inventor
Keizo Aoyanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5753180A priority Critical patent/JPS56156979A/en
Publication of JPS56156979A publication Critical patent/JPS56156979A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To reduce address transfer times and to improve the use efficiency of bus by performing the information transfer between a cash memory and a main memory by way of a common bus time-dividedly, and forming the relative addresses in blocks on both memory side. CONSTITUTION:At the cash miss, the output gate 34 of a cash memory 26 opens and an address is applied via a common bus 27 to the memory address register 36 of a main memory control part 23. Thence, the addresses excluding low-order bits are set in the register 36 via the control circuit 39 of the circuit 23, the lowest-order bit address is preset in a counter 37, and the information is read out from a main memory 22, and is written into a cash memory part 33 via a read register 38 and the bus 27. At the same time, the counter 37 is stepped by the circuit 39, and the continuous block information of the memory 22 are read out. Hence, the information transfer is processed time-dividedly by way of the common bus.
JP5753180A 1980-04-30 1980-04-30 Information processor Pending JPS56156979A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5753180A JPS56156979A (en) 1980-04-30 1980-04-30 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5753180A JPS56156979A (en) 1980-04-30 1980-04-30 Information processor

Publications (1)

Publication Number Publication Date
JPS56156979A true JPS56156979A (en) 1981-12-03

Family

ID=13058322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5753180A Pending JPS56156979A (en) 1980-04-30 1980-04-30 Information processor

Country Status (1)

Country Link
JP (1) JPS56156979A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6167157A (en) * 1984-09-07 1986-04-07 Toshiba Corp Microprocessor
JPS633352A (en) * 1986-06-23 1988-01-08 Digital:Kk Cache memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6167157A (en) * 1984-09-07 1986-04-07 Toshiba Corp Microprocessor
JPS633352A (en) * 1986-06-23 1988-01-08 Digital:Kk Cache memory device
JPH0511332B2 (en) * 1986-06-23 1993-02-15 Digital Kk

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