JPH0511332B2 - - Google Patents

Description

1. A cache memory device comprising: a sub-control unit 4 for outputting data;

2 Each main control section includes a bidirectional gate section 47 that controls data input/output to and from the memory sections 23 and 24;
48, first control units 41 and 42 that detect a cache and generate a read gate signal, second control units 45 and 46 that send read/write control signals to the memory units 23 and 24, and
The third control section 43, 44 generates a write gate signal during the data write cycle of the CPU 1, and the read gate signal and the write gate signal are connected to the gate sections 47, 48 to output data from the memory sections 23, 24. 2. The cache memory device according to claim 1, wherein the gate is opened in the direction of reading data or in the direction of writing data into the memory sections 23, 24.

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to an information processing device equipped with a cache memory, and in particular to a method for receiving data with matching bus widths from bus ports of various bit widths provided in a storage device and sending it to a CPU. The present invention relates to a cache memory device that can perform the following functions.

(Prior Art) Conventionally, in order to improve the processing speed of information processing equipment, a memory device with a small capacity but fast operating speed has been installed between the CPU 1 and the main storage device 7, as shown in FIG. A storage memory device 10 is arranged.

It is advantageous to provide the main memory device 7 with bus ports having a plurality of bit widths, such as 8 bits, 16 bits, and 32 bits, from the viewpoint of cost performance and miniaturization of the device. For this reason,
The CPU 1 is a CPU that has a so-called dynamic bus sizing function (for example, a 32-bit A microprocessor, Motorola's MC68020) is available.

For example, as shown in FIG.
In a system in which a cache memory device 10 is connected to a bus 8 having a width of 32 bits, the data that the CPU 1 attempts to read from the main memory device 7 has a width of 32 bits. If you are
The main memory device 7 creates a bus size signal indicating that the data is 32 bits wide and sends it to the CPU 1.
send to Based on this signal, the CPU 1 adapts the bus width to 32 bits and then receives data from the main memory 7.

However, the 32-bit data you are trying to read also exists in the cache memory (cache cache).
If so, the control circuit installed in the cache memory device 10 detects this, and the data is transferred from the cache memory.
Data is sent to CPU1.

Therefore, if the cache continues without a cache error, the CPU can continue executing the program by referring only to the cache memory, allowing extremely high-speed access.

(Problem to be Solved) However, in the conventional system shown in FIG. 6, the 16-bit data is always read from the main memory device 7, so the effect of the cache memory device 10 cannot be obtained, and the overall hit rate decreases. There was a problem with low performance.
This problem can be solved by equipping the 16-bit wide bus 80 with a cache memory device, but
As a result, the number of cache memory chips increases and cost performance decreases. or,
In addition to the individual control circuits for each cache memory, hardware (control circuits) are required to collectively control all the cache memories, resulting in a problem that the apparatus becomes complicated.

(Means for Solving the Problems) The present invention provides a cache memory device that is compatible with a dynamic bus sizing type CPU, has a high hit rate, and has a simple circuit configuration. The purpose is to provide.

In the cache memory device according to the present invention,
The cache memory 2 is composed of a plurality of memory sections 23 and 24 from which data can be read and written individually.

A plurality of data lines led from the storage device 7 are connected to each memory section 23 of the cache memory 2,
Each data line group is divided into a plurality of data line groups corresponding to the port size of 24, and each data line group is connected to a corresponding memory section 23, 24, and a plurality of data lines led from the storage device 7 are connected to each data line group. The address line is for read/write for cache memory 2.
The memory units are connected so that the required number of memory units can be selected according to the bus width of the data to be written.

The control circuit 3 also has a main control section for each memory section that detects the presence or absence of a cache in each memory section 23, 24 during a read cycle of the CPU 1, and controls reading/writing of data to each memory section 23, 24. , the data to be read from the cache memory is connected to the bus based on the hit signal output from each main control unit during cache.
It is composed of a sub-control unit 4 that creates a size signal and sends it to the CPU 1.

(Operation) When the storage device is accessed by CPU1,
The control circuit 3 receives the read/write output from the CPU 1.
Based on the write control signal WR, it is detected whether the command to the storage device is to read or write data.

When the command is to read data, the control circuit 3
Each main control section detects whether each memory section of the cache memory 2 has been hit or not, and when a hit has occurred, creates a hit signal representing this. Therefore,
By detecting whether a hit signal is output from any of the main control units, the bit width of the data can be determined.

In the case of a cache, the sub-control unit 4 creates a bus size signal representing the bit width of data based on the hit signal created by the main controller,
Send to CPU1. Based on this signal, the CPU 1 learns the bit width of the data to be read and adapts the bus width to the data to be received.

Further, under the control of the main control section, data for a hit area is simultaneously sent from a plurality of memory sections to the CPU 1, thereby shortening the access time.

On the other hand, if a cache error occurs, the data is written to the cache memory 2 at the same time as the data is read from the storage device. At this time, if the data has a small bit width, the first area is written to a small number of memory sections,
If the bit width is large, many or all memory sections are written.

Also, during the write cycle of the CPU 1, the cache memory 2 is corrected according to a predetermined rewriting method set in the main control section.

(Effects of the Invention) In the cache memory device according to the present invention, the entire size of the cache memory composed of a plurality of memory sections is set to a size that can store data of the maximum word length. , data for all word lengths to be processed can be stored in a single cache memory. Further, the CPU 1 can perform a dynamic bus sizing function based on a bus size signal sent from the cache memory device at the time of cache transfer. Therefore, compared to the conventional device shown in FIG. 6, for example, without increasing the number of memory chips,
The hit rate can be dramatically improved.

However, as is clear from the above description of the configuration and operation, the control circuit 3 can be configured with a simple hardware circuit consisting of, for example, logic circuit elements, so the circuit configuration of the device can be configured using multiple circuits of different sizes. It is much simpler than devices equipped with cache memory.

(Embodiment) As shown in FIG. 1, the system configuration of the information processing device according to the present invention includes a cache memory 2 interposed between a CPU 1 and a main storage device 7, which is controlled by a control circuit 3. This is what I did.

CPU 1 is a 32-bit microprocessor "MC68020" from Motorola.

The main memory device 7 has two types of ports, one 16-bit wide and the other 32-bit wide.
They are connected by a bus 5 consisting of data lines, and control lines 6, 60, 61, etc., which will be described later.
Note that each piece of data stored in the main storage device 7 is assigned a so-called byte address.

The cache memory 2 consists of a low memory section 23 and a high memory section 24, and is
It is linked to the CPU 1 and the main storage device 7. Both memory sections 23 and 24 each have a data storage section composed of a static RAM with a width of 16 bits, and are connected to buses 51 and 24 consisting of address lines and data lines.
52 and to the control circuit 3 via control lines 62 and 63.

Figure 2 shows the cache memory 2 and control circuit 3.
The control circuit 3 is constituted by a simple hardware circuit consisting of logic circuit elements and the like as shown in the figure.

Both memory sections 23 and 24 of the cache memory 2
, a management information column 21 in which a flag V for determining the validity of data is stored, an address tag column 20 in which the upper bit part T of the logical address is stored,
Data column 22 where data D in the storage device is stored
It is composed of:

Both memory sections 23 and 24 of the cache memory 2
are referenced by lower address lines A2 to Ak55, excluding A1, among address lines A1 to AN, respectively. Further, one of the low-order memory section 23 and the high-order memory section 24 is selected depending on the binary state of the address line A1 connected to the read/write control signal input port WE of each memory section 23, 24. That is, since each data in the main memory device 7 is assigned a byte address as described above, when A1="H", the lower memory section 23 is selected and becomes operational, and when A1="L" In this case, the high-order memory section 24 is selected and becomes operational.

Upper address lines Ak+1 to AN56 are connected to the tag fields 20 of both memory sections 23 and 24, respectively. In addition, among the 32 data lines, the lower data line D is in the data field 22 of the lower memory section 23.
0 to D15 are connected, and the remaining upper data lines D16 to D are connected to the data field 22 of the higher memory section 24.
31 is connected. Note that in a system in which 16-bit data is always sent via the upper data lines D16 to D31, a circuit is required to distribute the data to the lower memory section 23 and the higher memory section 24, but this circuit is Line A1 etc. can be easily configured as input information,
Further, since this is well known, illustration and description thereof will be omitted.

In the management information column 21 of both memory sections 23 and 24,
A violation signal ER is stored that takes a value of "L" when an abnormality occurs in the bus cycle being executed.

The control circuit 3 includes a low-level main control section and a high-level main control section that directly control the low-level and high-level memory sections 23 and 24 of the cache memory 2, respectively. Each main control section includes bidirectional gate sections 47 and 48 that control the input and output of data to and from the data column 22 of the memory sections 23 and 24, and bidirectional gate sections 47 and 48 that detect a cache and generate a hit signal HT, as well as a read gate signal.
First control units 41 and 42 output HR, second control units 45 and 46 send read/write control signals to each memory unit 23 and 24, and
It is composed of third control signals 43 and 44 that generate a write gate signal MW during a data write cycle of the CPU 1.

The control circuit 3 also includes a sub-control section 4 that creates bus size signals DSACK0 and DSACK1 based on the read gate signals HR sent from both main control sections and sends them back to both main control sections.

A read/write control signal WR from the CPU is input to the first control units 41 and 42. signal
WR indicates a read cycle when it is "H", and indicates a write cycle when it is "L".

The cache is on the upper address line 56.
, the cache memory 2 and the tag field 20 are detected by a comparator 30 connected to the input terminal. The output signal of the comparator 30 and the valid bit signal from the management information field 21 of the cache memory 2 are input to an AND gate 32, thereby creating a hit signal HT representing a valid hit.

Further, the hit signal HT and the read/write control signal WR are input to a NAND gate 33.
This creates read gate signal HR.

The third control units 43 and 44 receive a hit signal HT, a read/write control signal WR, and a sub-control unit 4 to be described later.
A write gate signal MW for the gate sections 47 and 48 is created by using the bus cycle completion signal CW from the input signal as an input signal. In addition, in the operation of the third control sections 43 and 44, when it is necessary to shift to a cache write operation (cache load), the AND gate 3 is activated.
The output signal L ₀ of the AND gate 35 becomes "H", and when it is necessary to proceed to the cache modification operation (cash modifier), the output signal M ₀ of the AND gate 35 becomes "H".
becomes.

The read gate signal HR and the write gate signal
MW is connected to gate sections 47 and 48 as a control signal, thereby controlling input/output to data column 22 of cache memory 2.

The second control units 45 and 46 control the address line A
1 and a signal M32 indicating whether or not the data is 32 bits, the data read/write mode for the lower memory section 23 and the higher memory section 24 is controlled. Incidentally, the signal M32 can be easily generated, for example, by connecting the upper address line 53a from the main memory device 7 to the address decoder 70 as shown in FIG.

The read gate signal HR from both the first control units 41 and 42 is input to the sub-control unit 4, and the outputs DSACK0 and DSACK of the open collectors 37 and 38 are inputted to the sub-control unit 4.
1 becomes the bus size signal for data to be read from cache memory. That is, DSACK
When 0="H" and DSACK1="L", it indicates that the data bus port size is 16 bits.
When both DSACK0 and DSACK1 are "L", it indicates that the data bus port size is 32 bits.

Furthermore, both signals DSACK0 and DSACK1 are input to the OR gate 31, which generates a signal CW indicating the completion of the bus cycle and sends it back to the third control units 43, 44.

Below, an example of the operation of the control circuit 3 shown in FIG.
The explanation will be based on the flowchart shown in the figure. however,
The control circuit 3 is a hardware circuit, and the flowchart is only used for convenience in explaining the circuit operation, and the order of operations on the flowchart does not represent the actual order of operation of the circuit.

1 During the data read cycle, the read/write control signal WR is set to “H”, thereby causing the control circuit 3 to
It is detected that the command to is to read data (FIG. 4, 9).

Both first control units 41 and 42 check whether the content T (address) of the tag column 20 of the cache memory 2 specified by the address line 55 matches the value of the upper address line 56. is detected by the comparator 30,
The presence or absence of a cache is determined (FIG. 4, 91 and 92).

(1) In the case of a cache, either one or both memory sections 23, 24
If the cache has been cached, the cache read operation is performed as described below.

When both memory units 23 and 24 are hit (FIG. 4, 93) A cache hit is detected in both first control units 41 and 42, and the management information column 2
When the valid bit in 1 is "H", the AND gate 32 outputs a hit signal HT (="H") representing a valid hit.
As a result, the read gate signal HR (="L") is obtained from the NAND gate 33.

The gate signal HR is transmitted to the bidirectional gate section 4
7, 48 and the sub-control unit 4, respectively. As a result, the gate sections 47 and 48 open their gates in the direction of reading data from the cache memory 2.

Further, the sub-control unit 4 generates a bus size signal DSACK0 (=
“L”) and DSACK1 (=“L”) are generated, and these signals are sent to the control lines 60 and 61.
is sent to CPU1 via. (See Figure 1).

Further, the second control units 45 and 46 control the output signal M of the address decoder 70 shown in FIG.
32 (="L") and the output signals MW (="H") of the third control units 43 and 44 shown in FIG. .

As a result, 32
The bit data is passed through data line 54.
Sent to CPU. The CPU 1 adapts the bus width to 32 bits based on the bus size signal from the sub-control unit 4, and accepts the data sent.

When only the low memory section 23 is hit (FIG. 4, 94) A cache hit is detected by the first control section 41 on the low memory section 23 side, and the hit signal HT (="H") and the read gate signal HR (=
"L") is created.

In contrast, the first
In the control unit 42, the NAND gate 33
The output becomes "H" and the gate in the data read direction is closed.

The sub-control unit 4 also outputs a bus size signal.
DSACK0 (=“H”) and DSACK1 (=
These signals are sent to the CPU 1 via control lines 60 and 61.

Further, the second control unit 45 controls the value “H” of the address line A1, the output signal M32 (=“H”) of the address decoder 70 shown in FIG.
And by inputting the output signal MW (="H") of the third control section 43 on the lower side in FIG. 2, the lower memory section 23 is set to the data read mode.

As a result, the 16-bit data stored in the data column 22 of the lower memory section 23 is
It is sent to the CPU via data line 54. The CPU 1 adapts the bus width to 16 bits based on the bus size signal from the sub-control unit 4, and accepts the data sent.

If the request from the CPU 1 is for 32-bit data, after the hit 16-bit data is transferred to the CPU 1, the remaining 16-bit data is read from the main storage device 7.

When only the high-order memory section 24 is hit (FIG. 4, 95) A cache hit is detected by the first control section 42 on the high-order memory section 24 side, and the hit signal HT (="H") and the read gate signal HR (=
"L") is created.

On the other hand, the first
In the control unit 42, the NAND gate 33
The output becomes "H" and the gate in the data read direction is closed.

The sub-control unit 4 also outputs a bus size signal.
DSACK0 (=“H”) and DSACK1 (=
"L"), and these signals are sent to the CPU 1 via control lines 60 and 61.

Furthermore, the second control unit 46 controls the value “L” of the address line A1, the output signal M32 (=“H”) of the address decoder 70 shown in FIG.
By inputting the output signal MW (="H") of the third control section 44 on the upper side in FIG. 2, the high-order memory section 24 is set to the data read mode.

As a result, the 16-bit data stored in the data column 22 of the high-order memory section 24 is
It is sent to the CPU via data line 54. The CPU 1 adapts the bus width to 16 bits based on the bus size signal from the sub-control unit 4, and receives the data sent.

(2) In the case of a cache miss In the case of a cache miss in which the two addresses do not match in either control section, a cache write operation (FIG. 4, 96) is executed.

For example, in a cache write operation of 32-bit data, the output signals MW of the third control sections 43 and 44 on the low-level side and the high-level side both become "L".

As a result, in both gate sections 47 and 48, the gate toward the cache memory 2 is opened, and the data sent from the main storage device via the data line 53 is written to the specified address in the data column 22. At the same time, data sent from the main memory is transferred to the CPU. At this time, the bus size signal DSACK0
and DSACK1 are supplied from the main storage device 7 (see FIG. 1).

Furthermore, in a cache write operation of 16-bit data, data is written to one of the memory sections.

2 During a data write cycle When the command from the CPU 1 is to write data to the main memory device 7, that is, when the read/write control signal WR is “L”, data at the specified write address exists in the cache memory 2. At the same time, data from the CPU is written to the main memory, and at the same time, the cache memory 2 is modified (cache modifier) based on the data (FIG. 4, 97).

That is, similar to the cache write operation described above,
If the data is 32 bits, both memory sections 23 and 2
If the data is 16 bits, the data is written to one memory section.

If the data at the specified write address does not exist in the cache memory 2, the data is written only to the main storage device 7, and the data is not stored in the cache memory 2.
There is no change within.

FIG. 5 compares the data flow in the cache memory device according to the present invention with the conventional device shown in FIG.

In the conventional device, the effect of the cache memory device 10 can be obtained only for 32-bit data, whereas in the device according to the present invention,
The cache memory device 10 also has a 16-bit width bus 80 connecting the CPU 1 and the main memory device 7.
are linked, and the effect of the cache memory device 10 is exhibited not only for 32-bit data but also for 16-bit data. Therefore, the cache memory hit rate doubles.

However, the capacity of the cache memory 2 to be installed in the cache memory device 10 is the same as that installed in the conventional device shown in FIG. 6, and cost performance can be improved.

In the cache memory device described above, the cache memory 2 is formed of a high-speed, small-capacity RAM, and the control circuit 3 is constructed mainly of logic circuit elements. Therefore, processing associated with writing and reading data is performed at extremely high speed, and the performance of the cache memory is fully utilized. However, when the present invention is implemented in a system equipped with a conventional cache memory, there is no need to modify the software (program) at all, and the standard OS can be easily ported.

Note that the configuration of each part of the present invention is not limited to the above embodiments,
Various modifications are possible within the technical scope of the claims.

For example, as shown in FIG. 3, the cache memory 2 includes first to fourth memory sections 25, 26, 27,
It is also possible to configure the main memory 7 with 8 bits, 16 bits and 32 bits.
The present invention can also be implemented in systems equipped with ports of three different bus widths.

Furthermore, the method for rewriting the cache memory is not limited to the one described above, and various known methods can be employed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an information processing apparatus equipped with a cache memory device according to the present invention, FIG. 2 is a circuit diagram of the cache memory device, FIG. 3 is a block diagram showing another embodiment, and FIG. 4 5 is a flowchart explaining the operation of the control circuit, FIG. 5 is a diagram explaining the data flow in the device of FIG. 2, and FIG.
It is an explanatory view of a conventional device corresponding to the figure. 1... CPU, 2... cache memory, 3...
...Control circuit, 7...Main memory, 23...Low memory section, 24...High memory section, 41, 42...
First control unit, 45, 46... Second control unit, 43,
44... Third control section, 47, 48... Gate section.

Claims (1)

[Claims] 1. A CPU 1 capable of changing port size with an external device according to a bus size signal representing the port size of the external device.
In an information processing apparatus, a control circuit 3 and a cache memory 2 whose data reading/writing is controlled by the control circuit are interposed between a storage device 7 accessed by the CPU 1 and a storage device 7 accessed by the CPU 1. The cache memory 2 is composed of a plurality of memory sections 23 and 24, each of which can read/write data individually, and the plurality of data lines led from the storage device 7 are Each memory section 2
It is divided into a plurality of data line groups corresponding to port sizes of 3 and 24, respectively, and each data line group is connected to its corresponding memory section 23 and 24 and led from the storage device 7. The plurality of address lines are connected to the cache memory 2 so that the necessary number of memory sections can be selected according to the bus width of the data to be read/written, and the selected memory section can be accessed. is,
The control circuit 3 reads each memory section 23,
The presence/absence of the cache 24 is detected, and data is read from/to each memory section 23, 24.
A main control unit for each memory unit that controls writing and a bus size signal for data to be read from the cache memory 2 are created based on the hit detection signal output from each main control unit during cache data, and the bus size signal for the data to be read from the cache memory 2 is created.・Send the size signal to CPU1