JPS5619578A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5619578A
JPS5619578A JP9534579A JP9534579A JPS5619578A JP S5619578 A JPS5619578 A JP S5619578A JP 9534579 A JP9534579 A JP 9534579A JP 9534579 A JP9534579 A JP 9534579A JP S5619578 A JPS5619578 A JP S5619578A
Authority
JP
Japan
Prior art keywords
memory
byte
controller
register
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9534579A
Other languages
Japanese (ja)
Inventor
Nobuyuki Baba
Toshio Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9534579A priority Critical patent/JPS5619578A/en
Publication of JPS5619578A publication Critical patent/JPS5619578A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To enable the high speed transfer within memories, by providing the buffer register in the memory controller and connecting between the register and the memory with the bidirectional bus having the same data width.
CONSTITUTION: The buffer register REG2 having the same data width of the memory MS, e.g., 4-byte, is provided in the memory controller MSC and between the memory MS and the register is connected with the bidirectional bus in 4-byte. Further, between the memory MS and the controller MSC, the readout and write-in in each 4-byte are made. Further, the processor CPU is provided with the register REG3 having less data width, e.g., in two-byte and the interval between the memory MS and the controller MCS is connected with the bus in 2-byte. Accordingly, readout and write-in are made in each two-byte unit via the controller MSC between the memory MS and CPU. Thus, without making broad the bus width between the controller and the processor, the data transfer in memories can be speeded up.
COPYRIGHT: (C)1981,JPO&Japio
JP9534579A 1979-07-26 1979-07-26 Information processor Pending JPS5619578A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9534579A JPS5619578A (en) 1979-07-26 1979-07-26 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9534579A JPS5619578A (en) 1979-07-26 1979-07-26 Information processor

Publications (1)

Publication Number Publication Date
JPS5619578A true JPS5619578A (en) 1981-02-24

Family

ID=14135083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9534579A Pending JPS5619578A (en) 1979-07-26 1979-07-26 Information processor

Country Status (1)

Country Link
JP (1) JPS5619578A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60142439A (en) * 1983-12-29 1985-07-27 Fujitsu Ltd Store buffer device
JPS61226881A (en) * 1985-03-30 1986-10-08 Toshiba Corp Image data processor
JPS62112291A (en) * 1985-11-09 1987-05-23 Omron Tateisi Electronics Co Control circuit
JPS633352A (en) * 1986-06-23 1988-01-08 Digital:Kk Cache memory device
JPH03118647A (en) * 1989-10-02 1991-05-21 Shikoku Nippon Denki Software Kk Data transfer system within main storage device of data processor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60142439A (en) * 1983-12-29 1985-07-27 Fujitsu Ltd Store buffer device
JPS61226881A (en) * 1985-03-30 1986-10-08 Toshiba Corp Image data processor
JPS62112291A (en) * 1985-11-09 1987-05-23 Omron Tateisi Electronics Co Control circuit
JPS633352A (en) * 1986-06-23 1988-01-08 Digital:Kk Cache memory device
JPH03118647A (en) * 1989-10-02 1991-05-21 Shikoku Nippon Denki Software Kk Data transfer system within main storage device of data processor

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