SU1569977A1 - Multifunctional counter - Google Patents

Abstract

The invention relates to digital devices, in particular, devices for counting pulses, shifting information and signature-based signal processing. The purpose of the invention — extending the functionality — is achieved by providing a sequential shift mode while simultaneously improving the speed in the signature signal processing mode. The multifunction counter contains the first 1, second 2, third 3, fourth 4 four-bit binary counters connected to obtain a sixteen-bit synchronous counter. In addition, the multifunctional counter contains four elements EXCLUSIVE OR 6, 7, 8, 9, D-flip-flop 5 and buses "data", "tact", "account", "reset 1", "reset 2", "installation" and "output". 1 tab., 1 Il.

Description

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the first 1, the second 2, the third 3, the fourth 4 are four binary binary counters connected to obtain a sixteen-bit synchronous counter. In addition, multi-functional

the counter contains- four elements EXCLUSIVE OR 6, 7, 8, 9, D-flip-flop 5 and tires Data, Beat, Counting, Reset 1, Reset 2, Setup and Exit. 1 tab., 1 Il.

The invention relates to digital devices, in particular, devices for counting information shift pulses and signature processing of signals.

The purpose of the invention is to expand the functionality of the device by providing a sequential shift mode while simultaneously improving performance in the signature-based signal processing mode.

The drawing shows an electrical structural diagram of a multifunctional counter.

The multifunction counter contains the first 1, second 2, third 3, fourth 4 four-bit binary counters connected to obtain a sixteen-bit synchronous counter by connecting the transfer output of the first counter 1 to the first count resolution enable inputs of the second 2, third 3 and fourth 4 counters and to the second the input of the resolution of the second 2 counter, the transfer output of the second 2 and third 3 counters to the second inputs of the resolution resolution of the third 3 and fourth 4 counters, respectively.

In addition, the multifunctional counter contains D-thrunger 5, four elements EXCLUSIVE OR 6-9 and tires Data 10, Tact 11, Score 12, Reset 1 13, Reset 2 14, Setup 15 and Output 16, outputs of bits 1 sixteen-bit counter from the first to the third, the fifth, the sixth, the eighth and the tenth to the fifteenth are connected respectively to the information inputs of bits from the second to the fourth, the sixth, the seventh, the ninth and the eleventh to the sixteenth, the bus Data and outputs of the fourth The seventh, ninth digit of the counter is connected to the first inputs of the corresponding 6-retarded first, second 7, and third 8, fourth 9 exclusive OR elements, outputs of which are under

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The keys are connected to the information inputs of the first, fifth, eighth and tenth bits of the counter, respectively. The second inputs of the EXCLUSIVE OR elements 6-9 are connected to the output of the D-flip-flop 5, the D-input of which is connected to the output of the fifteenth digit of the counter, the R-input to the bus Reset 2 14, the clock inputs of the D-flip-flop 5 and counters 1-4 - with bus Clock 11. Reset enable inputs and resolution enable inputs of counters 1-4 are connected to the Reset 1 13 and Set 15 buses respectively, and the count resolution inputs of the first counter 1 are connected to the Bus Account 12. The 16th counter output is connected to the bus Output sixteen.

Multifunction counter works as follows.

Possible modes of operation, depending on the control signals, are given in the table.

In the table, x indicates the state of the log. Oh and Log. one.

The Set to 0 mode is used to prepare the multifunction counter for operation. When giving a signal Log. O to bus Reset 1 counters 1-4 are prepared for installation in O, and with the arrival of the pulse front are set to O. D-flip-flop 5 is reset to O when fed to bus Reset 2 levels Log. ABOUT.

In the Count mode, the multifunction counter counts the pulses coming through the clock pulse. Counter capacity 214. The sequential shift mode is used to read the state of the 16-bit counter.

The readout is carried out in parallel with the Bus Out when six or more pulses are sent to the bus Tact. In this mode, the D-trigger 5 is constantly in the Log state. A. At the second inputs of the EXCLUSIVE OR 6-9 elements there is also a Log level. Oh, so information through

they, unlike the well-known counter, pass without distortion.

In the signature-based signal processing mode, D-flip-flop 5 is unlocked (on Reset 2 bus level Log. 1) and runs parallel to the sixteenth section of the counter.

Thus, the information arriving at the Data input is summed modulo 2 with the sixteenth bit content on element 6 EXCLUSIVE OR and shifted to the right as the pulses arrive. Tact. A similar transformation is carried out with information from the fourth, seventh and ninth on the counter bits on the elements EXCLUSIVE OR 7-9.

At the end of signature processing, the multifunction counter is transferred to the Storage mode. In this mode, the state of the counter bits does not change.

The result of the signature processing is read bitwise from the Exit bus. For this, the counter is transferred to the Signature processing mode and serves sixteen pulses per bus Tact.

Claims (1)

Invention Formula A multifunctional counter containing the first, second, third, and fourth four-bit binary counters, the transfer output of the first counter is connected to the first count resolution inputs of the second, third, and fourth counters and the second count resolution input of the second counter, the transfer outputs of the second and third counters - on the second inputs allow the account accordingly 0 0 five 0 five 0 the third and fourth counters, the first and second elements are EXCLUSIVE OR, the data pin which is connected to the first input of the first element EXCLUSIVE OR OR, whose output and outputs are first, second, third, fifth, sixth, eighth and tenth-fifteenth counters are connected to the information inputs of the first, second, third, fourth, sixth, seventh, ninth and eleventh through sixteenth bits of the sixteen-bit counter, respectively; bus The account that is connected to the first and second gates The counting of the first counter, bus Installation, Pulse, Reset 1 and Output, which are connected respectively to the installation resolution inputs, clock inputs, reset resolution inputs of all four-bit counters and the sixteenth digit output of the counter, characterized in that in order to extend the functionality due to the provision of the sequential shift mode while simultaneously increasing the speed in the signature signal processing mode, the D-thringer, the third and fourth elements EXCLUSIVE OR and the bus Reset 2 are entered into it The D input of the D-flip-flop is connected to the clock input of which is connected to the Tact bus, and the D input to the output of the fifteenth digit of the counter, the first inputs of the second, third and fourth elements are EXCLUSIVE OR connected to the outputs of the fourth, seventh and nine, respectively In addition, the bits of the 16-bit counter, and the second inputs of all elements EXCLUSIVE OR are connected to the output B of the trigger.