SU1444933A1 - Multichannel switching device - Google Patents

Abstract

The invention relates to electronic switching technology and can be used in control and data transmission systems. The purpose of the invention is to increase the reliability of the transmitted information. The Multichannel switch contains in each measuring channel a divider 1, an inverter 2, elements AND 3., 8 and 12, a switch 6, D- triggers 9 and 14, a control switch 18, a voltage bus 22. Introduction to the device of ring distributors II and 13, the OR element 17 of the comparator 15, the key 21 of the calibration, and in each measuring channel of the frequency divider 1 and the element OR 5 increases the reliability of information transmission, which is achieved by increasing the sampling frequency of the measuring channel. of any measuring channel through this channel, the polling frequency is reduced, and through another measuring channel, through which information is transmitted, the polling frequency is increased, I il. (L 4 4 j; ib with Od with

Description

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The invention relates to electronic switching technology and can be used in control systems and data transmission.

The aim of the invention is to increase the reliability of the transmitted information.

The goal is achieved by introducing a frequency divider and in each measurement channel. the OR element, in addition, the insertion of an additional OR element, two ring pulse distributors, a comparator and a calibration key into the device, resulting in the shutdown of the faulty measurement channel, an increase in the polling frequency of the serviceable channels and the identification of the number of the faulty measurement channel,

To this end, in the event of a transmission channel interruption, the comparator generates a signal that writes to the D-flip-flop, and with the aid of logic elements, strobe signals are generated, controlling the operation of the main and additional keys.

The drawing shows a schematic diagram of a comm-tutor for two isms,:.; And body channels,

In each measuring channel there is a frequency divider 1, zyho ,; which through inverter 2 is connected; with the second input of the first element And 3, and the input with the first input of the first element And 3 and with the first input of the second element 4, the output of which is connected to the first input of the element OR 5, the output of which is connected to the control input of the key 6 of the corresponding channel . The inputs 7 of the keys 6 are the inputs of the measuring channels. The output of the frequency divider 1 is connected to the second input of the element OR 5, the third input of which is connected to the output of the first element AND 3 of another channel and to the first input of the third element AND 8 of the same measuring channel, the output of which is connected to the C input of the D-flip-flop 9 The direct outputs of the D-flip-flops A are connected to the third input of the first element I 3 of its measuring channel, and the reverse outputs to the second input of the second element I 4 of its channel and to the fourth input of the first element I 3 of another cable.

The outputs of the keys 6 all measuring as-ARG connected to the output bus-, 10

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The output of the first bit of the first ring distributor 11 pulses is connected to the first input of an additional element I 12, and the output of the second bit to the input of the second ring distributor 13 pulses and to the second inputs of the third elements; And 8 all measuring channels

The output of the additional element AND 1J is connected to the C-input of the additional B-trigger 14, the D-input of which is connected to the output of the comparator 15, whose inputs are connected to the output bus 10 and to the bus 16 of the reference voltage,

The output of the additional D-flip-flop 14 is connected to the first input of the additional elem.: That OR 17 and to the D-BXO of the D-triggers 9 of all measuring channels.

Outlet Supplement of a Custom Element OR

17 is connected to the ynpaR THmmj M input of the test terminal 18, the input of which is connected to the terminal 19 of the control source, its voltage, and the output to the output bus 10,

The terminal 20 of the clock generator is connected to the input of the first ring distributor iI pulses and to the second input of an additional element. And 1-2,,.

The output of the first bit of the second ring distributor 13 pulses is connected to the input of the divider i frequency of the first measuring channel, the output of the second bit to the input of the divider 1 frequency of the second measuring channel, and the output of the third bit to the controller 211 at the calibration switch 21 whose input is connected to the calibration terminal 22, and the output to the output bus 10,

Frequency divider 1 may contain serially connected pulse counter 23 and AND 24 summing element, the output of which is the output of the frequency divider, and the second input of which is connected to the counting input of counter 23, which is the input of frequency divider 1,

Keys 6, 18 and 21 can be made in the form of K-MDP keys,

Control key resistance

18 in the open state should be much greater than the resistance of the key b of the measuring channels, and greater than the output impedance of the source

signal connected to the inputs of 7 channels.

The value of the control voltage is selected outside the range g

commuting signals of measuring cables,

The magnitude of the reference voltage is chosen so that the output of the comparator 15 is a zero signal, 10 when the voltage on the output gin 10 is in the range of switching voltages, and, conversely, that the output of the comparator 15 has a single signal when the voltage on the output the width of the transmitted information, not 10, is out of the commutation range. If the inputs 7 are interrupted, both measured voltages are equal or, for example, to the test voltage on terminal 19.

The device works in the following manner 20 times.

With the arrival of a pulse at the input of the first ring distributor of II pulses, the control key 18 is opened, and the voltage from the terminal 19 of the interrogation source of the measuring channel that the test voltage is post. bypassing to decrease the interval falls on the output bus 10. At the same time, the key 6 of the first measuring channel opens, and the voltage at the same time, the polling time of the channel 7 also goes to the output width, which is determined by the duration of the output 10, As a result of the presence of split pulses of the second ring pulse distributor, twice the duration of the pulses at the outputs of the first ring distributor 11

The second measurement channel will have a zero signal, and the output of the first IZ element is single. As a result, the key 6 of the second measurement channel will be closed {and the corresponding key 6 of the first channel will be re-opened.

Thus, unreliable information from the faulty measuring channel is not transmitted to the device output, and the sampling frequency of the remaining normal measuring channel increases, which increases the validation channels at the outputs of the second 4 and first 3 elements. Similarly, zero signals are formed, resulting in the keys 6 being closed and measuring no information is output to the output bus 10,

Frequency divider 1 reduces the initial duty cycle

The extent to which the transmitted information may be unreliable, B

the voltage generated by the resistance of the public keys 6 and 18, a voltage is formed on the output bus 10.

When the inputs 7 are broken, both measures of the second measuring channel will have a zero signal, and the output of the first IZ element will be single, As a result, the key 6 of the second measuring channel will be closed {and the corresponding key 6 of the first channel will be re-opened.

Thus, inaccurate information from the faulty measuring channel is not transmitted to the device output, and the polling frequency of the remaining normal measuring channel increases, thereby increasing the polling confidence of the measuring channel, which is necessary to reduce the time interval; the duration of the output pulses of the second ring plant channel at the outputs of the second 4 and first 3 elements and, analogously, zero signals are formed, with the result that the keys 6 are closed and zmer EMA information is not supplied to the output line 10,

Frequency divider 1 reduces the initial duty cycle

 polling of the measuring channel, which is necessary to reduce the time interval, the duration of the polling channels, determined by the duration of the output pulses of the second annular diversion, during which the transmitted information may be unreliable,

close to the switching of the first 35 pulses.

Calibration key 21 is opened by the signal from the last bit of the second ring distributor 13 pulse

measuring channel.

The zero signal from the output of the comparator 15 is written into the additional D-flip-flop 14 and then the gates, which allows for a periodic

The main pulse from the output of the third element in the time diagram of the magnitude of the voltage And 8 is recorded in the D-flip-flop 9 on the terminal 22 of the calibration of the defined measuring channel, In the number of the measuring channel, as a result, the input turns 7 which, as a result of a discontinuity of the clock pulse and over the access to the transmission channel, there was not enough output of the first bit of the second ring-45 to receive information,

Thus, a multichannel KOWnichnogo signal at the output of the second element I 4 of this measuring channel produces a single signal that permits polling of this channel for all 50 unreliable information in the case of the time of the enable signal, the transmission channel is disconnected and provides

When the input 7 is broken, for example, the second measuring channel, the keys 6 and, 18 work the same way. However, at the output of the comparator 15, the signal number 1- 55 results in a signal that is written to the additional D-flip-flop 14 and then to the D-flip-flop 9 of the second measurement channel. At the same time, the switch provides an adaptive mode of polling the measuring channels in time, reduces the possibility of transmitting

identification of a faulty measuring channel.

Claims (1)

Invention Formula A multi-channel switch containing in each measuring channel: a key whose input is the input of the channel and the output is connected to the output ow, which allows for periodic Thus, multichannel KOW-inaccurate information in the event of a transmission channel break and provides the mutator provides an adaptive polling mode of measuring channels in time, reduces the possibility of transmission unreliable information in the event of a broken channel and provides identification of a faulty measuring channel. Invention Formula A multi-channel switch containing in each measuring channel: a key whose input is the input of the channel and the output is connected to the output  bus device, the three elements And, np vert and. D-arigger, as well as a control key, the output of which is connected to the output bus of the device, an additional D-trnger and an additional element I, one of the inputs of which is connected to the clock generator terminal, which, in order to increase the reliability of transmission of the measured information, a frequency divider and an OR element are entered into each measuring channel, and, in addition, two ring pulse distributors, an OR OR element, a comparator, and a calibration key are entered into the device, and the comparator inputs are connected It is suitable to the reference voltage bus and to the device output bus, and the output is to the D input of an additional D-flip-flop, whose C input is connected to the output of an additional element I, and the output to the D inputs of D-triggers of measuring channels and -. the first input is an additional element 5 and the reverse output. D-flip-flop each. to OR, the second input of which is connected to the second input of the additional element AND, and the output to the control input of the control key, the input of which is connected to the terminal of the source of the test voltage, the input of the first ring distributor imp, is connected to the terminal clock r & nerator, the output of the first discharge of this distributor is connected to the second input of an additional element AND, from the measuring channels are connected respectively to the additional inputs of the OR elements and to the additional inputs of the first elements AND all other 30 measuring channels, and the output of the most significant bit of the second ring distributor of pulses is connected to the control input of the calibration key, the input to the expensive is connected to the terminal ka-jg librovkn, and the output - to the output bus of the device. the output of the second bit is with the input of the second ring pulse distributor and with the second inputs of the third elements AND of all measuring channels, the output of the corresponding bits of the second ring pulse distributor subkey1-1 to the input of the frequency divider and the first inputs of the first and second elements And the same measuring channels, in each of which the output of the frequency divider is connected to the first input of the third element AND, to the second input of the element OR and through the inverter to the second input of the first element AND, the output of the third element And is connected to I. ... -. The D-flip-flop input, the direct output of which is connected to the third input of the first element And, and the return output with the second input of the second element And, the output of which is connected to the first input of the element, the output of which is connected to the control input of the key, and, besides In addition, the output of the first element and from the measuring channels are connected respectively to the additional inputs of the OR elements and to the additional inputs of the first elements AND all other measuring channels, and the output of the most significant bit of the second ring pulse distributor is connected to the control input of the calibration key, the input to the expensive is connected to the terminal of the calibration cable, and the output is connected to the output bus of the device.