SU1480110A1 - Multichannel switch - Google Patents

Abstract

The invention relates to electronic switching technology and can be used in automation, control and measurement systems. The aim of the invention is to enhance the functionality of the switch while increasing its reliability by implementing the prohibition of switching on measuring channels during a short circuit of the output bus and limiting short-circuit currents. In the switch that contains the keys 1, the inputs of which are the inputs of 2 channels, the outputs are connected to the output bus 3, and the control inputs are connected to the outputs of the first pulse distributor 4, and the calibration channel containing the main key 7, the first element And 15, D- trigger 17, second 18 and third 21 elements AND, the target is achieved by introducing six additional keys 8-13, element AND-OR 16, voltage divider 14, two comparators 19.20 and second voltage distributor 5. In the event of a short circuit, the output tires 3 for the voltage in This range, determined by the voltage divider 14, at the expense of the entered elements, signals are generated that prohibit the switching on of the keys of the measuring channels. 1 il.

Description

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The invention relates to electronic switching technology and can be used in systems of automation, control and measurement.

The purpose of the invention is to expand the functionality while increasing its reliability, which is achieved by introducing six additional keys, a voltage divider, two comparators and an AND-OR element into the switchboard by generating signals that prohibit the switching of the keys of the measuring channels during a short circuit of the output bus of the device to a voltage which is in a predetermined range defined by a voltage divider. At the same time, short-circuit currents are limited, which increases the reliability of the device.

The drawing shows a functional diagram of a multi-channel switch containing, for example, three measuring channels.

A multi-channel switch contains in each measuring channel a key 1, the input of which is connected to the input bus 2 of the corresponding channel, and the outputs of all keys 1 are combined and connected to the output bus 3, the control inputs of the keys are connected to the corresponding outputs of the first distributor 4 pulses, the input of which is connected to the third output of the second distributor 5 pulses, the input of which is connected to the clock bus 6.

The calibration channel includes the main key 7, six additional keys 8-13, the inputs of which are connected to the corresponding outputs of the division0

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voltage bodies 14, the first element 15, the first input of which is connected to the clock bus 6, and the output to the first inputs of the circuits AND of the I-IPI 16, the output of which is connected to the C input of the D flip-flop 17, the D input which is connected to the output of the second element And 18, the inputs of which are connected to the outputs of the first and second Comparators 19 and 20, and the third element And 21, the output of which is connected to the installation input of the D-flip-flop 17, and the inputs are connected to the first outputs of the first and second valves, respectively 4 and 5 pulses „

The non-inverting input of the first and the inverting input of the second comparators 19 and 20 are connected to the output bus 3, and the second inputs - respectively to the combined outputs of the fifth 12 and sixth 13, third 10 and fourth 11 additional keys. The combined outputs of the first 8 and second 9 additional keys are connected to the input of the main key 7, the output of which is connected to the output bus 3, and the control input is connected to the first output of the first distributor 4 pulses and the second input of the first element I 150

The control inputs of the first 8, third 10, and fifth 12 additional keys are connected to the third output of the second distributor 5 pulses and the second input of one of the I-IPI circuit 16.

The control inputs of the second 9, fourth 11 and sixth 13 additional keys are connected to the second output of the second distributor 5

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pulses and the second input of another circuit AND element AND-OR 16,

The second input of the first element I 15 is connected to the first output of the first distributor 4 pulses, and the third to the direct output of the D-flip-flop 17 whose reverse output is connected to the installation input of the first distributor 4 pulses „

All keys can be made in the form of, for example, K-MDP keys based on a pair of complementary MIS transistors and an inverter.

The first and second distributors of 4 and 5 pulses are made on the basis of a shift register, for example, on the basis of a counter and a decoder. Valves are triggered on the falling edge of the input signal. The first outputs of the distributors are the outputs of the lower bits.

D-trigger 7 is triggered by the leading edge of the pulse arriving at the C input “

If there is a single signal at the installation input of the first distributor of 4 pulses, all the outputs of the distributor, except the first, are set to zero signals.

The resistance in the open state of the keys 1 of the measuring channels is much less than the resistance of the main key 7 of the calibration channel.

Voltage divider 14 is a chain of seven series-connected resistors, which is connected between the device power buses. The connection points of the resistors are the outputs of the voltage divider,

Multichannel switch works as follows.

During normal operation of the switch, the pulses that arrive at the input of the second distributor 5 pulses, divide the frequency three times, arrive at the input of the first distributor 4 pulses, and begin to connect keys 1 in series.

After turning on the key, the calibration channel is turned on. The calibration channel is used to calibrate the measurement channels of the switch and is an indicator for determining the closure of the output bus 3 to any voltage

Work channel kliibrovki consists of three cycles. In prem of the first cycle of Kanaml calibration, with

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corresponding to the pulse coming from the first output of the second distributor 5 pulses, is set to 1 D-flip-flop 17. During the second cycle of the calibration channel, corresponding to the pulse coming from the second output of the second distributor 5 pulses, the voltage U comes to the input of the main switch 7 From the second output of the voltage divider 14 During the third cycle of the calibration channel, corresponding to the pulse coming from the third output of the second distributor 5 pulses, the input of the main switch 7 is received voltage U7 outputs a fifth voltage divider 14.

Consider the operation of the calibration channel in case of the output bus 3 not closing on the switch for some voltage. During the first cycle of the calibration channel, the D-trigger 17 is set. During the second cycle of the calibration channel, the voltage U, from the second output of the divider 14 voltages are fed to the input of the first additional key 8 ". Since the primary 7 and the first additional 8 keys are open, this voltage is fed to the output bus 3. Simultaneously, the voltage U. + MJ from the third output of the voltage divider 14 is opened The third third additional key 10 is fed to the non-inverting input of the second comparator 20, and the voltage U, dU from the first output of the voltage divider 14 through the open fifth additional key 12 to the inverting input of the first comparator 19. At the outputs of the first and second comparators 19 and 20. Single signals are generated. Since there are single signals at both inputs of the second element And 18, there is also a single signal at its output, which confirms the single state of the D-trnger 17. During the third cycle of the channel operation, ki voltage U i to the fifth output voltage divider 14 is input to the second additional key 9. Since the second additional keys 9 and the main open, this voltage is supplied to the output line 3.

Simultaneously, the voltage 11g is from the fourth output of the divider 14 to 514

through the open sixth additional terminal 13 goes to the inverting input of the first comparator 19, and the voltage a from the sixth output of the voltage divider 14 through the open fourth additional key 11 to the non-inverting input of the second comparator 20. At the output of the first and second comparators 19 and 20 single signals are formed. Since there are single signals at both inputs of the second element And 18, there is also a single signal at its output, which confirms the single state of the P-trigger 17.

Consider the operation of the switch in case the output bus 3 is closed to the voltage U.

During the second cycle of the calibration channel, the voltage U1 from the second output of the voltage divider 14 is fed to the input of the first additional key 8. Since the main and first additional 8 keys are open, this voltage goes to the output bus 3 Simultaneously, the voltage U, - From the first output, the voltage divider 14 is fed to the inverting input of the first comparator 19, and the voltage U., + / Ill to the non-aligning input of the second comparator 20. Single signals are formed at the outputs of the first and second comparators 19 and 20. Since both outputs of the second element And 18 are single signals, there is also a single signal at its output, which confirms the single state of the P-trigger 17 During the third cycle of the calibration channel, the voltage from the fifth output of the voltage divider 14 is fed to the input of the second Additional key 9, Since the output bus 3 is closed to voltage II, this voltage will always be on it. At the same time, the voltage TIj- and 11 goes to the inverting input of the first comparator 19, and the voltage + LI to the non-inverting input of the second comparator 20. At the output of the first comparator 19, there will be a zero signal that will be written to D-trigger 17. About the second distributor of 4 pulses, and only at its first output will be a single guitar.

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Consider the operation of the switch in the middle, if the output bus 3 is closed to the voltage U.

During the second cycle of the calibration channel, the voltage from the fifth output of the voltage divider 14 is fed to the input of the first additional key 80. Since the first additional key 8 is open, this voltage will go to the input of the main key 7. There will always be voltage on the output bus 3 U7. The output of the first comparator 19 will be a zero signal, which will be recorded in the D-flip-flop 17, 4 pulses will be set to O of the second distributor, and only its first output will be a single signal. Only the calibration channel will work,

Consider the operation of the switch in case the output bus 3 is closed for any voltage that does not coincide with U1 or U.

During the second cycle of the calibration channel, the voltage from the output of the voltage divider I4 is fed to the input of the first additional switch 8C. Since the first additional switch 8 is open, this voltage will go to the input of the main switch 7. On the output bus 3 there will always be a short circuit voltage “If U% / U ,, is dU, then the output of the first or second comparator 19 or 20 will be a zero signal, and in any case a zero signal will be written to the D-flip-flop 17. The second distributor will have 4 pulses in O, and only on it the first exit will be single signal. Only the calibration channel will work.

Thus, in case of closing the output bus 3 to a voltage in a certain predetermined range, the switching on of the measuring channels is prohibited. After eliminating the closure, the multichannel switch restores its operation with

Since the keys 1 of the measurement channels close when the output bus is short-circuited, and the resistance of the public key 7 is sufficiently high, short-circuit currents in the switch are significantly limited, resulting in increased reliability. Therefore, this switch can be used 714801

Designed for self-monitoring systems with a wide range of voltages and signals used, both digital and analog.

Claims (1)

Invention Formula A multi-channel switch containing keys in each measuring channel, whose inputs are channel input buses, outputs are combined and connected to the device output bus, and control inputs are connected to the corresponding outputs of the first pulse distributor, as well as a calibration channel that includes the main key, the output of which connected to the output bus, the three elements And and the D-flip-flop, which differs from and with the fact that, in order to extend the functionality while increasing reliability, six additional cells are introduced into it whose AND-OR element, voltage divider, two comparators and the second pulse distributor, whose input is connected to the first input of the first AND element and connected to the clock bus, the output of the first AND element, is connected to the first inputs of the AND-OR circuit, the second inputs which are connected respectively to the second and third outputs of the second pulse distributor, to which the control inputs are also connected, respectively eight 0 five 0 five 0 five second, fourth, sixth and first, third, fifth additional keys, the third output of the second pulse distributor is also connected to the input of the first pulse distributor, the installation input of which is connected to the reverse output of the D-flip-flop, whose C input is connected to the output of the I- element OR, D-input - with the output of the second element I, and the installation input - with the output of the third element I, whose inputs are connected to the first outputs of the pulse distributors, the second input of the first element I is connected to the control input of the main key and the first output of the first pulse distributor, and the third input - with the direct output of the D-flip-flop, the non-inverting input of the first and the inverting input of the second comparators, whose outputs are connected to the inputs of the second element And, are connected to the output bus of the device, and the second inputs of the same the comparators are connected to the combined outputs of the fifth, sixth and third, fourth additional keys, respectively; the combined outputs of the first and second additional keys are connected to the input of the main key, and the outputs of the divider Order voltages are connected respectively to the inputs of the fifth, first, third, sixth, second, and fourth additional keys.