SU1368982A1 - Redundancy divider-shaper - Google Patents

Description

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The invention relates to a pulse technique and can be used to organize synchronous operation of the channels of a redundant digital complex.

The purpose of the invention is to expand the functionality by ensuring the operation of both synchronous and asynchronous (phased) input signals.

The drawing shows the electrical structure of the divider-maker „

The redundant splitter driver contains a clock signal bus 1, which is connected to the clock inputs of register 2 and D-flip-flop 3, the inverse outputs of the high bits of the register 2 of all channels are connected to the inputs of the majority elements of all 4 channels, and besides, the input of the comparison element 5, the outputs of the register 2 are connected to the output buses 6, the second input of the comparison element 5 is connected to the output of the majority element A, to the first input of the first element And 7 and to the information input of the D-flip-flop 3, output For example, comparison circuit 5 is connected to the second input element AND 7 and through the inverter 8 to the first input of the second element AND, the second input of element AND 9 is connected to the output of D-flip-flop 3, the outputs of elements AND 7. and 9 are connected to the first and second inputs of the element OR 10, the output of which is connected to the information input of the register 2.

Divider-shaper works as follows.

By turning on the power, the device triggers can be set to an arbitrary state.

Suppose that (as an example, a 3-bit register is considered) in channel 1, the first, second, third bits of register 2 were set to (1,0,0) in channel II (0,0,0) in the channel III (O, 1.0), D-flip-flop 3 of all channels - in one state. Then the outputs of elements 4 and 5, of all channels are in one state, and the outputs of inverters 8 of all channels are in zero state Elements 7 of all channels are open, and elements 9 are closed.

On the first clock pulse from bus 1 (let the clock pulses of all channels

phased out and start, respectively, in channels I, II, and III) register bits 2 and D-flip-flop 3 are set in channel I in the state (1,1,0,1), in canape II (1, 0,0,1), in channel III (1,0,1,1). In channel III, element 5 is set to the zero state, closing element 7 and opening element 9. As in channel III, U-flip-flop 3 remains in one state, then at the output of element 10 there is one state, as well as at the output of element 4 .

In the first channel on the second clock pulse register bit 2 set0

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Copies 4 all channels to zero state.

In channel II, element 5 is set to the zero state, closing element 7 and opening element 9. Since D-flip-flop 3 remains in one state, there is also a single state at output of element 5.

In the L1 channel, element 5 is set to one state by opening element 7 and closing element 9. At the output of element 10, there is a zero state (as well as at the output of element 4).

On the second clock pulse from bus 1 in channel II, register bits 2 and D-flip-flop 3 are set to state (1,1,0,0), element 10 is set to zero state.

On the second clock pulse from bus 1 in channel III, register bits 2 and D-flip-flop 3 are set to (0,1,0,0), the major elements of all channels are set to one.

In channel I, element 5 is set to the zero state by closing element 7 and opening element 9. At the output of element 10, there is a single state (as at the output of the D-trigger 3).

In channel II, element 5 goes into one state, opening element 7 and closing element 9. At the output of element 10, it is a single state.

5 According to the third clock pulse from bus 1 of channel I, the state of the elements in channel I does not change.

On the third clock pulse of channel II, register bit 2 and D-trigger

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pue level) not from element 4, but from 0-flip-flop 3 through elements 9 and 10. On the sixth clock pulse of channel II in channel II, element 5 is set to one state, and register 2 registers to the state (0.0, 0) - the same as B 1 and III (anals, i.e., registers 2 of all channels-phas are phased.

3

3 in the second channel, the elements of all 4 channels and the element 10 are set to zero in one state.

In channel 1, element 5 is set to one by opening element 7 and closing element 9. At the output of element 10, the state is zero.

In channel III, element 5 is set to the zero state by closing element 7 and opening element 9. At the output of element 10, there is a zero state (as well as at the output of D-flip-flop 3).

On the third clock pulse of channel III in channel III, register bit 2 and D-flip-flop 3 go to state (0,0,1,0), element 5 switches to one state, opening element 7 and closing element 9.

On the fourth clock pulse, the register 2 and the D-flip-flop 3 of the I and II channels are switched to the state (0,1,1,0) and in the III channel the register 2 and the D-flip-flop 3 are set to the state (0,0,0, 0), and element 5 is in the zero state o

According to the sync pulse, the state of registers 2 and D-flip-flops 3 in channels I and II (0,0,1,0), in channel III (0,0,0,0). The state of the remaining elements is the same.

On the sixth sync pulse of channel I, the state of the register 2 and the D-flip-flop 3 of the I channel (0,0,0,0), the elements 4 of all channels are set to one state, the element 5 of the third channel is set to one state, opening the element 7 and closing the element 9. The information input from the channel 2 register III through the elements 7 and 10 receives information from the element 4 - the unit level. In channel II, element 5 is set to the zero state by opening element 9 and closing element 7. The information input of the register 2 of channel II receives information

Since the registers 2 of all channels are phased, the first one changes its state to the register, to the sync input of which the first clock pulse arrives after phasing the channels. Such a register is Channel 2 Register 2. The change of information is sequentially carried out in I and II channels.

The maximum phasing time of the lost channels is (pT,), where n is the number of register bits, TgK is the period of the synchronizing signals.

The worst case is considered: when all channels are de-phased with phased input signals. In this case, the shift between the same channel bits is equal to the shift between the input signals.

Claims (1)

Invention Formula 25 0 five 0 five 0 five A redundant divider-driver, containing three division channels, each of which contains a clock signal bus connected to the register and D-trigger clock inputs, the first AND element whose output is connected to the first input of the OR element, the output of which is connected to the information input of the register and the majority element, the inputs of which are connected to the corresponding inputs of the majority elements of other division channels, characterized in that, in order to expand the functionality, it is entered into The second element is And, the comparison element and the inverter, the inverse outputs of the high bits of the registers of all channels are connected to the corresponding inputs of the majority elements of all channels, besides the inverse output of the high bit of the register of its channel is connected to the first input of the comparison element, the second input of which is connected to the output of the majority element, with the first input of the first element ll and with the information input of the D-flip-flop, the output with the second input of the first element I and through the inverter with the first input of the second element I, the second input otorrhea Dtriggera connected to the output, the output - to the second input of the OR element.