SU1241208A1 - Pulsed stabilizer - Google Patents

Abstract

The invention relates to the field of stabilized power sources. The aim of the invention is to simplify the pulse stabilizer. The goal is achieved by the fact that the voltage is stabilized as follows. When the high voltage deviates from the one specified on the direct or inverse output of the comparator 3, a signal 1 appears, the key 13 or 14 opens, and the pulse from the counter 11 sets the trigger 8 to one state. As a result, the switch 6 ISD 4; u o 00

Description

P

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tuiH 7 changes its state and the pulse from generator 5 is fed to the reporting input of the second discharge of counter 11 or 12. A clock pulse arrives at the input of the first 0 of the discharge of counter 11 or 12. The pulse advance from the output of counter 11 of the pulse from the output of counter 12 will increase or decrease by a time T, i.e. The duration of 1shpulse at the output of the trigger 10 will increase or decrease by the time T ,, which will cause an increase or decrease. The invention relates to electrical engineering and can be used in the development of sources of secondary power supply for radio-electronic equipment of wide application.

The purpose of the invention is to simplify the pulse stabilizer.

The drawing shows a block diagram of a pulse stabilizer.

The impulse stabilizer contains an adjustable 1T element 1, a converter 2 with a filter, a compiler 3, usi 1P1tel 4, a clock generator 5, the first and second switches 6 and 7, the first, second and third triggers 8-10, the first and second counters 11 and 12j the first and second keys 13 and 14 and the source 15 of the reference signal.

The operating input of the regulating element 1 is the input of the device, the control input is connected to the output of amplifier 4, and the input to the input of converter 2 with a filter whose output is connected to the output of the device and to the first input of the comparator 3, the second inlet of which is connected to output source 15 of the reference signal. The direct and inverse outputs of the comparator 3 are connected to the control inputs of the first and second keys 13 and 14, respectively, the outputs of which are connected to the installation inputs 1 of the first and second triggers 8 and. 9. Output clock generator. 5 is connected to: the working inputs of the first and the second; ommparators 6 and 7, the control inputs of which are connected to the direct outputs of the first and second triggers 8 and 9, respectively. First exit

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field output voltage depending on mismatch sign. ;; if by the time the next pulse appears at the output of the counter 11, the output voltage level is still different from the set one, the process will be repeated, 1 will be added to the counter 11 or 12, i.e. advancing further increases or decreases, which leads to a corresponding change in the output voltage. I il.

 the first switch 6 is connected to the counting input of the first bit of the first counter 11, and the second output is connected to the counting input of the second bit of this

5 same meter and with the installation input in. the first trigger 8. The first output of the second switch 7 is connected to the counting input of the first bit of the second: 12 counter 12, and the second output 0i to the counting input of the second ra: protection of the same counter and to the installation input of the second trigger 9.. The output of the overflow of the first counter 11 is connected to the working input

15 of the first key 13 and with the input of the installation in 1 of the third trigger Yu, and

. } Overflow of the second counter 12 - with the working input of the second key 14 and with the installation input in O

20-third trigger 10, the output of which is connected to the input of the amplifier 4.

5 The tutorial works as follows.

25 In the initial state, the required stabilization level is set at the output of the source 15 of the reference signal: - days, counter; 11 is half full, for example, and the counter 12 and all of the triggers are set to the output of the device, the supply voltage is applied. In this case, the working inputs of the switches 6 and 7 are connected to their first outputs.

Let the output voltage be stabil35

there are no single signals at the outputs of the comparator and, therefore, the keys 13 and 14 are closed.

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The clock pulses from the output of the generator 5 synchronously arrive through the switches 6 and 7 to the counting inputs of the first bits of the counters 11 and 12, as a result, overflow outputs of these counters appear pulses with a period T ° 2 TO. Since in the initial state, the counter 11 was half filled, the pulses on its

the output is ahead of the pulses at the output of the counter 12 at the time T ° / 2. As a result, at the output of the trigger 10, rectangular control pulses of a duration Tu T ° / 2 with a period T ° are formed.

 Amplified by amplifier 4, these pulses are fed to the control input of the regulating element 1. If the output voltage is equal to the specified one, the device continues to operate in the described mode.

Let the output voltage of the stabilizer decrease. In this case, a single signal occurs. At the direct output of the comparator 3, the key 13 opens and another overflow pulse of the counter 11 passes through this key, sets the trigger 8 to 1. As a result, the switch 6 changes its state and the next pulse from the generator 5 goes to the counting input of the second discharge of the counter 11, as well as to the zero input of the trigger 8, thereby returning the switch 6B to the initial state.

Thus, one of the clock pulses is fed to the input of the first digit of the counter 12 and to the second bit of the counter 11. As a result, the pulse advances from the output of the meter 11 to the pulse of the output of the counter 12 increases by time T, i.e. the pulse duration is increased by the time TO, which causes an increase in the output voltage.

- If by the time the next pulse appears at the output of the counter 11, the required output voltage level is still not reached, then the additional (as compared with the counter 12) 1, i.e. the lead time and, consequently, the pulse duration is increased by another time TO, etc.

When the output voltage reaches a predetermined level after K of the described cycles, the key 13 is closed and the device continues to form a pack

o

five

0

0

0

2084 equalizing pulses with a duration of Tu T ° / 2 + KTO ensuring the maintenance of the required level of the output voltage.

If the output voltage is less than a predetermined one, a single signal appears at the inverse output of comparator 3, key 14 is opened and additional pulses are received in the same way as described in counter 12, as a result of which pulses from the output of the counter 11 pulses from the output of counter 12 decrease, t . the value of T decreases, which leads to a decrease in the output voltage. This process continues until the output voltage reaches a predetermined level. After that, at both outputs of the comparator 3, a zero signal appears and the change in the duration of the control pulses is stopped.

Thus, the device provides signal stabilization with simpler technical means, and the stabilization accuracy can be as high as desired.

If the signal from source 15 changes over time, the output reproduces this change.

Claims (1)

Invention Formula Pulse stabilizer containing a regulating element, a converter with a filter, a clock generator, two counters, two keys and an amplifier, an output connected to the control input of the regulating element connected between the input terminals and the input of the inverter with a filter whose output is connected to the output terminals , characterized in that, in order to simplify the device, two switches, three triggers, a comparator and a source of reference signal, connected by an output to the first input of the comparator, are introduced into the device, the second input is cat This is connected to the output terminals, and the direct and inverse outputs are connected to the control inputs of the first and second keys, the outputs of which are connected to the installation inputs to 1 of the first and second triggers, and the inputs are combined respectively with the installation inputs to 1 and O of the third trigger connected output to the input of the amplifier, and are connected to the outputs of the first and second counters 12412084, respectively, with the counting respectively, the output of the clock of the inputs of the first and second bits The hub is connected to the working inputs of the first and second counters, except the first and second switches, on the other hand, the second outputs of the first and second-turn codes of which are connected by kgo switches are connected to the inputs direct outputs of the first and second installations in About the first and triggers, the first and second outputs of the second triggers, respectively. the first and second switches connect.