SU1357940A1 - Timer - Google Patents

Abstract

The invention relates to computing and can be used in control computing systems for real-time operation. A special feature of the timer is that it ensures that information is accumulated during the counting without prejudging the count, as well as recording a new value of the time interval without breaking the current count. The aim of the invention is to increase the speed. The goal is achieved by introducing a second register 3, the driver 13 pulses. 1 hp f-ly, 3 ill. (L fiv.1

Description

The invention relates to computing and can be used in control computing systems for real-time operation.

The aim of the invention is to increase speed.

Fig. 1 shows the functionality of the timer circuit of Fig. 2 — a functional diagram of the pulse former; Fig. 3 shows time diagrams of the timer operation in the census mode in the second register and read resolution. The timer contains a register 1, a counter 2, a register 3, an interval setting group 4, an information output group 5, a write enable input 6, an interrupt enable input 7, a read permission input 8, AND 9, a clock generator 10 containing a master oscillator 11 and driver 12 pulses with a high porosity, driver pulses 13, the element AND NOT 14, interrupt output 15, response signal output 16.

The shaper 13 pulses contains the element NOT 17, the trigger 18 and the element And 19.

The timer works as follows.

The digital value of the specified time-30 inhibits the passage of the clock interval of the interval is recorded from a group of 4 inputs on the record enable signal from input 6 to register 1 and is fed to the information inputs of counter 2, which operates in subtraction mode. The pulses from the clock generator 10 are fed to the clock input of counter 2, and if there is no signal at input 7 of the interrupt resolution, then at the output of element 9 there is a rewrite signal that allows the digital value of the time interval to be written to the counter 2 to be written.

element 9 of the resolution signal pre- starts the reading of information on

The re-write signal from counter 2 is removed at input 7, and it starts counting on the leading edge of clock pulses until a pulse appears at the counter overflow output, which arrives at interrupt output 15 and, through AND 9, restores or records the new the digital value of the time interval in counter 2, stored in register 1.

Record a new value of the specified time interval reg.

The data recording enable signal received at input 6 can be carried out during counting without changing the counter state. This is due to the fact that during counting, there is no overwrite signal at the control input of the counter, and the write enable signal affects only register 1.

The timer in the overwriting mode in register 3 and read resolution (Fig. 3) works as follows. On the falling edge of each clock pulse in the absence of a signal at input 8

permission to read status information. The counter 2 is rewritten to register 3. In this case, the trigger 18 is in the initial (zero) state, at its inverse output, a signal with a Log level. 1 disengages the passage of clock pulses through AND 19 element to control input of register 3.

When the read enable signal arrives at the input 8 when no record is written to register 3, the flip-flop 18 is thrown when the read enable signal arrives. At the inverse output of the trigger 18, a signal is formed with a Log level. Oh which

five

0

pulses through the element AND 19. Thus, the write signal to the register 3 is not formed, and the state of the register 3 during the reading does not change. The trigger 18 is reset to the initial state after the end of the read enable signal on the falling edge of the next clock pulse.

If the read enable signal arrives at the input 8 of the timer at the time of writing to register 3, then the trigger 18 is thrown over the falling edge of the clock pulse used to write to register 3. When

the read enable signal is jarred relative to its start, the smaller, the shorter the duration of the clock pulse.

Simultaneously with the prohibition of changing the state of the register 3, the AND-HI element 14 generates a timer response signal for the time of coincidence of the signal at the forward output of the flip-flop 18 and the read enable signal.

Thus, the read enable signal does not interrupt the arrival of clock pulses in counter 2, but at the same time prohibits the formation of sig31

write to register 3, thereby providing readable information from register 3 during the read enable signal regardless of its duration.

In addition, information can be recorded in register 1 during the current account (without changing the latter) by separating the data recording enable signal and enabling the interrupt.

Claims (2)

1. A timer containing a first register, a counter, a clock generator, an AND element and a NAND element, the group of information inputs of the first register is a group of inputs for setting the timer interval, the input of recording resolution of the first register is an input of recording resolution of timer connected to a group of information inputs of the counter, the input of the resolution of which account is connected to the output of the element I, the first input of which is connected to the inverse output of the overflow of the counter and is the output of interrupting neither the timer, Exit AND-NO element is output response timer, characterized in that, in order to increase operating speed, introduced in it and forms the second register five n pulse generator, the clock generator output is connected to the clock input of the counter and the synchronizer input of the pulse generator, the first output of which is connected to the write enable input of the second register, the counter bits outputs are connected to the information inputs of the second register, the outputs of which are the timer information outputs, input permitting the reading of the timer is connected to the enable input of the pulse former and to the first input of the NAND element, the second input of which is connected to the second output of the pulse former c, the second input of the AND element is the timer interrupt enable input. 2. Timer pop. 1, characterized in that the pulse shaper includes a trigger, an NOT element and an AND element, wherein the read enable input of the pulse shaper is connected to the information input the trigger whose sync input is connected to the output of the NOT element, the sync input of the pulse former is connected to the input of the NOT element and to the first input of the element I, the second input of which is connected to the inverse output of the trigger, the output of the element I is the first output of the imager, the direct output of the trigger is the second shaper output. f pezi / cmpy J Kelemen / g y Fig2 yy t and fff eight Srig. H  Editor L. Langazo Order 5999/49 Compiled by N.Toropova Tehred A. Kravchuk Corrector V. But ha Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production .-printing company, Uzhgorod, st. Project, 4