SU1290503A1 - Device for controlled delay of pulses - Google Patents

Abstract

The invention relates to a pulsed technique and can be used in telemetry, measurement and instrumental technology. The purpose of the invention, the extension of the field of application, is achieved due to the possibility of working with zero delay codes. Another goal — an increase in reliability — is achieved by reducing the number of circuit elements and locking the device when the input signal duration does not match the selected delay range. The device contains triggers 1 and 2, D-trigger 3, which forms trigger 4, elements AND 5-9, elements OR 10-13, elements NOT 14 and 15, generator 16 clock pulses, counter 17, device input 18, bus 19 code, output bus 20. With the help of the code supplied to bus 19, discrete control is performed of the selection of the output pulse delay value. When a zero code is applied to these muds, the device switches to the initial state. 2 Il. S (L O SP oo fae1

Description

The invention relates to a pulse technique and can be used in telemetry 5 in a measuring and computing technique.

The purpose of the invention is to radiate the field by providing the ability to work with zero delay codes and increasing reliability as a result of reducing the number of elements and locking the device if the input signal length does not match the selected delay range.

Fig, I shows the functional diagram of the pre-burned device; In Fig. 2, timing diagrams explaining the operation of a device for controlling a dependent impulse.

The controllable pulse delay device contains the first 1 and second 2 triggers, the D-flip-flop 3, which forms the flip-flop 4, the first 5, the second 6 third 7, the fourth 8 and the fifth 9 Elements And, the first 10, the second., The third 2 and the fourth 13 elements SH, first 14 and second 15 elements NOT, - generator 16 clock pulses, counter 17, device input 18, code bus 9 and output bus 20. Clock output 16 clock connected to D-input of D-flip-flop 3; the input element And 5 and through the element NOT 15 with the input element And 6 The second inputs of the elements 5 and 6 are connected to the inverse and forward outputs of the D-flip-flop 3, and the outputs through the element OR 10 - to the subtractive input of the counter 17. Information inputs

D

i 9

S Dj counter 17 connected

to tires 19 code. Input 18 of the device is directly connected to the counting input of the first trigger and through the first element NOT 14 to the counting input of the second trigger 2. The inputs of the third element OR 12 are connected to the forward outputs of the first and second triggers 1 and 2, and the output is connected to the C input D-flip-flops 3. The inputs of the third element And 7 are connected to the inverse outputs of the flip-flops 1 and 2 "The inputs of the fourth element And 8 are connected respectively to the direct output of the trigger 1 and the output of the first element NOT 14, The outputs of the elements 7 and 8 through the element OR 11 are connected to permit entry for counter 17, the inputs of the element OR 13 are connected to the tires of the 19th code, and the output is connected to the R input of the forming trigger

4 and the input element I 9. The counting input of the forming trigger 4 is connected to the output of the counter 17, the direct output to the output bus 20 and the R input of the reset

trigger 2, and the inverse output to the second input element And 9. The output element And 9 is connected to the R input of the reset of the first trigger 1.

The device works as follows.

in the way

In the initial state on bus 18, the input signal is absent (zero level). At the output of the generator 16, there are rectangular pulses,

the duration of which is half the period. At the output of the element NOT 15 there are inverted pulses of the output of the generator 16. On the tires 19 there is a zero code, which is

walks through the element OR 13 zero level. The zero output level of the element OR 13 acts directly on the trigger 4 and through the element AND 9 on the R input of the trigger 1,

keeping them in zero states (on direct outputs - zero, on inverse - single levels), Zero level of direct output of trigger 4 passes to bus 20 and to R-input

trigger 2 and keeps trigger 2 in the zero state. The unit levels of the inverse outputs of the triggers 1 and 2 pass through the element AND 7 and the element OR 11 with the unit level at the input

permitting the write of counter 17, according to which the zero code of tires 19 is entered into counter 17, Trigger 3 is in the zero state. The pulse output of the generator 16 passes through

the element AND 5 and the element OR 10 to the subtracting input of the counter 17. The counter 17 does not sense the output pulses of the element OR 10 and is in the zero state until

The record enable input will not remove a single level. At the outputs of the elements And 6, OR 12, the counter 17, And 8 are zero levels, and at the output of the element NOT 14 - single

level, bus zero code 19, the device is reliably blocked, bus zero is present on bus 20, and input pulse 18 does not affect the device,

,

Before starting work on tires 19

The binary code, other than zero, is entered, which corresponds to the delay value.

A non-zero code is entered into the counter 17. At the output of the element OR 13, a single level appears, which unlocks trigger 4 and trigger 1 through the element 9.

When the input pulse arrives, trigger 1 is triggered. In this case, at the forward output of trigger 1, a difference from zero to one appears, which passes through the OR element 12 to the C input of the D-trigger 3. If at this moment D the input is a single signal level from the output of the generator 16, the D-trigger 3 is set to one, and vice versa, if the D-input has a zero level from the output of the generator 16, then the D-trigger 3 remains in the initial state, In this In the case of (FIG. 2), D-trigger 3 is set to one e. In this case, the And 5 element is blocked by the zero level of the D flip-flop 3, and the And 6 element is unlocked by the single level of the D-flip-flop 3 Inverted element NOT 15 clock signals (shifted by half of the period, and in the clock signals of the duration of positive and negative pulses equal) through the elements of AND 6 and OR 10 begin to flow to the subtracting input of counter 17, the zero level of the inverse output of trigger 1 blocks the element AND 7, while at its output there is a zero level that passes through the element OR I1 to the input of the rez pisi counter 17, zero input level write enable blocks 17 in the counter data inputs D ,,,,. , Djj and allows the conversion of pulses. The counter 17 produces a subtraction unit from the content each time on the leading edge of the signal at the subtractive input. When the counter 17 reaches the zero state, at the moment of the end of the clock pulse, a signal appears at the output of its clock output, on the leading edge of which the forming trigger 4 is triggered, forming a leading edge of the delayed output pulse on the bus 20. The zero level of the inverse output of the formative trigger 4 passes through the element AND 9 and returns the trigger 1 to the initial state. In this case, the output ele5

The OR of 12 is set to zero, and the unit level of the inverse output of trigger 1 passes through the elements AND 7 and OR 11 to the input 5 of the recording resolution, and overwrites the code from the buses 19 to the counter 17 and simultaneously blocks its subtracting input. At the end of the input signal at the output

NOT 14 appears a difference from the zero level to the unit one, by which the trigger 2 is set to the unit state. At the same time, at the output of the ISH 12 element, a differential from a zero level to a single one is formed, according to which the D-t.rigger 3 returns to its initial state (the input signal ended at the time of the pause between clocks

0 m pulses, t, e, at this moment on the D-input of D-flip-flop 3 there was a zero level of the output of the generator 1b). As a result, the AND 6 element is blocked, and the generator 16 pulses pass through the AND 5 and OR 10 elements to the subtracting input of the counter 17, and the unit level from the recording resolution output is removed. Counter 17 likewise calculates the clock pulses to the zero state and at its output a pulse appears, by which the forming trigger 4 returns to the initial state, forming on the bus 20 the rear of the scientific research institute the front of the delayed output

signal. The zero level of the direct output of the forming trigger 4 returns the trigger 2 to the initial state, in which the initial state

0, the elements OR 12, AND 7 and OR 11 are returned. At the same time, the code 17 is entered into the counter 17 and the counter 17 is locked, i.e. device goes to source

5 uchy mode. The next input pulse repeats the process of forming a delayed pulse i

0 In the proposed device, the accuracy of the formation of the delayed pulse of the prototype is preserved, since the operation of the counter 17 occurs in the same way as the positive differences

5 inverted clock signal, or non-inverted. The choice of only one of the two clock signals occurs also at the moment of arrival of the input pulse.

0

With the help of a code assigned to the buses 19, discrete control is performed of the selection of the output pulse delay. The discrete delay adjustment is set only within the duration of the input signal. If an input signal is inputted to input 18, the duration of which is less than the duration of the clock pulse or if the delay code set on bus 19 exceeds the duration of the input signal, then in this case the formation of a delayed pulse does not occur. The blocking is carried out by the element And 8, which is triggered by coincidence-510. unit levels of the direct output of the trigger 1 and the element NOT 14. The presence of a single level at the direct output of the trigger 1. indicates that the counter 17 and the forming trigger 4 did not form the leading edge of the delayed pulse, and the unit level of the element 14 indicates that the input the signal has ended.

The single output level of the AND 8 element occurs through the OR element 1J stops counting the counter 17 by entering a code from the buses 19. A single output level of the And 8 element indicates that the device has detected a failure of the 19 bus delay code and the input signal duration. To return the device to its original state, it is necessary to submit a zero code to the tires 19. To continue the work, an input signal of the required duration must be fed to the bus 18.

Claims (1)

Invention Formula A controllable pulse delay device containing a forming trigger, a clock pulse generator, the output of which is connected to the D-input of the D-flip-flop, the input of the first element H and through the second element NOT with the input of the second element AND, the second inputs of the first and second elements AND are connected respectively to the inverse and forward outputs of the D trigger, and the outputs through the first element OR are connected to the read input of the counter, the information inputs of which are connected to the code buses, the device input is connected to the counting the input of the first trigger and through the first element is NOT to the counting input of the second trigger, the outputs of the third and fourth elements AND are connected to the inputs of the second element OR, the output bus is connected to the forward output of the forming trigger Pa, characterized in that, in order to expand the scope of use due to the possibility of working with zero delay codes, and increasing reliability due to the reduction in the number of elements and blocking the device if the input signal duration does not match the selected delay range, the fifth element is entered into it, the third and fourth elements of the ШШ, and the inputs of the third element OR are connected to the direct outputs of the first and second triggers. and the output is connected to the C-input of the D-flip-flop, the inputs of the third element And are connected to the inverse outputs of the first and second triggers, the inputs of the fourth element And are connected respectively to the direct output of the first trigger and the output of the first element NOT, the code bus is connected to the inputs the fourth OR element whose output is connected to the reset input of the forming trigger and to the input of the fifth AND element whose output is connected to the reset input of the first trigger; the counter output is connected to the counting input of the forming trigger, direct and inverse output Which are connected respectively to the reset input of the second trigger and the second input of the fifth element AND, and the output of the second element OR is preset to the input 40 45 50 razrecheni counter entries. sixteen. I I I I I I I I 75 YU I I I I I I I t I I I I I I I I I I 11 nJ ruiLrrrLTb.  I l M I I AL7 4  2 .2 Compiled by A.Titov Editor L.Pcholinska Tehred.Hodanich Proofreader V. But ha Order 7915/56 Circulation 922 Subscription VNIIPI USSR State Committee. for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4