SU1336216A1 - Pulse-delay device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in an information processing and control h.h. system. The purpose of the invention — extending the functionality — is achieved by adjusting the magnitude of the delay time in proportion to the change in the follow-up period of the input pulses. To do this, a delay element 1, a counter 3, a trigger 7, a logic element AND 8, a second counter 9 with presetting codes are additionally introduced into the device. In addition, the device contains trigger 2, memory register 4, divider 5 with variable division factor, counter 6 with preset code, write bus 10, input 11 clock pulses, device input 12 and output 13. In this device, when the period value changes following the input pulses, the magnitude of the generated time delay is proportional to this change, which extends its functionality. 1 il. & co oo: rsD 05 13

Description

The invention relates to a pulse technique and can be used in information processing and control systems.

The purpose of the invention is to expand the functionality due to the possibility of adjusting the magnitude of the delay time in proportion to the change in the follow-up period of input pulses.

The drawing shows a structural diagram of the device delay pulses.

The device contains a delay element 1, the first trigger 2, the counter 3, the memory register 4, the inputs connected to the bits of the counter 3, the divider 5 frequencies with a variable division factor, the input of the zero setting of which is connected to the output of the first trigger 2, and the output to the counter input of counter 3, the first counter 6 with a preset code, the information inputs of which are connected to the outputs of memory register 4, the second trigger 7, the unit setup input connected to the output of delay element 1 and the unit setup input of the first trigger 2, as well as to the inputs of the installation of zero counter 3 and counter 6 with preset code, logical element 8, the first input of which is connected to the rewrite input and output of the first counter 6 with preset code, the second counter 9 with preset code, counting input connected to the output of the logic element And 8, and the rewrite input connected to the output of the second trigger 7 and the second input of the logic element And 8, bus 10 records connected to the outputs of the bits of the second counter 9 with preset code, 11 clock inputs, connected to the counting inputs of the frequency divider 5 with variable division factor and the first counter 6 with a preset code, device input 12 connected to the zero set input of the first trigger 2 and the register 4 overwriting memory, output 13 device connected to the input of the zero setting of the second trigger 7 and the output of the second counter 9 with the preset code.

The delay device and pulses works as follows.

In the initial state, the input 12 receives pulses with a constant follow-up period. At bus 10 records there is a code corresponding to the value of the initial time delay. The counting inputs of the frequency divider 5 with a variable division factor and the first counter 6 with preset code receive clock pulses from input 11. The first counter 6 with preset code generates pulses, the period of which is determined by the code present on its information inputs (working

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This mode is performed in this mode by applying the output impulse of counter 6 with presetting the code to its input overwriting the time setting value). A review of the operation of the time delay device starts from the moment when the first trigger 2 is in the single state, and the second trigger 7 is in the zero state. In this case, counter 3 counts clock pulses arriving at its counting input through a frequency divider 5 with a variable division factor, and the second trigger 7 blocks the AND 8 logic element and the second counter 9 with a preset code for the rewrite input.

When the next input pulse arrives at the device 12 input, the trigger 2 is set to the zero state, blocking the frequency zero divider at the installation input zero with a variable division factor. Counter 3 stops counting pulses. In register 4 of memory from counter 3, the code corresponding to the measured last period of the input pulses is written, which is equal to

 Tta

whereT is the value of the period of the following clock pulses at the input 11;

N is the division factor of frequency divider 5.

At the same time, the input pulse arrives at the delay element 1, which makes it possible to carry out advance rewriting of information from counter 3 to memory register 4. From the output of the delay element 1, the pulse arrives at the first trigger 2, sets it to one state, and to counter 3, sets it to the zero state — at the same time, a frequency divider 5 with a variable division factor and a divided clock frequency are released at the zero input. its output is fed to the input of counter 3, which again starts counting pulses, measuring the follow-up period of the input signals. The pulse also arrives at the first counter 6 with the preset code, sets it to the zero state — at the same time, it begins to re-generate a sequence of pulses, the follow-up period of which is determined by code K rewritten into register 4,

t t. V t -8.

  ° T.-NN

In addition, the pulse arrives at the second trigger 7, sets it to the single state — this unlocks the AND 8 logical element at the second input and writes the M code corresponding to the initial time delay to the second counter 9 with the code preset.

Pulses from the output of the first counter with presetting code 6 through the logical element I 8 unlocked on the second input arrive at the counting input of the second counter 9 with presetting the code and this counter starts counting the clock pulses. At the moment when the second counter with preset code 9 counts the recorded number of pulses and sets to the zero state, a pulse delayed in time relative to the input signal appears at its output, which arrives at output 13 of the delay device and at the input of setting zero of the second trigger 7. The latter is set to the zero state, blocking the logical element I 8 at the second input and the second counter 9 at the rewrite input with presetting the code. Thus, the pulse delay device returns to its original state. In this case, the value generated by the second counter 9 with presetting the time delay code is equal to

- T

 sch

m-m

with the arrival of the next input pulse at input 12, the cycle of operation of the pulse delay device is repeated.

When the input signal frequency changes, the operation of the device differs from that described in that the output of the bits of counter 3 changes the code (it corresponds to the value of the changed input period), which is written to memory register 4. In this case, the period of the pulses from the output of the first counter 6 is changed with a preset of the code and, therefore, the time interval formed by the second counter 9 with the preset of the code is changed.

In the proposed device, the pulse delay, as well as the known change in the value of the time delay (with constant values of the input period Tg and the division factor of the frequency divider 5) is proportional to the code present in the write 10, i.e.

N const Gvh const.

By changing the value of N, the scale of the coefficient of proportionality between Tjj and T is regulated, and, moreover, when the value of the period of following the inputT is changed

Compiled by A. Titov

Editor .m. BlanarTehred I. VeresKorrektor A. Tsko

Order 3814/55 Circulation 901 Subscription

VNIIPI USSR State Committee for Inventions and Discoveries

1 13035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, ul. Project, 4

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pulses, the magnitude of the generated time delay (at constant values of the M code on the 10 write buses and the division factor of the 5 N frequency divider) is proportional to this change, i.e. Tech N const M const.

which extends the functional capabilities of the pulse delay device.

Claims (1)

Invention Formula A nMnyvibcoB delay device, a variable frequency divider with a variable division factor, a memory register, a first counter with a preset code, and a first trigger, the output of which is connected to the input of a zero divider with a variable division factor, characterized in that functionality due to the possibility of adjusting the delay time is proportional to the change in the period of the following pulses, a delay element, a counter, a second trigger, a logic element are introduced into it t and the second counter with preset code, and the device input is connected to the input of the zero setting of the first trigger, the memory register register overwriting input and through the delay element to the installation inputs of the first and second triggers, with the installation inputs of the zero counter and the first counter with preset code, the clock input of the device is connected to the counting inputs of a frequency divider with a variable division factor and the first counter with a preset code, the output of the frequency divider from changes The dividing coefficient is connected to the counter input of the counter, the outputs of the bits of which are connected through the memory register to the information inputs of the first counter with presetting the code whose output is connected to the rewriting input of this counter and the first input of the logic element whose second input is connected to the output the second trigger and the rewrite input of the second counter with the preset code, the counting output of which is connected to the output of the logic element, and the information inputs are connected to the write buses si, and the output is connected to the setup input zero of the second flip-flop and is the output of the device.