SU1334108A1 - Device for tolerance check of frequency - Google Patents

Abstract

The invention relates to automation and measurement technology and can be used in digital tracking systems for tolerance control of frequency. The aim of the invention is to expand the scope and simplify the device. The device contains a reversible counter 1, elements I 2 and 3, blocks 4 and 5 with 1 synchronization, code setters 6 and 9, a pulse generator 7, controlled frequency divider 8, delay element 10, triggers 11 and 12, or element 13. K The control object 14 is connected to the device. The device provides the ability to control the frequency by the magnitude of the relative rather than absolute error. At the same time, the value of the set tolerance is not related to the value of the measured frequency, which expands the field of application of the device. 1 il. (L 00 SLE

Description

 , one

The invention relates to automation and measuring technology and can be used in digital following electric drives for the tolerance control of the rotational speed of an actuator shaft.

The purpose of the invention is to expand the field of application and simplify the device for tolerance frequency control.

The drawing shows a block diagram of the device.

The device contains a reversible counter 1, the first 2 and the second 3 elements And, the first 4 and second 5 blocks of synchronization, a code setpoint generator 6 for the tolerance for the upper limit, a generator of 7 clock pulses, a controlled frequency divider 8, a tuning unit 9 for the tolerance value, element 10 delays, first 11 and second 12 and triggers and element OR 1

The device works as follows.

The work cycle begins with writing to the reversible counter 1 with a pulse from the controlled frequency divider 8 over the element 10 of the delay of a certain number K coming from the code set.

The value of tolerance on the upper 30 f о is the number 14, the number preliminarily recorded is at the same time as the output of the half-output. in the reversible counter 1, the reversible counter 1 will be set to increase or decrease, the level at which the dependences of the 2 and 3 are less or more is open. Through the element of the measured frequency f of the reference frequency AND 2 from the synchronization unit 4, 35 s fj are received. When writing to the reversible counter-short pulses of the reference frequency g at the input of the trigger 11 and to the element OR 13. These pulses with the leading edge set the trigger 11 to a state in which the reversible counter 1 produces the addition of incoming pulses, and dropping through the element OR 13, this pulse is recorded in a reversible counter, thereby increasing the number recorded in it. Element 3 from the synchronization unit 5 receives short pulses, the measured frequency f, leading the trigger edge 11 to the opposite state, in which the reversing pulses 3 are subtracted in the reversing counter 1 after these pulses 13 decay the element OR 13, the number written in the reversible counter, decreases.

The frequency pulses at the outputs of the generator 7 are shifted relative to each other, and in blocks 4.5

assigning pulses of frequencies f ,,, and f to these mismatched pulse sequences, which excludes the simultaneous appearance of pulses of frequencies fg and f at the inputs of the trigger 11, and consequently, malfunctions in its operation.

In case of equal frequencies f and f. the number written in the reversible counter 1 will pulse around one level, the pulse of frequency fg increases this number by one, and the incoming pulse of frequency f again restores this number. In this case

When the next pulse from the controlled frequency divider 8 arrives, the logic level at the overflow output of the reversible counter 1 will not change, the trigger 12 by the pulse from the controlled frequency divider 8 will not overturn, and the indicator 15 will indicate that the measured frequency does not exceed the tolerance limit. The impulse from the controlled frequency divider 8, having passed through the element 10, the delay, again writes the number K to the reversible counter 1 and the cycle of operation of the device repeats,

In case f differs from

The maximum or minimum value of the number 1 changes the logic level at its overflow output, while the passage of pulses through the AND 2 and 3 elements is prohibited, and the corresponding logic level is set at the input D of the flip-flop 12. The next impulse from the controlled splitter 8 frequency will make a trigger 12, because the level at its input D has changed. Indicator 15 will: indicate the output of the measured frequency f beyond the set tolerance, Delayed

the impulse from the controlled frequency divider 8 will again write the number K into the reversible counter 1 and the new cycle of frequency comparison will begin.

Let us show mathematically that the device allows the frequency tolerance to be measured by the magnitude of the relative error.

Let foj.7 fo, the number written in the reversible counter decreases in proportion to the frequency difference f - fg over time (fo; .rfo in the reversible counter

the minimum value of the number will be recorded, which will be fixed by the device

equality control

B ki

foc-fo fc.

where K - the value of the code coming from the code unit 9 tolerance values. Transform this equality, we get;

. ± fo K,

f -f By definition 8 -2f-- -

about

where 0+ is the relative measurement error at the upper limit, thus:

, 5 ± - k.

Let f .fg be a number in this case. the recorded in reversible counter 1 increases in proportion to the difference and during K - / () it will record the maximum value here of the number of pulses that is needed to fill the reverse counter with a capacity N from the value K to the maximum value.

Similarly to the previous case, we obtain:

e- fo for -

f tf about K.

where is the relative measurement error at the lower limit. The total relative error 8 recorded by the device is determined from expressions (1) and (2),

S & +8 --- + - ± i --- к, к, к,

Learning that the sum K + K is equal to the capacity of the reverse counter N, reduced by one (due to the fact that a number is written in it), expression (3) can be written in the form:

p CZK + K-N-1

and - y-- -k

From this expression, it follows that the monitoring device allows

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35

40

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lead tolerance control frequency of the magnitude of the relative error. The value of the controlled tolerance does not depend on the value of the measured frequency, but is entirely determined by the parameters of the control device. Given the value of K | With a code coming from setpoint 9 with a constant capacity N of reversible counter 1, the controlled tolerance can be varied over a wide range, and by changing the code K coming from setpoint 14, the upper limit tolerance and the total tolerance can be set independently of each other .

Claims (1)

Invention Formula A device for frequency control, containing a reversible counter, the first and second elements And, the indicator, the first and second synchronization blocks and the clock generator, the outputs of which are connected to the first inputs of the first and second synchronization blocks, the second inputs of which serve as inputs to the device to connect the control object , and the outputs are associated respectively with the first inputs of the first and second elements AND, the second inputs of which are connected to the overflow output of the reversible counter, differing from the fact that Expanding the application area and simplifying the device, a controlled frequency divider, first and second setters, a delay element, first and second triggers, and an OR element, whose output is connected to the counting input of a reversible counter, are entered into it, and the first and second inputs are connected respectively to the outputs of the first and second elements AND, respectively, also connected respectively to the reset inputs and the installation of the first trigger connected by the output to the control input of the reversible counter, the first installation input to is connected with the output of the second code master, whose input is the first information input of the device, the second installation input of the reversible counter is connected to the output of the delay element, whose input and the C input of the second trigger are connected to the output of a controlled frequency divider connected by information 51334108b the input with the output of the first block by the syn- thetic input of the device, the output of the replication, and the control input - the replenishment of the reversible counter with the output of the first code setter, one with the input of the second trigger, whose input serves as the second information g indicator input.