SU500517A1 - Digital pulse width controller - Google Patents

Description

one

This invention relates to digital automatic control systems.

Known latitude-impulse regulator. contains an analog-code converter connected in series, the first register, the first rewriting unit and the counter of the controlled parameter converter, the second register connected in series, the second rewriting unit, the counter of the software installation, and the pulse generator with the first input connected frequency divider, a. to

the second one is successively connected; the second divider and two delay lines, a read trigger, the outputs of which are connected to the inputs of the actuator, and a sign,

; However, this regulator peculiar to. Limit g-1ena application area and low control accuracy,.

The purpose of the invention is to improve the accuracy of the controller,

This is due to the fact that in it, a software installation trigger, a ban trigger, a trigger

No pulse width signal, AND, OR elements, additional delay line and switch, and the output of the second frequency divider is connected to the single input of the inhibit trigger, the output of the first frequency divider is connected via the first AND element (the other input of this element is connected to the single trigger output forming a pulse-width signal) with the input of the counter-converter of the adjustable parameter, and through the second element I (to the other input of which the unit output of the trigger of the installation is connected) with another input of the counter-transducer Azovatelts software installation. The single output of the inhibit trigger is connected through the third element I (the other input of which is connected to the output of the last discharge of the counter-converter of the adjustable parameter) is connected to the zero input of the trigger of the backdating pulse signal, to the input of the first element OR and through the fourth element I (to the other input of which is connected to the unit output of the trigger setup) - with the input of the second element OR,

The output of the second delay line is connected to the moves of the rewriting blocks, additional delay time.JH through the fifth element I (the second bit of the first storage register is connected to the other input of the first register) -s with a single sign trigger trigger input, the output of the prohibition trigger is connected through a natural element And (to the other input of which the last one is connected, the program converter counter. Settings) -10 with the input of the third OR element and with the input of the fourth OR element. The output of the additional delay line is connected to the zero input of the inhibition trigger, to the single input of the trigger for forming a 15 pulse width signal, through the seventh AND element (to another input of which the zero and the zero sign trigger output is connected) to the first and third ILIG elements, and through the eighth AND element (to another20

the input of which is connected to a single output of the sign trigger) - with the second and fourth elements OR. The outputs of the second and third elements OR are connected to the single and zero trigger inputs of the readout 25, respectively, the output of the first and fourth OR elements with the single and zero inputs of the signal setup trigger, the output of the actuator through the switch is connected to the converter input analog-code and the other output of the switch is connected to the input of the second storage register.

This embodiment will improve the accuracy of the digital pulse-width controller and expand its scope. In the drawing given the proposed device. It contains the analog-code converter 1, the first and second registers 2 and 3, the first and second blocks of the census 4 and 5, the counter-converter 6 of the controlled parameter, the counter-converter; 7 software installation, control channel 8, switch U, .. control unit 10, pulse generator 11, first and second frequency dividers 12 and 13, first 14 and second 15 delay lines, trigger-1 inhibit bar 16, first, second , third, fourth, fifth, sixth, seventh: and eight "And 17-24 elements, additional delay line 25, sign trigger 26, pulse width signal trigger 27, setpoint trigger 28, first, second, the third and fourth elements 55 OR 29-32, read trigger 33, output block 34, amplifier 35, actuator, and Spare device36. The regulator works as follows.

The mismatch signal of the remote control of the tracking system (x; where U is the program setpoint, and is the feedback signal sv -

 - .OS

3Hjraven D os at My O

D Uoc at Nose O

From the output of the transducer 1 to the input of the first register receives a binary code containing information about the position of the executive body 36 (signal Kos). Via the control channel 8, the second | register 3, containing P bits, is entered by a serial or parallel program setpoint code containing information about the required position of the actuator. The adjustment range is conventionally divided into positive and negative sections. The number 2, where P is the number of bits of registers 2 and 3, corresponds to the zero position of the executive body. The total number greater than 2 i corresponds to the negative position of the executive body (unit of register bit of register 2) and, conversely, the total number less than 2 corresponds to., The positive position of executive body ((zero sign bit of register 2).

At the beginning of the adjustment cycle, the first pulse from the output from the divider 13 sets the inhibit trigger 16 to one state. After passing through the first delay line 14, the impulse leads counters 6, 7 and the sign trigger 26 to the initial (zero) state, while the single trigger state 16 excludes the passage of possible overflow signals of counters 6 and 7 to read trigger 33. After passing the delay line 15, the pulse rewrites the contents of register 3 into counter 7, enters the contents of the sign bit of register 2 into trigger 26. At the same The pulse converted in the first block of rewrite 4 code is recorded in the counter 6. Block 4 implements the function of obtaining the code code, where Xj is the unit state of the tth digit of the register 2, /

 1.2 ... L 1; Y is the unit state of the sign bit of register 2, when the register is working with the measured value expressed in the direct code (for subtraction) or the function when the register is working with the measured value, expressed in the additional code (for addition).

Claims (1)

Depending on the state of the trigger 26, the values of U and | Woc | , or their subtraction. The running time of the program setpoint recorded in register 3 corresponds to one HHiHOMy condition of trigger 33 and the positive polarity of the output pulse of amplifier 35, therefore the measured value having a positive value must be subtracted from the programmed value, setpoint (L and and - iMocI) , and the measurable quantity, having a negative value, is added to it (and {U + lUod) Let the measurable quantity negator 3 26 have a single state. Upon the arrival of a pulse from the output of the delay line 25, the triggers 27.33 are set to one, and the trigger 28 is set to zero. Due to the fact that trigger ger 27 is in a single state. research, through the element U 17; From the divider 12, the pulses go to the input of the counter 6 of the measured value by the overflow signal, the trigger 27 is transferred to zero, and the trigger 28 is in the single state .. The unit state of the latter ensures the passage of pulses through the U 18 element from the divider 12 to the input of the counter 7. After working off the counter 7; programs aby the settings with the overflow signal are zeroed: triggers 28 and 33. Thus, at the output of trigger 33, the time intervals corresponding to the operation of counters 6 and 7 were added. For the remainder of the overflow of counter 7, the control cycle 33 is in the zero state, which corresponds to negative output potential of the amplifier 35 ,,. In the absence of overflow of the counter 7 within the cycle, the trigger 33 is in a single state during the whole cycle (positive polarity of the output pulse of the amplifier 35). When the measured value Uoc O is positive, trigger 26 is in the zero state. Upon the arrival of the pulse 1c, the delay line 25 triggers 27, 28 are set to one state, the trigger 33 is zeroed. The single state of the flip-flops 27 and 28 ensures the arrival of pulses from the output of divider 12 to the inputs of counters 6 and 7. In case the overflow signal of counter 6 arises before the overflow signal of counter 7, then a flip-flop of trigger 33 from the zero in one condition. . The overflow signal of the counter 7 triggers 28 and 33 are zeroed out. Thus, the interval of the counter 6 operation was subtracted from the interval of the counter 1k 7, corresponding to the single state of trigger 33, In case the overflow signal of the counter 7 occurs earlier than the overflow signal of the counter 6 (subtracted modulo more decrementable), then this signal confirms the zero state of the trigger 33, the trigger 28 is set to the zero state. The overflow of the counter 6 that does not pass through the element 20 to the single input of the trigger 33, i.e. during the whole control cycle the trigger 33 is in the zero state (negative polarity of the output pulse of the amplifier 35), the described device can perform the functions of the known digital controller, and the analog error signal. For this, the channel 8 of the controller connection with the control digital device is disconnected, the actuator 36 is disconnected from the converter 1, the 3 inputs into the lower register bits of the register 3, into the lower bit - units using the device 9, which is a conventional switch, with each setting input of register 3 being supplied with a high or a low potential level depending on which digit is to be written,. This setting of register 3 corresponds to the absence of governing influence. The operation of the controller in this case is a special case of the described operation of the proposed device (when writing the number 2 to the register 3), and the error signal in analog form is sent to the converter 1. DETAILED DESCRIPTION OF THE INVENTION A digital pulse-width controller containing an analog-code converter connected in series, a first hyster, a first rewriting unit and a variable parameter converter, a second register connected in series, a second rewriting unit, a software setpoint converter, and a pulse generator one output of which is connected to the first frequency divider, and to the second - serially connected second divider and two delay lines, a trigger trigger, whose outputs Connected to the inputs of the actuator, and the sign trigger, which is recorded in order to improve the accuracy of the controller, it contains the {) program setpoint, the inhibit trigger, the pulse width trigger, the elements AND, OR, the additional line delays and switch, npifneM output of the second frequency divider is connected to the single input of the inhibit trigger, the output of the first frequency divider connects through the first And element, to the other input of which the single output of the trigger is formed signal, with the input of the counter-converter of the parameter being regulated, and through the second element to another input of which a single output of the setpoint trigger is connected, with another input of the counter of the converter of the software setpoint, a single output of the inhibit trigger through the third element I, the other input of which is connected to the output of the last bit of the counter-converter of the adjustable parameter, connected to the zero input of the trigger forming a pulse-width V. signal, to the input of the first, OR element and through the fourth element AND, to to the other input of which the unit output of the setpoint trigger is connected, with the input of the second element OR, the output the second delay line is connected to the inputs of the rewriting blocks, the additional delay line and through the fifth element I, to the other input of which is connected to the last The SRI of the first storage register, with a single input of a character trigger, the zero output of the inhibit trigger is connected through the sixth AND element, to the other input of which the last bit of the software setpoint transducer counter is connected (, to the input of the third OR element and to the fourth OR input, additional line output the delay is connected to the zero input of the inhibition trigger, to the single output of the trigger of the formation of the pulse-width signal via the seventh And element, to the other input of which the zero output of the sign trigger is connected , with the first and third elements OR, and through the eighth element AND, to the other input of which the unit output of the sign trigger is connected, with j the second and fourth elements OR, the outputs of the second and third elements OR are connected to the unitS the zero and zero inputs of the read trigger, respectively, the output of the first and fourth elements OR with the single and zero inputs of the signal setpoint trigger, the output of the actuator through the switch is connected to; the analog-code input to the converter input and the other output of the commutator is connected to the input of the second register.