SU661609A1 - Logic storage - Google Patents

Description

 - / The invention relates to the field of storage devices. One of the known devices has in its accumulator a set of logical cells that differ from the rest of the accumulator cells in the more complex firmware of control and output buses t1. This requires not only complicating the structure of the storage device of the storage device, increasing the accumulator control electronics, but also organizing the operation of the device according to a special program. Of the known devices, the most technical solution to this invention is a logical storage device containing an address register connected to decoders, the outputs of which are address and the write and read address keys are connected to the inputs of the drive connected to the write bit driver and through read amplifiers connected to the register word, the control unit 2. The disadvantage of this device is low functionality, since it can realize only two modes of operation s (Read with regeneration, Write with cleaning) and perform only its own classic functions; writing information to the drive, storing and issuing (reading) information from the drive's bluck. It; also reduces the field of application of the device. Another disadvantage of the device is the inefficient use of the cycle time of the device, since it excludes the possibility of reading information from one drive cell and writing other information to the same or any other drive cell during one cycle of the device access, which reduces the speed of the device. The object of the present invention is to expand the field of application and increase the speed of the device. The goal is achieved by the fact that the device contains triggers, a reset forming unit and ele. The cops are AND and OR, the first output of the control unit is connected to the first inputs of the first and second elements AND, the outputs of which the first element OR are connected to the enabling inputs of the address key and the first input of the second element OR, the second

the output of the control unit is connected to the first inputs of the third and fourth elements AND, the outputs of which through the third element OR are connected to the enabling inputs of the address keys of the record and to the second input of the second element OR whose output is connected to the enabling inputs of the address drivers, the second inputs of the third element and the third elements And connected to a single output of the first trigger, - the second inputs of the second and fourth elements And connected to the One-way output of the second trigger, the third inputs of the second and fourth elements And connected with Respectively to the third and fourth outputs of the control unit, the outputs of the second and fourth elements AND are connected via serially connected fourth element OR and a reset forming unit to the first input of the fifth OR element, the output of which is connected to the installation inputs of the address registers and the word, the second input of the the OR element is connected to the fifth output of the control unit and the zero inputs of the flip-flops, the single inputs of which are connected respectively to the inputs of the control unit.

The scheme of the proposed device is shown in FIG. 1, in FIG. 2 shows a diagram of his work in various modes. The device contains (see Fig. 1) address register 1 with input 2 set to zero, decoder 3, address drivers with enable input 5, accumulator 6 on multihole ferrite platinum, address read keys 7 with enable input 8, address write keys 9 with allow input 10, decoder 11, bit write drivers 12 with authorization input 13, read amplifiers 14 with gating input 15, word register 16 with input 17 set to zero. The device also contains a control unit 18 with command read inputs. 19, records 20, references 21, resolutions 22 and with outputs 3-28.

The device also contains a trigger, a 29-time temporary storage of the command signal, an inversion signal, a trigger 30 for temporarily storing the command signal, the operation mode, the AND 31 elements, the OR 32 elements, and the reset forming unit 33.

The first output 23 of block 18 is connected to the first inputs of the first and second elements AND 31, the outputs of which through the first element OR 32 are connected to the enabling inputs of keys 7 and to the first input of the second element OR 32. The second output 24 of block 18 is connected to the first inputs of the third and of the fourth element AND 31, the outputs of which through the third element OR 32 are connected to the enabling inputs 10 of the keys 9 and to the second input of the second element OR 32, the output of which is connected to the enabling inputs of the 5 drivers 4. The second inputs of the first and third elements AND 31 are connected to the single output of the first trigger 29, the second inputs of the second and fourth elements And connected to the single output of the second trigger 30, the third

inputs of the second and fourth elements

And 31 are connected respectively to the third 25 and fourth 26 outputs of block 18. The outputs of the second and fourth elements And 31 are connected through

Fourth element OR 32, b. 33, connected in series to the first input of the fifth element OR 32, the output of which is connected to the installation inputs of registers 1 and 16. The second

0 the input of the fifth element OR 32 is connected to the fifth output 34 of the block 18 and the zero inputs of the flip-flops 29, 30, the single inputs of which are connected respectively to the inputs 21 and 22

block 18.

The device works as follows. . ,

When accessing the device, the k inputs 19–22 of the control unit - 18 receive command signals that determine the operating modes of the device: Read with regeneration, Write with CLEAN, Read, Write. Read / write, /

5 In the Read with Regeneration mode, the Read and Inverting signals, respectively, are received at the inputs 19 and 21 of the control unit 18. The control unit 18 provides the following control signals to its outputs (see FIG. 2, a) S allowing the key to read — exit 23; write keys — exit 24; resolution of the bit shapers of the record, - at the output 27; reading amplification strobe at code 28; set to zero - exit 34; allow- shdy signal - output 25. As the input 21 of the control unit 18 is connected to the single input of the trigger 29, then

50 this trigger under the action of the signal Circulation is set to one state, and the resolution signal from its single output nocTynaesT to the corresponding inputs of the first and third elements And 31, allowing the signals C from the outputs 23 and 24 of the control unit to pass, nor 18 through the first and third elements And 31 and cooTBeTCTBsno, elements OR 32, on control

gQ inputs 8, 10, and 5, respectively, of the read keys 7, 9, and address drivers 4. In this case, two permitting signals arrive at the input S of the drivers in series: the first one in the read cycle and the second in

65 regeneration cycle. The trigger 30 is in the zero state, and the potential from its single output prohibits the passage of signals through the second and fourth elements and 31. At the same time with the signal Circulation on the address code buses, the address code that is stored on it enters the address register 1. The address is decoded by the decoders 3 and 11, each of them on. one of its outputs generates a start signal, respectively, the address driver 4, the start signal of the corresponding read key. 7 and the record key 9 of the same name. Since, on the permitting inputs 5, 8, 10 of these keys, there are resolving signals, the excited address driver generates pulses of the address reading current (first) and write (second) to the corresponding input of the accumulator 6, and the excited keys readings and writes commute at the appropriate time of their passage through the selected memory cell of accumulator 6. In this case, under the action of the first pulse of the address current, the parameters of the memory elements of the selected memory cell of the accumulator 6 change, and dnyh outputs accumulator 6 are output signals, which in the presence impulsa.stroba inlet 15 the read amplifiers 14 are converted into the read amplifiers in standard word signals. This word is entered into the register of the word 16 and from its outputs goes to the output busses of the device and to the corresponding inputs of the bit writers 12.

In the regeneration cycle, from the output 27 of the control unit 18 to the input 13 of the bit shapers of record 12, the resolution signal is received. If information of O is regenerated in the selected cell of the drive, the bit write driver corresponding to this bit is started and produces a pulse of write current that compensates for the effect on the memory element of the selected drive cell of the write current 6 . In this case, the switching of the memory element does not occur. If carried out, then det regeneration

The recording write driver does not produce a compounded discharge current, and the write address current (the second address current pulse) re-magnetizes the memory element to a state. As with regeneration,

and during regeneration

The bit write driver in the regeneration cycle generates an additional pulse of the installation current that does not coincide with the action of the address current (this pulse is not shown in Fig. 2).

switching memory element of state

in a state of destruction

The information on the register of the word 16 and on the register of the address 1 is reset to zero by setting the pulse to zero, 5 which from the output 34 of the control unit 18 goes to the corresponding inputs 17 and 2 of these registers through the OR element 32.

In Record mode with eyes

0, the inputs 20 and 21 of the control unit 18 receive, respectively, the signals Record and. The control unit 18 outputs the following control signals to its outputs.

5 (see Fig. 2, b): read key resolution - at output 23; permission of keys of record - at the exit 24; the resolution of the bit shapers of the recording is at output 27; installation, to zero - at exit 34; permitting

the signal is output 26. The operation of the device in the Record mode with cleaning is similar to the operation of the device in the Read mode with regeneration, with the exception of the following devices. In the reading cycle, when the Record with Clear mode is implemented, the strobe pulse does not arrive at the input of the 15 reading amplifiers 14, and the information read from the selected memory cell

0 drive 6, is not entered in the register of the word 16 (lost). At the same time, in the tact record on the input code buses, the words expose the code of the word, which is entered in the register of the word

5 16 and from its outputs goes to the corresponding inputs of the bit shapers of the record 12, each of; the bit formers of which runs and produces the write current at write O, and does not produce the write current when writing ..

The information on the register of the word 16 and on the register of the address 1 resets c to zero in the same way as in the mode

5 IReader with regeneration, impulse set to zero.

In the Read mode, the signals Read and

0 Operation mode. The control unit 18 outputs the following control signals (see FIG. 2, c): output, reading key decision — at output 23, resolution of write keys — at output 24; strobe reading amplifiers at output 28; output enable signal 25.

Since the input 22 of the control unit 18 is connected to the single input trigger Q 30, then this trigger under the action of a signal The operating mode is set to one, and the enabling signal from its single output goes to the corresponding inputs of the second and fourth elements

And 31, allowing the passage of signals from the output 23 of the control unit 18 through the (Second element AND 31 and the corresponding elements OR 32 to the control inputs 8 and 5, respectively, of the reading keys 7 of the address drivers 4 (first pulse). At the output 26 of the control unit 18. There is no signal, and therefore the enable signal does not arrive at the input 10 of the write keys 9. Accordingly, there is no second enable signal at the input 5 of the address drivers - i. - The trigger 29 is in the zero STATUS, and the potential from its single output prohibits the passage The signals from the inputs 23 and 24 of the control unit 18 through the first and third elements And 31. Simultaneously with the signal, the mode of operation for the address code buses enters the address register 1 at the input of the address code, which is not stored in. The address code is deciphered by the digiters 3, 11, each of which at one of its outputs, respectively, generates the start signal of the address driver of block 4, the start signal of the corresponding read key 7 and the write key of the same name 9. Since the decisive signal is present at the input 8 of keys 7, and at the entrance 5 hell If only the first permissive pulse is present, then the excited address driver generates the corresponding read current current pulse (first) for the corresponding VCD drive 6 — ONLY the read key switch 7 commutes its passage through the selected cell. - b. At the same time, under Addressing Current, the parameters of the memory cell MeHTQB of the selected cell are changed and output signals appear on the double outputs of accumulator 6, which, in the presence of a pulse from the horn at the input 15 of read amplifiers 14, are converted into body forces reading in the standard word signals a V This word enters with the register word 16 and from its outputs goes to the output buses of the device and to the corresponding inputs of the bit writers of the record 12. The information on the register of the word 16 and the address register 1 is reset to Hojfe- momentum set to zero, which is formed in duration immediately after the end of the pulse of the address current reading by the reset formation unit 33, the input from the terminal through the element OR 32 receives a signal from the output of the second element AND 31. In connection with the absence of the second pulse of the current current and the enabling signal , at the input of 13 bit shapers of the record, the 12 clock cycle of regeneration during the operation of the device in the reading is not performed. 8 In the Record mode, the signals 0 and 22 of the control unit 18 are recorded. Records of the corresponding signals. The operation mode of the Local Control Unit 18 outputs the following control signals (see ell. 2, d): resolution of read keys at output 23, resolution of key locks - output 24, the enabling signal - output 26; the resolution of the bit writers of the record is at the output 27. At the same time, the trigger 30 is set to the one state when the Read4 mode is executed, and the trigger 29 is set to zero. However c. difference from the mode Read to RECORD instead of allowing the signal at the output 23 of the control unit 18 to generate, the signal is at. output 26 of the same block, so the signal from output 24 of control block 18 through the fourth element AND 31 and the corresponding elements OR 32 goes to the enabling inputs 10 and 5, respectively, of the write keys 9 and the address drivers 4. In this case, the address driver generates only the second address pulse current (write cycle), and at the same moment of time, the corresponding record key is opened, which commutes the passage of this current through the selected memory cell of accumulator 6. Simultaneously with the enable signal of the write keys to the input code busses: words expose a code of a word that is entered into the register word 16 and from its outputs goes to the corresponding inputs of the bit formative block of Record 12, each of the bit formers of which starts and produces a write current for the write during the write and does not produce a write current when recording. The information on the register of word 16 and on the register of address 1 is reset to zero by setting impulse to the volt, which is formed in duration immediately after the end of the impulse of address write current by the reset forming unit 33, to the input of which through element OR 32 a signal comes from the fourth element And 31. In connection with the absence of the first pulse of the address current, the reading cycle when working from the device in the direction of the Record is not performed, which makes it possible to record information in any cell of the storage device without its preliminary cleaning. If word A was in the selected accumulator cell and B word is written into it, then after the Record mode is implemented, the C word is formed in this cell as a result of the logical OR function on A and B words. Read / Write mode (see FIG. 2, e) is a combination of the Read mode and the Write mode. At the same time, the command signals 18 are received at the inputs 19, 20, 22 of the control unit 18: Read, Write, Operating mode. The local expansion unit 18 bridges all the control signals necessary for the execution of the Read modes. Write separately: the read key resolution is at output 23; the resolution of the write keys is at output 24, allowing output signals 25 and 26; resolution of the bit format for the world record - output 27; the reading amplifiers strobe is output 28. In this case, the trigger 29 is in the zero state, and three germs 30 are in the single state, allowing passage of the pulses from the .23 and 24 outputs, respectively, through the Second and Fourth elements AND and the corresponding elements OR 32 Inputs 8, 10 and 5 of the keys for reading, writing and address drivers. In this case, just as in the. Read mode, the address shaper produces the first pulse of the address current, which did not read the information from the memory cell of drive 6, and then as well as the Write mode, the second pulse of the address current to write the read or any other information in the same or any other memory cell of accumulator 6, and the information on the address register 1 and the register of word 16 is entered at the beginning of the read cycle and, as in the read mode, is reset to zero at the end of this cycle, and then to the same registers in the beginning of the beat record The system records new information, which, as in Record mode, is reset to zero at the end of the recording cycle. Otherwise, the operation of the device in the Read-Write mode is similar to the operation of the signal device in the Record mode. Read and then. Thus, the described device allows to perform a logical function OR in the storage unit cell, which is impossible in the prototype, and read information from one storage unit cell. and recording any other information in the same or another cell during one cycle of the memory operation instead of the required time of the two cycles of the prototype 10 09 of the invention (Logical memory formula), containing the address register, connected to digital diffusers, whose outputs through address drivers and write and read address keys are connected to the inputs of a storage device connected to the bit driver of the record and connected to the word register, the control unit is different in that expanding the field of application and improving the speed of the device, it contains triggers, a reset forming unit and AND-OR elements, the first output of the control unit being connected to the first inputs of the first and second AND elements whose output through the first OR element is connected to the enable inputs of the reading address keys and to the first input of the second OR element, the second output of the control unit is connected to the first inputs of the third and fourth AND elements, the outputs of which through the third OR element are connected to the address enable inputs keys, records and from the second input of the second .OR element, whose output is connected to the enabling inputs of the address drivers, the inputs of the first and third AND elements are connected to the single output of the first Trigger the second inputs of the second and fourth elements of AND are connected to the single output of the second trigger, the third inputs of the second and fourth elements of AND are connected respectively to the third and fourth outputs of the control unit, the outputs of the second and fourth elements of AND are connected via series-connected fourth element OR and reset forming unit to the first input of the fifth OR element, the output of which is connected to the installation inputs of the address and word registers, the second input (the FIFTH element OR is connected to the fifth output of the control unit neither the zero inputs of the triggers, the single inputs of which are connected respectively to the inputs of the control unit. Sources of information taken into account during the examination. 1. Copyright certificate USSR 374604, cl. Q 06 F 13/08, 1972. 2. Automation; 5, 1972, pp. 76-79. :

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