SU1338094A1 - Clock-time synchronization device - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to improve noise immunity by reducing the effects of random phase shifts in the radio channel. The device contains a differentiating unit 1, the EL OR 2, the counting trigger 3, the ELTs 4 and 5, the phase discriminator (PD) 6, consisting of the EL 15 and 16 and the RS trigger 17, the counter 7 pulses, block of shift registers 8, block of multiplying 9 by weights, adder 10, shaper 11 correction signals, frequency divider 12, block of addition and elimination (BDI) 13 pulses and specifying grs 14. The target is achieved by introducing el OR 2, trigger 3, elet I 4 and 5, counter 7. of block of registers 8, block of multiplication 9, adder 10 and shaper 11, with the help of which in BDI 13, an indirect adjustment of the frequency of the pulses coming from grs 14 and, consequently, a change in the phase position of the pulses of the clock frequency at the output of the divider 12, Device. 2 f-ly is characterized by the performance of PD 6,1 hp ff, 2 ill. (L with QO 00 about (X 4

Description

113

The invention relates to telecommunications and can be used in systems for transmitting discrete information via radio channels for clock synchronization,

The purpose of the invention is to increase noise immunity by reducing the effect of random phase shifts in the radio channel.

FIG. Figure 1 shows the structural electrical circuit of the clock synchronization device; in fig. 2 is a structural electrical circuit of a correction signal driver.

The clock synchronization device contains a differentiating unit 1, the element OR 2, the counting trigger 3, the first 4 and the second 5 elements And, the phase discriminator 6, the pulse counter 7, the block 8 of the shift registers, the multiplier 9 by weights, the adder 10 , shaper 11 of correction signals, frequency divider 12, block 13 for adding and eliminating pulses, driving oscillator 14.

The phase discriminator 6 contains the first 15 and second 16 elements And and the RS-trigger 17.

Shaper 11 corrective

signals contains key 18, counter 19

pulses and switch 20.

The clock synchronization device operates as follows.

The input signal is fed to the differentiating unit 1 (Fig. 1), which produces narrow pulses corresponding to the front edges of the input signal. The pulses from the output of the differentiating unit 1 and the pulses from the output of the divider 12 are fed to the input of the counting trigger 3, which changes its state to the opposite on the leading edge of the input pulse. The signal from the output of the counting trigger 3 opens the key implemented on the first element I 4, the output of which forms a burst of pulses (with the frequency of the master oscillator 14). The number of pulses in a packet is proportional to the duration of the signal at the output of the counting trigger 3 (m, e, the phase mismatch between, the front of the input signal and the output signal of the clock synchronization device),

At the output of the second element And 5 a pulse is formed, corresponding to the second (in time) pulse, pos

Q

g

0 5

five

0

0

depending on the sign of the phase mismatch, this may be a pulse from the output of differentiating unit 1 or pulses from the output of counter 7. The pulse from the output of the second element And 5 is fed to the clock input of the block 8 of registers, triggered by the falling edge of this pulse . In phase discriminator 6, the first element I 15 separates the pulse from the output of differentiating unit 1, if it came before the pulse from the output of divider 12. If the pulse came first from the output of divider 12, then this pulse is selected by the second element 16 of the phase discriminator 6, The pulses from the outputs of the first 15 and second 16 elements And control the RS-trigger 17. The output signal of the RS-flip-flop 17 carries information about the sign of the phase mismatch.

At the output of the first element And 4, a pulse is formed, corresponding to the moment of termination of the packet of pulses at the output of the second element And 5. At the moment

the action of this pulse at the output of the phase discriminator 6 is present .1 or O, depending on the sign of the phase mismatch. The number of pulses from the output of the second element AND 5 is counted by counter 7, which performs the function of a serial to parallel converter. The pulse at the output of the first element 4 records the 7 number formed by the counter in the register block 8 and zeroes the counter 7. At the same time, the most significant (digit) digit of the number stored in the register block 8 is written 1 or 0 from the output of the phase discriminator 6. Thus, in block 8, a number is written with a sign corresponding to the magnitude and direction of the phase mismatch. Writing each new number to the register block 8 causes information shift in it by one bit. In this case, the register block 8 is a memory of the magnitude (and sign) of the phase mismatches at previous clock intervals.

The signed numbers from the outputs of block 8 of registers are fed to the inputs of block 9 of multiplication, which consists of permanent storage blocks (FUL). Each number from the outputs of the block of 8 registers arrives at the address inputs

313

corresponding PHB. At the same time, at the output of this FBL, information is given that was pre-wired at this address, namely, a number equal to the product of the address code by the corresponding coefficient. Thus, each number from the outputs of block 8 of registers is multiplied by a coefficient, the value of which is determined by the position of the number in the corresponding register of block 8 of registers, as a result of which a large contribution of the detuning value is obtained to the immediately preceding

clock intervals at the | 5 diode channel, are introduced sequentially

thirty

determining the necessary phase position correction.

The products of the mismatch values for the respective weights are summed by the adder 10, 20 at the output of which a number is formed with a sign that carries information about the required value and direction of correction of the phase of the clock pulses.

At the end of the pulse at the output 25 of the first element 4, the number from the output of the adder 10 is recorded in the counter 19 of the driver 11 (Fig. 2). At the same time, the key 18 is opened, through which the pulses from the master oscillator 14 arrive at the clock input of the counter 19 and reduce the number recorded in it. At the moment when the counter 19 passes through zero, a pulse is formed at its output, which closes the key 18. At the same time, at the output of the key 18, a packet of pulses is formed, the number of which is proportional to the magnitude of the required correction of the phase of the clock frequency pulses.

A burst of pulses from the output of the switch 18 is fed to the information input of the switch 20. Depending on the sign of the number at the output of the adder 10, the pulses from the information input of the switch 20 arrive at the corresponding correction inputs of the addition and elimination unit 13, to the clock input of which the pulses go oscillator 14. At the same time, in block 13 for adding and excluding pulses, the frequency of the pulses received from the master oscillator 14 is indirectly adjusted, and, consequently, the phase field changes Pulse clock pulse 55 ment And and RS-flip-flop, as well as vto40

, 45

50

the connected element OR, the counting three ger, the first element AND and the counter of 4-pulses, the second element AND sequencer of the correction signals connected in series, as well as the block of shift registers, the unit multiplying by weights and the adder, while the outputs of the differentiating block and divider frequencies are connected respectively to the first and second inputs of the OR element, the output of which is connected to the first input of the second element AND, the second input of which is connected to the control input of the phase discriminator and connected to the output the counting trigger, the output of the criminator's phase distance and the pulse discharge outputs are connected to the corresponding information inputs of the shift register block, the clock input of which is connected to the output of the second terminal I, the outputs of the shift register block through the multiplier by weighting factors and the adder are connected to the corresponding information inputs of the driver correction signals, the clock input of which is connected to the additional output of the master oscillator, the output of which is connected to the second input th element, and first and second output of the correction signals coupled to corresponding inputs of adding corrective conductive block and eliminating pulses.

2. The device according to claim 1, which is based on the fact that the phase discrimination discriminator is made in Vade in series of the first electrified output of the divider 12.

Claims (2)

1. A clock synchronization device containing a series-connected master oscillator, a pulse addition and exclusion unit, a frequency divider and a phase discriminator, as well as a differentiation unit whose output is connected to the information input of the phase discriminator, the differentiator block input and the frequency divider output are respectively input and an output of the device, characterized in that, in order to improve noise immunity by reducing the effect of random phase shifts in 0 25 35 55 cops And and RS-flip-flop, and also vto40 45 50 the connected element OR, the counting trigger, the first element AND and the counter of U4 pulses, the second element AND sequencer of the correction signals connected in series, as well as the block of shift registers, the multiplication unit by weights and the adder, while the outputs of the differentiating unit and the frequency divider are connected respectively, to the first and second inputs of the OR element, the output of which is connected to the first input of the second element AND, the second input of which is combined with the control input of the phase discriminator and connected to the output Counting the trigger output of the phase discriminator and outputs bits c etchi-. The pulses are connected to the corresponding information inputs of the shift register block, the clock input of which is connected to the output of the second input I, the outputs of the shift register block through the multiplication unit by weighting factors and the adder are connected to the corresponding information inputs of the correction signal generator, the clock input of which is connected to the additional output that specifies generator, the output of which is connected to the second input of the first element, and the first and second outputs of the driver corrective signals are connected to respective inputs of the corrective unit and eliminating the addition of pulses. 2. The device according to claim 1, about tl, which is the fact that the phase discriminator is made in Vade a serially connected first E-element I, the output of which is connected to the R input of an RS flip-flop, the first inputs of the first and second I elements respectively 513380946 the information and clock inputs of the AND components and the RS-trigger output are the discriminator of the Internet, combined with the control input, respectively, of the second inputs of the first and second elements and the output of the phase discriminator. F 4 F F 1B nineteen 20 FI.2