SU1246350A1 - Device for selecting single pulse - Google Patents

Abstract

The invention may be used in automatic control systems. The purpose of the invention is to increase the functional reliability of the device. The device contains a D-flip-flop 1, RS-flip-flop 2, the element NO 3 and the bus 5, 6 and 7 control clock pulses and output, respectively. The introduction of the element OR-NOT 4 and the formation of new connections in the device reduces the amount of equipment used. 2 Il. 4 od 00 cl

Description

eleven

The invention relates to a pulse technique and can be used in automatic control systems, as well as in a measuring computing technique for inserting a single pulse from a series to synchronize input signals with clock pulses.

The purpose of the invention is to increase the functional reliability of the device by reducing the amount of equipment used.

Fig. 1 shows a functional diagram of a device for infusing a single pulse; 2 shows timing diagrams for his work.

The device for the extraction of a single pulse contains a D-flip-flop 1, RS-flip-flop 2, element NO 3, element OR-NO 4, control bus 5, bus 6 clock pulses and output bus 7 5 with the first input of RS flip-flop 2 connected to bus 5 control and with the installation input of the D-flip-flop 1, the first output of which is connected to the second input of the RS-flip-flop 2, the output of the latter is connected to the information input of the D-flip-flop 1, and the first input of the element OR-NOT 4 is connected to the second output of the D-flip-flop 1, the counting input of which is connected to the bus 6 clock pulses and through the element NO 3 with a second input of OR-NO element 4, the output of which is connected to the output bus 7 ..

The device for ejection, single-pulse operation works as follows.

In the initial state, the D-flip-flop 1 and the RS-flip-flop 2 are held in the zero state by a single potential, which is fed to the control bus 5 (Fig. 2a). In this case, a zero potential is established on the EI-OUT bus 7 (Fig. 2e), since the OR-NO 4 element is closed to the input by a single potential coming from the inverse output of the D-flip-flop 1 (Fig. 2e).

After the signal of the zero level (Fig. 2a) arrives at the control bus 5 on the leading edge of the first clock pulse, which enters the bus 6 clock pulses at the digital input of the D-flip-flop 1 (Fig. 26), the D-flip-flop 1 switches to one state 5 as on its information input there is unified463502

a significant potential from the inverse output of the RS flip-flop 2 (Fig. 2g). On a single potential from the direct output of the D-flip-flop 1 (fig.2g) RS-flip-flop 2

,, switch to state. at which on. its inverse output is set to zero potential (Fig. 2g), arriving at the information input of D-flip-flop 1. At the same time (3, the inverse output of D-flip-flop 1 sets zero potential (Fig. 2e) allowing the passage through the element OR NOT 4 inverted element NOT 3 clock

J2 pulse (figv.) On the output bus 7 (phi: g.2e). .

Trace}, skinny clock impz / ls free- the leading edge sets the D-flip-flop 1 to the zero state, with

20 which, at its inverse output, a single potential is established (fig. 2e), prohibiting the passage of pulses: pulses inverted by an HE 3 element, through an OR-HE 25 4 element per pin bus 7. State

RS-flip-flop 2 does not change et-. c (fig, | 2g). Upon termination of the zero-level signal on the control bus 5 (Fig. 2a) E. B flip-flop 2 is set.

JP is poured into the zero state (fig. 2g) k together with the D-flip-flop 1 holding. It is before the next control signal of the zero level, i.e. the device returns to its original state.

Claims (1)

Formula A device for isolating a single pulse containing a D-flip-flop, an RS-flip-flop, the first input of which is connected to the control bus and the installation input of the D-flip-flop, the first output of which is connected to the second input of the RS-flip-flop, the output of which is connected to information input B - trigger, element NOT, bus clock 1-1Mgg Ls and output bus, different in 4TOj for the purpose of functional functioning reliability, the element 11PI-NOT is entered into it, the first input of which is connected to the second input of the D-trigger-. pa whose counting input is connected with the bus clock pulses and through the element NOT with the second input element I.TI-NOT, the output of which is connected to the output bus. vcs "o Editor H. Bobkova Compiled by V. Lobyntsev Tehred L.Oleynik Proof-reader I. Erdeyk Order 4021/55 Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 N4 (“j rr eo Ct5 Cb