SG81933A1 - Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby - Google Patents

Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby

Info

Publication number
SG81933A1
SG81933A1 SG9802663A SG1998002663A SG81933A1 SG 81933 A1 SG81933 A1 SG 81933A1 SG 9802663 A SG9802663 A SG 9802663A SG 1998002663 A SG1998002663 A SG 1998002663A SG 81933 A1 SG81933 A1 SG 81933A1
Authority
SG
Singapore
Prior art keywords
solder
shaped
increasing
bump
controlled
Prior art date
Application number
SG9802663A
Other languages
English (en)
Inventor
Glenn A Rinne
Paul A Magill
Original Assignee
Mcnc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mcnc filed Critical Mcnc
Publication of SG81933A1 publication Critical patent/SG81933A1/en

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
SG9802663A 1997-07-25 1998-07-24 Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby SG81933A1 (en)

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EP (1) EP0899787A3 (de)
JP (1) JP3425526B2 (de)
KR (1) KR100378126B1 (de)
SG (2) SG99384A1 (de)
TW (1) TW520628B (de)

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KR100349374B1 (ko) * 1999-12-16 2002-08-21 주식회사 하이닉스반도체 웨이퍼 레벨 패키지 및 그의 제조 방법
KR100668809B1 (ko) * 2000-06-30 2007-01-16 주식회사 하이닉스반도체 웨이퍼 레벨 패키지
US6550666B2 (en) * 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
GB2381665B (en) * 2001-11-02 2005-06-22 Jetmask Ltd Method of forming a mask on a surface
US7834449B2 (en) * 2007-04-30 2010-11-16 Broadcom Corporation Highly reliable low cost structure for wafer-level ball grid array packaging
JP4962217B2 (ja) * 2007-08-28 2012-06-27 富士通株式会社 プリント配線基板及び電子装置製造方法
FR2924302B1 (fr) * 2007-11-23 2010-10-22 St Microelectronics Grenoble Procede de fabrication de plots de connexion electrique d'une plaque
KR20140041975A (ko) * 2012-09-25 2014-04-07 삼성전자주식회사 범프 구조체 및 이를 포함하는 전기적 연결 구조체
JP2015228472A (ja) * 2014-06-03 2015-12-17 株式会社ソシオネクスト 半導体装置およびその製造方法

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JPH0766207A (ja) * 1993-08-24 1995-03-10 Sony Corp 表面実装型電子部品及びその製造方法並びに半田付け方法

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JPH0766207A (ja) * 1993-08-24 1995-03-10 Sony Corp 表面実装型電子部品及びその製造方法並びに半田付け方法

Also Published As

Publication number Publication date
EP0899787A3 (de) 2001-05-16
JPH11102926A (ja) 1999-04-13
JP3425526B2 (ja) 2003-07-14
EP0899787A2 (de) 1999-03-03
SG99384A1 (en) 2003-10-27
TW520628B (en) 2003-02-11
KR19990014176A (ko) 1999-02-25
KR100378126B1 (ko) 2003-07-18

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