SG166669A1 - Semiconductor device and packaging method thereof - Google Patents
Semiconductor device and packaging method thereofInfo
- Publication number
- SG166669A1 SG166669A1 SG200104537-6A SG2001045376A SG166669A1 SG 166669 A1 SG166669 A1 SG 166669A1 SG 2001045376 A SG2001045376 A SG 2001045376A SG 166669 A1 SG166669 A1 SG 166669A1
- Authority
- SG
- Singapore
- Prior art keywords
- resin
- chip
- semiconductor device
- mounting area
- area
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000000034 method Methods 0.000 title 1
- 238000004806 packaging method and process Methods 0.000 title 1
- 239000011347 resin Substances 0.000 abstract 4
- 229920005989 resin Polymers 0.000 abstract 4
- 239000000523 sample Substances 0.000 abstract 1
- 238000007789 sealing Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4905—Shape
- H01L2224/49051—Connectors having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000225982A JP2002040095A (ja) | 2000-07-26 | 2000-07-26 | 半導体装置及びその実装方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG166669A1 true SG166669A1 (en) | 2010-12-29 |
Family
ID=18719677
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200104537-6A SG166669A1 (en) | 2000-07-26 | 2001-07-26 | Semiconductor device and packaging method thereof |
Country Status (7)
Country | Link |
---|---|
US (1) | US6747361B2 (de) |
EP (1) | EP1176638A2 (de) |
JP (1) | JP2002040095A (de) |
KR (1) | KR100443476B1 (de) |
CN (1) | CN1334602A (de) |
SG (1) | SG166669A1 (de) |
TW (1) | TW502349B (de) |
Families Citing this family (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003010825A1 (en) * | 2001-07-24 | 2003-02-06 | Seiko Epson Corporation | Transfer method, method of manufacturing thin film element, method of manufacturing integrated circuit, circuit substrate and method of manufacturing the circuit substrate, electro-optic device and method of manufacturing the electro-optic device, and ic card and electronic equipmen |
US7262074B2 (en) * | 2002-07-08 | 2007-08-28 | Micron Technology, Inc. | Methods of fabricating underfilled, encapsulated semiconductor die assemblies |
JP3724464B2 (ja) * | 2002-08-19 | 2005-12-07 | 株式会社デンソー | 半導体圧力センサ |
AU2003272405A1 (en) * | 2002-09-17 | 2004-04-08 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnection between stacked packages |
US7064426B2 (en) | 2002-09-17 | 2006-06-20 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnect between stacked packages |
US7034387B2 (en) | 2003-04-04 | 2006-04-25 | Chippac, Inc. | Semiconductor multipackage module including processor and memory package assemblies |
US6906416B2 (en) * | 2002-10-08 | 2005-06-14 | Chippac, Inc. | Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package |
US6998721B2 (en) * | 2002-11-08 | 2006-02-14 | Stmicroelectronics, Inc. | Stacking and encapsulation of multiple interconnected integrated circuits |
JP2005064479A (ja) * | 2003-07-31 | 2005-03-10 | Sanyo Electric Co Ltd | 回路モジュール |
JP2005123542A (ja) | 2003-10-20 | 2005-05-12 | Genusion:Kk | 半導体装置のパッケージ構造およびパッケージ化方法 |
JP5197961B2 (ja) * | 2003-12-17 | 2013-05-15 | スタッツ・チップパック・インコーポレイテッド | マルチチップパッケージモジュールおよびその製造方法 |
JP2005209882A (ja) * | 2004-01-22 | 2005-08-04 | Renesas Technology Corp | 半導体パッケージ及び半導体装置 |
US20050258527A1 (en) | 2004-05-24 | 2005-11-24 | Chippac, Inc. | Adhesive/spacer island structure for multiple die package |
US20050269692A1 (en) * | 2004-05-24 | 2005-12-08 | Chippac, Inc | Stacked semiconductor package having adhesive/spacer structure and insulation |
US8552551B2 (en) | 2004-05-24 | 2013-10-08 | Chippac, Inc. | Adhesive/spacer island structure for stacking over wire bonded die |
JP4561969B2 (ja) * | 2004-05-26 | 2010-10-13 | セイコーエプソン株式会社 | 半導体装置 |
US7253511B2 (en) * | 2004-07-13 | 2007-08-07 | Chippac, Inc. | Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package |
US7202554B1 (en) * | 2004-08-19 | 2007-04-10 | Amkor Technology, Inc. | Semiconductor package and its manufacturing method |
JP2006073825A (ja) * | 2004-09-02 | 2006-03-16 | Toshiba Corp | 半導体装置及びその実装方法 |
US7466012B2 (en) * | 2004-09-13 | 2008-12-16 | International Rectifier Corporation | Power semiconductor package |
KR100771860B1 (ko) * | 2004-12-28 | 2007-11-01 | 삼성전자주식회사 | 솔더볼을 사용하지 않는 반도체 패키지 모듈 및 그 제조방법 |
US20060163707A1 (en) * | 2005-01-21 | 2006-07-27 | Motorola, Inc. | Method and apparatus for reducing stresses applied to bonded interconnects between substrates |
JP2006216911A (ja) * | 2005-02-07 | 2006-08-17 | Renesas Technology Corp | 半導体装置およびカプセル型半導体パッケージ |
US20060202320A1 (en) * | 2005-03-10 | 2006-09-14 | Schaffer Christopher P | Power semiconductor package |
US7364945B2 (en) * | 2005-03-31 | 2008-04-29 | Stats Chippac Ltd. | Method of mounting an integrated circuit package in an encapsulant cavity |
KR101213661B1 (ko) * | 2005-03-31 | 2012-12-17 | 스태츠 칩팩, 엘티디. | 칩 스케일 패키지 및 제 2 기판을 포함하고 있으며 상부면및 하부면에서 노출된 기판 표면들을 갖는 반도체 어셈블리 |
KR101172527B1 (ko) * | 2005-03-31 | 2012-08-10 | 스태츠 칩팩, 엘티디. | 상부면 및 하부면에서 노출된 기판 표면들을 갖는 반도체적층 패키지 어셈블리 |
US7429786B2 (en) * | 2005-04-29 | 2008-09-30 | Stats Chippac Ltd. | Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides |
US7354800B2 (en) * | 2005-04-29 | 2008-04-08 | Stats Chippac Ltd. | Method of fabricating a stacked integrated circuit package system |
US7582960B2 (en) * | 2005-05-05 | 2009-09-01 | Stats Chippac Ltd. | Multiple chip package module including die stacked over encapsulated package |
US7394148B2 (en) | 2005-06-20 | 2008-07-01 | Stats Chippac Ltd. | Module having stacked chip scale semiconductor packages |
JP4541253B2 (ja) * | 2005-08-23 | 2010-09-08 | 新光電気工業株式会社 | 半導体パッケージ及びその製造方法 |
US7456088B2 (en) | 2006-01-04 | 2008-11-25 | Stats Chippac Ltd. | Integrated circuit package system including stacked die |
US7768125B2 (en) | 2006-01-04 | 2010-08-03 | Stats Chippac Ltd. | Multi-chip package system |
US7750482B2 (en) | 2006-02-09 | 2010-07-06 | Stats Chippac Ltd. | Integrated circuit package system including zero fillet resin |
US8704349B2 (en) | 2006-02-14 | 2014-04-22 | Stats Chippac Ltd. | Integrated circuit package system with exposed interconnects |
JP2007294488A (ja) * | 2006-04-20 | 2007-11-08 | Shinko Electric Ind Co Ltd | 半導体装置、電子部品、及び半導体装置の製造方法 |
US7420206B2 (en) | 2006-07-12 | 2008-09-02 | Genusion Inc. | Interposer, semiconductor chip mounted sub-board, and semiconductor package |
DE102006033864B4 (de) * | 2006-07-21 | 2009-04-16 | Infineon Technologies Ag | Elektronische Schaltung in einer Package-in-Package-Konfiguration und Herstellungsverfahren für eine solche Schaltung |
JP2008141122A (ja) * | 2006-12-05 | 2008-06-19 | Denso Corp | 樹脂モールド電子部品及びその製造方法 |
US8237259B2 (en) * | 2007-06-13 | 2012-08-07 | Infineon Technologies Ag | Embedded chip package |
US7901955B2 (en) * | 2007-06-25 | 2011-03-08 | Spansion Llc | Method of constructing a stacked-die semiconductor structure |
US8203214B2 (en) * | 2007-06-27 | 2012-06-19 | Stats Chippac Ltd. | Integrated circuit package in package system with adhesiveless package attach |
US7825502B2 (en) * | 2008-01-09 | 2010-11-02 | Fairchild Semiconductor Corporation | Semiconductor die packages having overlapping dice, system using the same, and methods of making the same |
TW201140664A (en) * | 2010-05-05 | 2011-11-16 | Aptos Technology Inc | Method for acquiring recycled chips and method for fabricating semiconductor package |
CN102468122A (zh) * | 2010-11-01 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件失效分析样品制作方法及分析方法 |
JP2013211407A (ja) | 2012-03-30 | 2013-10-10 | J Devices:Kk | 半導体モジュール |
US9385006B2 (en) * | 2012-06-21 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming an embedded SOP fan-out package |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0623954A1 (de) * | 1993-05-07 | 1994-11-09 | AT&T Corp. | Vergossene Kunststoffverkapselung für elektronische Anordnungen |
US6013948A (en) * | 1995-11-27 | 2000-01-11 | Micron Technology, Inc. | Stackable chip scale semiconductor package with mating contacts on opposed surfaces |
US6072239A (en) * | 1995-11-08 | 2000-06-06 | Fujitsu Limited | Device having resin package with projections |
US6221682B1 (en) * | 1999-05-28 | 2001-04-24 | Lockheed Martin Corporation | Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects |
US6429532B1 (en) * | 2000-05-09 | 2002-08-06 | United Microelectronics Corp. | Pad design |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0653393A (ja) | 1992-07-31 | 1994-02-25 | Nec Corp | 半導体装置用リードフレーム |
JPH0662382A (ja) | 1992-08-06 | 1994-03-04 | Fujitsu Ltd | 文字放送番組受信表示方式 |
JPH0722567A (ja) | 1993-07-01 | 1995-01-24 | Fujitsu Miyagi Electron:Kk | モールド樹脂封止型半導体装置とその製造方法 |
JPH0738240A (ja) | 1993-07-21 | 1995-02-07 | Rohm Co Ltd | ハイブリッド集積回路装置の構造 |
US5367763A (en) | 1993-09-30 | 1994-11-29 | Atmel Corporation | TAB testing of area array interconnected chips |
JP2833996B2 (ja) | 1994-05-25 | 1998-12-09 | 日本電気株式会社 | フレキシブルフィルム及びこれを有する半導体装置 |
JPH08306853A (ja) * | 1995-05-09 | 1996-11-22 | Fujitsu Ltd | 半導体装置及びその製造方法及びリードフレームの製造方法 |
JPH0917910A (ja) | 1995-06-28 | 1997-01-17 | Hitachi Ltd | 半導体装置及びその製造方法、検査方法、実装基板 |
US6054337A (en) * | 1996-12-13 | 2000-04-25 | Tessera, Inc. | Method of making a compliant multichip package |
KR100237051B1 (ko) * | 1996-12-28 | 2000-01-15 | 김영환 | 버텀리드 반도체 패키지 및 그 제조 방법 |
JPH1140617A (ja) | 1997-07-22 | 1999-02-12 | Toshiba Corp | スモール・テープ・キャリア・パッケージ用の配線テープとそれを用いた半導体装置およびそのテスト方法 |
-
2000
- 2000-07-26 JP JP2000225982A patent/JP2002040095A/ja active Pending
-
2001
- 2001-07-24 TW TW090118112A patent/TW502349B/zh not_active IP Right Cessation
- 2001-07-24 US US09/910,899 patent/US6747361B2/en not_active Expired - Fee Related
- 2001-07-25 EP EP01118044A patent/EP1176638A2/de not_active Withdrawn
- 2001-07-25 KR KR10-2001-0044947A patent/KR100443476B1/ko not_active IP Right Cessation
- 2001-07-26 SG SG200104537-6A patent/SG166669A1/en unknown
- 2001-07-26 CN CN01123729A patent/CN1334602A/zh active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0623954A1 (de) * | 1993-05-07 | 1994-11-09 | AT&T Corp. | Vergossene Kunststoffverkapselung für elektronische Anordnungen |
US6072239A (en) * | 1995-11-08 | 2000-06-06 | Fujitsu Limited | Device having resin package with projections |
US6013948A (en) * | 1995-11-27 | 2000-01-11 | Micron Technology, Inc. | Stackable chip scale semiconductor package with mating contacts on opposed surfaces |
US6221682B1 (en) * | 1999-05-28 | 2001-04-24 | Lockheed Martin Corporation | Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects |
US6429532B1 (en) * | 2000-05-09 | 2002-08-06 | United Microelectronics Corp. | Pad design |
Also Published As
Publication number | Publication date |
---|---|
JP2002040095A (ja) | 2002-02-06 |
KR20020010513A (ko) | 2002-02-04 |
TW502349B (en) | 2002-09-11 |
KR100443476B1 (ko) | 2004-08-09 |
CN1334602A (zh) | 2002-02-06 |
US20020011651A1 (en) | 2002-01-31 |
EP1176638A2 (de) | 2002-01-30 |
US6747361B2 (en) | 2004-06-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
SG166669A1 (en) | Semiconductor device and packaging method thereof | |
TW200518354A (en) | Device package and methods for the fabrication and testing thereof | |
SG95651A1 (en) | Method for encapsulating intermediate conductive elements connecting a semiconductor die to a substrate and semiconductor devices so packaged | |
KR950007621A (ko) | 칩 캐리어 | |
US5408190A (en) | Testing apparatus having substrate interconnect for discrete die burn-in for nonpackaged die | |
US5440240A (en) | Z-axis interconnect for discrete die burn-in for nonpackaged die | |
US5721496A (en) | Method and apparatus for leak checking unpackaged semiconductor dice | |
EP1296388A3 (de) | Dichtungsstruktur für sehr feuchtigkeitsempfindliche elektronische Vorrichtung und Herstellungsverfahren | |
MY123034A (en) | Semiconductor device and method of fabricating the same | |
MY134479A (en) | Method and apparatus for packaging integrated circuit devices | |
EP1296385A3 (de) | Sehr feuchtigkeitsempfindliche elektronische Vorrichtungen und Herstellungsverfahren | |
KR0119464B1 (en) | Semiconductor device and lead frame | |
US6340838B1 (en) | Apparatus and method for containing semiconductor chips to identify known good dies | |
WO2001036990A3 (en) | Wafer level interposer | |
EP0755075A3 (de) | Bandträgerpackung | |
WO2003041158A3 (en) | Semiconductor package device and method of formation and testing | |
EP1058306A3 (de) | Elektronikkomponente zur Montage auf LPL mit darin verkapseltem Elektronikbauteil und ihre Herstellung | |
ES2147286T3 (es) | Empaquetamiento electronico sellado para la proteccion del ambiente de electronica activa. | |
WO1999019906A3 (en) | Method and apparatus for packaging high temperature solid state electronic devices | |
TW345685B (en) | Semiconductor device with wafer burn-in and method therefor | |
US5396032A (en) | Method and apparatus for providing electrical access to devices in a multi-chip module | |
US5874319A (en) | Vacuum die bond for known good die assembly | |
US6828812B2 (en) | Test apparatus for testing semiconductor dice including substrate with penetration limiting contacts for making electrical connections | |
KR950014897A (ko) | 번인 테스트용 칩 홀딩장치 및 그 제조방법 | |
KR100374630B1 (ko) | 반도체 장치용 소켓과 인쇄 회로 기판 및 테스트 방법 |