SG11202105865XA - Semiconductor memory device and method of manufacturing semiconductor memory device - Google Patents

Semiconductor memory device and method of manufacturing semiconductor memory device

Info

Publication number
SG11202105865XA
SG11202105865XA SG11202105865XA SG11202105865XA SG 11202105865X A SG11202105865X A SG 11202105865XA SG 11202105865X A SG11202105865X A SG 11202105865XA SG 11202105865X A SG11202105865X A SG 11202105865XA
Authority
SG
Singapore
Prior art keywords
memory device
semiconductor memory
manufacturing
manufacturing semiconductor
semiconductor
Prior art date
Application number
Other languages
English (en)
Inventor
Shigeki Kobayashi
Yoshinori Nakakubo
Yasutaka Nonaka
Original Assignee
Kioxia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kioxia Corp filed Critical Kioxia Corp
Publication of SG11202105865XA publication Critical patent/SG11202105865XA/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
SG11202105865X 2020-03-09 2020-03-09 Semiconductor memory device and method of manufacturing semiconductor memory device SG11202105865XA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/009994 WO2021181455A1 (ja) 2020-03-09 2020-03-09 半導体記憶装置及び半導体記憶装置の製造方法

Publications (1)

Publication Number Publication Date
SG11202105865XA true SG11202105865XA (en) 2021-10-28

Family

ID=77671256

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202105865X SG11202105865XA (en) 2020-03-09 2020-03-09 Semiconductor memory device and method of manufacturing semiconductor memory device

Country Status (4)

Country Link
US (1) US20210313334A1 (zh)
CN (1) CN113632230B (zh)
SG (1) SG11202105865XA (zh)
WO (1) WO2021181455A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230032177A1 (en) * 2021-07-27 2023-02-02 Micron Technology, Inc. Electronic devices comprising multilevel bitlines, and related methods and systems
WO2023105763A1 (ja) * 2021-12-10 2023-06-15 キオクシア株式会社 メモリデバイス

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* Cited by examiner, † Cited by third party
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JPH0963283A (ja) * 1995-08-28 1997-03-07 Sony Corp 半導体不揮発性メモリ素子およびその使用方法
US6876590B2 (en) * 2002-11-20 2005-04-05 Infineon Technologies, Ag 2T2C signal margin test mode using a defined charge exchange between BL and/BL
JP2005353657A (ja) * 2004-06-08 2005-12-22 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
WO2010106922A1 (ja) * 2009-03-19 2010-09-23 株式会社 東芝 半導体装置及びその製造方法
JP2015172990A (ja) * 2014-03-12 2015-10-01 株式会社東芝 不揮発性半導体記憶装置
US9780104B2 (en) * 2015-09-10 2017-10-03 Toshiba Memory Corporation Semiconductor memory device and method of manufacturing the same
JP2018049673A (ja) * 2016-09-20 2018-03-29 東芝メモリ株式会社 半導体記憶装置
JP2018157106A (ja) * 2017-03-17 2018-10-04 東芝メモリ株式会社 記憶装置および容量素子
KR20180126914A (ko) * 2017-05-19 2018-11-28 에스케이하이닉스 주식회사 캐패시터를 구비하는 반도체 메모리 장치
JP2019117679A (ja) * 2017-12-27 2019-07-18 東芝メモリ株式会社 半導体記憶装置
JP2019145191A (ja) * 2018-02-23 2019-08-29 東芝メモリ株式会社 半導体記憶装置及び半導体記憶装置の制御方法
KR102614728B1 (ko) * 2018-04-04 2023-12-19 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
JP2019192869A (ja) * 2018-04-27 2019-10-31 東芝メモリ株式会社 半導体記憶装置
JP2019200826A (ja) * 2018-05-14 2019-11-21 東芝メモリ株式会社 半導体記憶装置
JP2019212350A (ja) * 2018-06-01 2019-12-12 東芝メモリ株式会社 半導体メモリ
JP2020009509A (ja) * 2018-07-03 2020-01-16 キオクシア株式会社 半導体記憶装置
JP2020009904A (ja) * 2018-07-09 2020-01-16 キオクシア株式会社 半導体メモリ
JP2020013889A (ja) * 2018-07-18 2020-01-23 キオクシア株式会社 半導体記憶装置
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US11342006B2 (en) * 2019-10-28 2022-05-24 Sandisk Technologies Llc Buried source line structure for boosting read scheme

Also Published As

Publication number Publication date
CN113632230A (zh) 2021-11-09
WO2021181455A1 (ja) 2021-09-16
US20210313334A1 (en) 2021-10-07
CN113632230B (zh) 2024-03-05

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