SG10202101210VA - Semiconductor memory device and erasing method of the semiconductor memory device - Google Patents
Semiconductor memory device and erasing method of the semiconductor memory deviceInfo
- Publication number
- SG10202101210VA SG10202101210VA SG10202101210VA SG10202101210VA SG10202101210VA SG 10202101210V A SG10202101210V A SG 10202101210VA SG 10202101210V A SG10202101210V A SG 10202101210VA SG 10202101210V A SG10202101210V A SG 10202101210VA SG 10202101210V A SG10202101210V A SG 10202101210VA
- Authority
- SG
- Singapore
- Prior art keywords
- memory device
- semiconductor memory
- erasing method
- erasing
- semiconductor
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020200046886A KR20210128791A (en) | 2020-04-17 | 2020-04-17 | Semiconductor memory device and erasing method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10202101210VA true SG10202101210VA (en) | 2021-11-29 |
Family
ID=77920134
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10202101210VA SG10202101210VA (en) | 2020-04-17 | 2021-02-04 | Semiconductor memory device and erasing method of the semiconductor memory device |
Country Status (6)
Country | Link |
---|---|
US (2) | US11562956B2 (en) |
KR (1) | KR20210128791A (en) |
CN (1) | CN113611345A (en) |
DE (1) | DE102021201252A1 (en) |
SG (1) | SG10202101210VA (en) |
TW (1) | TW202141479A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200144000A (en) * | 2019-06-17 | 2020-12-28 | 에스케이하이닉스 주식회사 | Memory device and operating method thereof |
JP2023137979A (en) * | 2022-03-18 | 2023-09-29 | キオクシア株式会社 | Semiconductor storage device and manufacturing method thereof |
US20230389308A1 (en) * | 2022-05-26 | 2023-11-30 | Sandisk Technologies Llc | Three-dimensional memory device containing dual-depth drain-select-level isolation structures and methods for forming the same |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7590005B2 (en) * | 2006-04-06 | 2009-09-15 | Macronix International Co., Ltd. | Program and erase methods with substrate transient hot carrier injections in a non-volatile memory |
CN100452406C (en) * | 2006-04-10 | 2009-01-14 | 清华大学 | Trap charge capturing quick flashing storage array structure and operating method thereof |
KR100777348B1 (en) * | 2006-07-11 | 2007-11-20 | 삼성전자주식회사 | Cell array structure of non-volatile memory device and method of forming the same |
US8144511B2 (en) * | 2009-08-19 | 2012-03-27 | Sandisk Technologies Inc. | Selective memory cell program and erase |
KR101658479B1 (en) * | 2010-02-09 | 2016-09-21 | 삼성전자주식회사 | Nonvolatile memory device, operating method thereof and memory system including the same |
JP2012119013A (en) * | 2010-11-29 | 2012-06-21 | Toshiba Corp | Nonvolatile semiconductor memory device |
KR20130084834A (en) * | 2012-01-18 | 2013-07-26 | 에스케이하이닉스 주식회사 | Semiconductor memory device and operating method thereof |
KR102022502B1 (en) * | 2012-08-30 | 2019-09-18 | 에스케이하이닉스 주식회사 | Programming method of nonvolatile memory device |
KR20150063851A (en) * | 2013-12-02 | 2015-06-10 | 에스케이하이닉스 주식회사 | Semiconductor memory device and erasing method thereof |
KR102239596B1 (en) * | 2017-06-13 | 2021-04-12 | 에스케이하이닉스 주식회사 | Nonvolatile memory device |
KR102409799B1 (en) * | 2018-01-17 | 2022-06-16 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
KR102434922B1 (en) * | 2018-03-05 | 2022-08-23 | 에스케이하이닉스 주식회사 | Semiconductor memory device and operating method thereof |
KR102624619B1 (en) | 2018-04-30 | 2024-01-15 | 삼성전자주식회사 | Three-dimensional semiconductor memory devices |
KR20200033067A (en) | 2018-09-19 | 2020-03-27 | 에스케이하이닉스 주식회사 | Semiconductor device and manufacturing method thereof |
JP2020144962A (en) * | 2019-03-07 | 2020-09-10 | キオクシア株式会社 | Semiconductor storage device |
-
2020
- 2020-04-17 KR KR1020200046886A patent/KR20210128791A/en not_active Application Discontinuation
- 2020-09-23 US US17/030,013 patent/US11562956B2/en active Active
-
2021
- 2021-01-28 CN CN202110117512.6A patent/CN113611345A/en active Pending
- 2021-02-04 SG SG10202101210VA patent/SG10202101210VA/en unknown
- 2021-02-10 DE DE102021201252.3A patent/DE102021201252A1/en active Pending
- 2021-03-11 TW TW110108690A patent/TW202141479A/en unknown
-
2022
- 2022-12-16 US US18/083,206 patent/US11804429B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20230120166A1 (en) | 2023-04-20 |
TW202141479A (en) | 2021-11-01 |
US11562956B2 (en) | 2023-01-24 |
CN113611345A (en) | 2021-11-05 |
DE102021201252A1 (en) | 2021-10-21 |
KR20210128791A (en) | 2021-10-27 |
US11804429B2 (en) | 2023-10-31 |
US20210327805A1 (en) | 2021-10-21 |
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