SG11202100824QA - Semiconductor plug protected by protective dielectric layer in three-dimensional memory device and method for forming the same - Google Patents
Semiconductor plug protected by protective dielectric layer in three-dimensional memory device and method for forming the sameInfo
- Publication number
- SG11202100824QA SG11202100824QA SG11202100824QA SG11202100824QA SG11202100824QA SG 11202100824Q A SG11202100824Q A SG 11202100824QA SG 11202100824Q A SG11202100824Q A SG 11202100824QA SG 11202100824Q A SG11202100824Q A SG 11202100824QA SG 11202100824Q A SG11202100824Q A SG 11202100824QA
- Authority
- SG
- Singapore
- Prior art keywords
- forming
- dielectric layer
- memory device
- same
- dimensional memory
- Prior art date
Links
- 230000001681 protective effect Effects 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2018/107790 WO2020061868A1 (en) | 2018-09-27 | 2018-09-27 | Semiconductor plug protected by protective dielectric layer in three-dimensional memory device and method for forming the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG11202100824QA true SG11202100824QA (en) | 2021-02-25 |
Family
ID=65462659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11202100824QA SG11202100824QA (en) | 2018-09-27 | 2018-09-27 | Semiconductor plug protected by protective dielectric layer in three-dimensional memory device and method for forming the same |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US10714493B2 (ko) |
| EP (2) | EP3811406B1 (ko) |
| JP (1) | JP2022502859A (ko) |
| KR (1) | KR20210028247A (ko) |
| CN (2) | CN109417074A (ko) |
| AU (1) | AU2018443831B2 (ko) |
| SG (1) | SG11202100824QA (ko) |
| TW (1) | TW202013685A (ko) |
| WO (1) | WO2020061868A1 (ko) |
Families Citing this family (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110121778B (zh) * | 2019-03-04 | 2020-08-25 | 长江存储科技有限责任公司 | 三维存储器件 |
| CN110062958B (zh) | 2019-03-04 | 2020-05-26 | 长江存储科技有限责任公司 | 用于形成三维存储器件的方法 |
| JP7353374B2 (ja) * | 2019-03-18 | 2023-09-29 | 長江存儲科技有限責任公司 | 三次元メモリデバイスにおける高κ誘電体層およびこれを形成するための方法 |
| WO2020198943A1 (en) | 2019-03-29 | 2020-10-08 | Yangtze Memory Technologies Co., Ltd. | Memory stacks having silicon oxynitride gate-to-gate dielectric layers and methods for forming the same |
| CN110114880B (zh) | 2019-03-29 | 2020-10-30 | 长江存储科技有限责任公司 | 具有氮化硅栅极到栅极电介质层的存储堆叠体及其形成方法 |
| KR20210137533A (ko) * | 2019-04-12 | 2021-11-17 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 증착된 반도체 플러그들을 갖는 3차원 메모리 디바이스 및 이를 형성하기 위한 방법들 |
| CN110137178B (zh) * | 2019-04-19 | 2022-04-01 | 长江存储科技有限责任公司 | 3d存储器件及其制造方法 |
| JP7279202B2 (ja) * | 2019-06-17 | 2023-05-22 | 長江存儲科技有限責任公司 | ゲート線スリットがない３次元メモリデバイスおよびそれを形成するための方法 |
| CN113745235B (zh) | 2019-06-17 | 2024-04-26 | 长江存储科技有限责任公司 | 具有在栅极线缝隙中的支撑结构的三维存储器件和用于形成其的方法 |
| CN111402942B (zh) * | 2019-08-08 | 2021-03-19 | 长江存储科技有限责任公司 | 非易失性存储器及其制造方法 |
| WO2021056520A1 (en) * | 2019-09-29 | 2021-04-01 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device having epitaxially-grown semiconductor channel and method for forming the same |
| CN111162086A (zh) * | 2020-01-03 | 2020-05-15 | 长江存储科技有限责任公司 | 三维存储器及其制备方法 |
| EP3963629A4 (en) * | 2020-01-21 | 2022-12-21 | Yangtze Memory Technologies Co., Ltd. | THREE-DIMENSIONAL STORAGE DEVICES WITH CRITICAL DIMENSION OF AN EXTENDED CONNECTION AND METHOD OF PRODUCTION THEREOF |
| CN111328428B (zh) * | 2020-02-10 | 2021-05-25 | 长江存储科技有限责任公司 | 在三维存储器件中具有抗蚀刻层的半导体插塞 |
| WO2021163841A1 (en) * | 2020-02-17 | 2021-08-26 | Yangtze Memory Technologies Co., Ltd. | Methods for forming channel structures in three-dimensional memory devices |
| CN111403408B (zh) * | 2020-03-23 | 2023-06-30 | 长江存储科技有限责任公司 | 一种半导体器件制作方法和用该方法制成的半导体器件 |
| US11264275B2 (en) | 2020-05-12 | 2022-03-01 | Micron Technology, Inc. | Integrated assemblies and methods of forming integrated assemblies |
| US11877448B2 (en) | 2020-05-27 | 2024-01-16 | Yangtze Memory Technologies Co., Ltd. | Methods for forming three-dimensional memory devices |
| EP3942612B1 (en) * | 2020-05-27 | 2024-01-03 | Yangtze Memory Technologies Co., Ltd. | Methods for forming three-dimensional memory devices |
| WO2021237880A1 (en) | 2020-05-27 | 2021-12-02 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices |
| CN112585754B (zh) * | 2020-05-27 | 2024-07-19 | 长江存储科技有限责任公司 | 用于形成三维存储器件的方法 |
| CN114743985A (zh) | 2020-05-27 | 2022-07-12 | 长江存储科技有限责任公司 | 三维存储器件 |
| CN111801799B (zh) | 2020-05-27 | 2021-03-23 | 长江存储科技有限责任公司 | 用于形成三维存储器件的方法 |
| US11963349B2 (en) | 2020-05-27 | 2024-04-16 | Yangtze Memory Technologies Co., Ltd. | Methods for forming three-dimensional memory devices with backside source contacts |
| US12048151B2 (en) | 2020-05-27 | 2024-07-23 | Yangtze Memory Technologies Co., Ltd. | Methods for forming three-dimensional memory devices with backside source contacts |
| CN111801798B (zh) | 2020-05-27 | 2021-04-16 | 长江存储科技有限责任公司 | 三维存储器件 |
| CN111755453B (zh) * | 2020-05-29 | 2021-06-04 | 长江存储科技有限责任公司 | 3d存储器件及其制造方法 |
| CN111785733A (zh) * | 2020-07-03 | 2020-10-16 | 长江存储科技有限责任公司 | 3d nand存储器的形成方法 |
| TWI793434B (zh) * | 2020-07-07 | 2023-02-21 | 大陸商長江存儲科技有限責任公司 | 用於形成三維記憶體元件的方法 |
| CN115132701A (zh) * | 2021-03-25 | 2022-09-30 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
| WO2022266785A1 (en) * | 2021-06-21 | 2022-12-29 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device with divided drain select gate lines and method for forming the same |
| US20240074145A1 (en) * | 2022-08-26 | 2024-02-29 | Nanya Technology Corporation | Semiconductor device having bonding structure and method of manufacturing the same |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8013389B2 (en) * | 2008-11-06 | 2011-09-06 | Samsung Electronics Co., Ltd. | Three-dimensional nonvolatile memory devices having sub-divided active bars and methods of manufacturing such devices |
| US8173987B2 (en) | 2009-04-27 | 2012-05-08 | Macronix International Co., Ltd. | Integrated circuit 3D phase change memory array and manufacturing method |
| TWI442551B (zh) | 2010-03-04 | 2014-06-21 | Macronix Int Co Ltd | 記憶體元件及其製造方法 |
| KR20120003351A (ko) * | 2010-07-02 | 2012-01-10 | 삼성전자주식회사 | 3차원 비휘발성 메모리 장치 및 그 동작방법 |
| KR102044275B1 (ko) | 2013-07-31 | 2019-11-14 | 에스케이하이닉스 주식회사 | 에어갭을 구비한 반도체장치 및 그 제조 방법 |
| US9230984B1 (en) * | 2014-09-30 | 2016-01-05 | Sandisk Technologies Inc | Three dimensional memory device having comb-shaped source electrode and methods of making thereof |
| US9613975B2 (en) * | 2015-03-31 | 2017-04-04 | Sandisk Technologies Llc | Bridge line structure for bit line connection in a three-dimensional semiconductor device |
| US9853043B2 (en) * | 2015-08-25 | 2017-12-26 | Sandisk Technologies Llc | Method of making a multilevel memory stack structure using a cavity containing a sacrificial fill material |
| US9728551B1 (en) * | 2016-02-04 | 2017-08-08 | Sandisk Technologies Llc | Multi-tier replacement memory stack structure integration scheme |
| US10115732B2 (en) * | 2016-02-22 | 2018-10-30 | Sandisk Technologies Llc | Three dimensional memory device containing discrete silicon nitride charge storage regions |
| US10242994B2 (en) * | 2016-03-16 | 2019-03-26 | Sandisk Technologies Llc | Three-dimensional memory device containing annular etch-stop spacer and method of making thereof |
| US9818760B1 (en) * | 2017-03-20 | 2017-11-14 | Macronix International Co., Ltd. | Memory structure, method of operating the same, and method of manufacturing the same |
| US10608012B2 (en) * | 2017-08-29 | 2020-03-31 | Micron Technology, Inc. | Memory devices including memory cells and related methods |
| CN107871744B (zh) * | 2017-11-09 | 2019-03-19 | 长江存储科技有限责任公司 | 一种nand串结构及其制备方法 |
-
2018
- 2018-09-27 KR KR1020217003725A patent/KR20210028247A/ko not_active Application Discontinuation
- 2018-09-27 CN CN201880001825.1A patent/CN109417074A/zh active Pending
- 2018-09-27 SG SG11202100824QA patent/SG11202100824QA/en unknown
- 2018-09-27 JP JP2021517384A patent/JP2022502859A/ja active Pending
- 2018-09-27 CN CN202110619167.6A patent/CN113345912A/zh active Pending
- 2018-09-27 WO PCT/CN2018/107790 patent/WO2020061868A1/en unknown
- 2018-09-27 EP EP18935095.2A patent/EP3811406B1/en active Active
- 2018-09-27 EP EP24164626.4A patent/EP4362624A3/en active Pending
- 2018-09-27 AU AU2018443831A patent/AU2018443831B2/en active Active
- 2018-11-06 TW TW107139242A patent/TW202013685A/zh unknown
- 2018-11-16 US US16/194,273 patent/US10714493B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TW202013685A (zh) | 2020-04-01 |
| CN113345912A (zh) | 2021-09-03 |
| EP3811406A4 (en) | 2022-02-23 |
| US20200105781A1 (en) | 2020-04-02 |
| BR112020025889A2 (pt) | 2021-04-06 |
| CN109417074A (zh) | 2019-03-01 |
| EP3811406B1 (en) | 2024-05-01 |
| AU2018443831A1 (en) | 2021-02-04 |
| JP2022502859A (ja) | 2022-01-11 |
| AU2018443831B2 (en) | 2022-03-10 |
| WO2020061868A1 (en) | 2020-04-02 |
| EP4362624A2 (en) | 2024-05-01 |
| EP3811406A1 (en) | 2021-04-28 |
| KR20210028247A (ko) | 2021-03-11 |
| EP4362624A3 (en) | 2024-10-16 |
| US10714493B2 (en) | 2020-07-14 |
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