SG10201903932WA - Method for producing bonded soi wafer - Google Patents
Method for producing bonded soi waferInfo
- Publication number
- SG10201903932WA SG10201903932WA SG10201903932WA SG10201903932WA SG10201903932WA SG 10201903932W A SG10201903932W A SG 10201903932WA SG 10201903932W A SG10201903932W A SG 10201903932WA SG 10201903932W A SG10201903932W A SG 10201903932WA SG 10201903932W A SG10201903932W A SG 10201903932WA
- Authority
- SG
- Singapore
- Prior art keywords
- soi wafer
- bonded soi
- film thickness
- producing
- layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 5
- 238000000034 method Methods 0.000 abstract 3
- 230000003647 oxidation Effects 0.000 abstract 3
- 238000007254 oxidation reaction Methods 0.000 abstract 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract 2
- 238000010438 heat treatment Methods 0.000 abstract 2
- 229910052786 argon Inorganic materials 0.000 abstract 1
- 230000032798 delamination Effects 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 239000002245 particle Substances 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015211730A JP6473970B2 (ja) | 2015-10-28 | 2015-10-28 | 貼り合わせsoiウェーハの製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201903932WA true SG10201903932WA (en) | 2019-05-30 |
Family
ID=58630023
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201802984RA SG11201802984RA (en) | 2015-10-28 | 2016-08-29 | Method for producing bonded soi wafer |
SG10201903932WA SG10201903932WA (en) | 2015-10-28 | 2016-08-29 | Method for producing bonded soi wafer |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201802984RA SG11201802984RA (en) | 2015-10-28 | 2016-08-29 | Method for producing bonded soi wafer |
Country Status (8)
Country | Link |
---|---|
US (1) | US10347525B2 (ko) |
EP (1) | EP3370249B1 (ko) |
JP (1) | JP6473970B2 (ko) |
KR (1) | KR102317552B1 (ko) |
CN (1) | CN108140553B (ko) |
SG (2) | SG11201802984RA (ko) |
TW (1) | TWI709999B (ko) |
WO (1) | WO2017072994A1 (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111146146B (zh) * | 2019-12-30 | 2022-09-06 | 长春理工大学 | 一种基底可多次利用的高效散热半导体衬底的制备方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0964321A (ja) | 1995-08-24 | 1997-03-07 | Komatsu Electron Metals Co Ltd | Soi基板の製造方法 |
JPH11204452A (ja) * | 1998-01-13 | 1999-07-30 | Mitsubishi Electric Corp | 半導体基板の処理方法および半導体基板 |
JP4228419B2 (ja) * | 1998-07-29 | 2009-02-25 | 信越半導体株式会社 | Soiウエーハの製造方法およびsoiウエーハ |
CN100454552C (zh) * | 2001-07-17 | 2009-01-21 | 信越半导体株式会社 | 贴合晶片的制造方法及贴合晶片、以及贴合soi晶片 |
CN101124657B (zh) | 2005-02-28 | 2010-04-14 | 信越半导体股份有限公司 | 贴合晶圆的制造方法及贴合晶圆 |
JP4398934B2 (ja) * | 2005-02-28 | 2010-01-13 | 信越半導体株式会社 | Soiウエーハの製造方法 |
JP2007317988A (ja) | 2006-05-29 | 2007-12-06 | Shin Etsu Handotai Co Ltd | 貼り合わせウエーハの製造方法 |
JP5245380B2 (ja) | 2007-06-21 | 2013-07-24 | 信越半導体株式会社 | Soiウェーハの製造方法 |
JP5135935B2 (ja) * | 2007-07-27 | 2013-02-06 | 信越半導体株式会社 | 貼り合わせウエーハの製造方法 |
JP5499428B2 (ja) * | 2007-09-07 | 2014-05-21 | 株式会社Sumco | 貼り合わせウェーハの製造方法 |
EP2075830A3 (en) * | 2007-10-11 | 2011-01-19 | Sumco Corporation | Method for producing bonded wafer |
JP5522175B2 (ja) | 2009-09-04 | 2014-06-18 | 信越半導体株式会社 | Soiウェーハの製造方法 |
JP5521561B2 (ja) * | 2010-01-12 | 2014-06-18 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
JP5541136B2 (ja) * | 2010-12-15 | 2014-07-09 | 信越半導体株式会社 | 貼り合わせsoiウエーハの製造方法 |
JP6056516B2 (ja) * | 2013-02-01 | 2017-01-11 | 信越半導体株式会社 | Soiウェーハの製造方法及びsoiウェーハ |
JP6380245B2 (ja) * | 2015-06-15 | 2018-08-29 | 信越半導体株式会社 | Soiウェーハの製造方法 |
JP6513041B2 (ja) * | 2016-02-19 | 2019-05-15 | 信越半導体株式会社 | 半導体ウェーハの熱処理方法 |
-
2015
- 2015-10-28 JP JP2015211730A patent/JP6473970B2/ja active Active
-
2016
- 2016-08-29 SG SG11201802984RA patent/SG11201802984RA/en unknown
- 2016-08-29 KR KR1020187011656A patent/KR102317552B1/ko active IP Right Grant
- 2016-08-29 SG SG10201903932WA patent/SG10201903932WA/en unknown
- 2016-08-29 US US15/767,174 patent/US10347525B2/en active Active
- 2016-08-29 CN CN201680059158.3A patent/CN108140553B/zh active Active
- 2016-08-29 WO PCT/JP2016/003916 patent/WO2017072994A1/ja active Application Filing
- 2016-08-29 EP EP16859235.0A patent/EP3370249B1/en active Active
- 2016-09-01 TW TW105128176A patent/TWI709999B/zh active
Also Published As
Publication number | Publication date |
---|---|
US20190074213A1 (en) | 2019-03-07 |
KR20180073580A (ko) | 2018-07-02 |
WO2017072994A1 (ja) | 2017-05-04 |
CN108140553A (zh) | 2018-06-08 |
TW201724176A (zh) | 2017-07-01 |
US10347525B2 (en) | 2019-07-09 |
EP3370249A1 (en) | 2018-09-05 |
EP3370249B1 (en) | 2020-03-11 |
TWI709999B (zh) | 2020-11-11 |
JP6473970B2 (ja) | 2019-02-27 |
EP3370249A4 (en) | 2019-06-26 |
CN108140553B (zh) | 2022-04-08 |
KR102317552B1 (ko) | 2021-10-27 |
JP2017084963A (ja) | 2017-05-18 |
SG11201802984RA (en) | 2018-05-30 |
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