SG10201807525XA - Storage device and data training method thereof - Google Patents
Storage device and data training method thereofInfo
- Publication number
- SG10201807525XA SG10201807525XA SG10201807525XA SG10201807525XA SG10201807525XA SG 10201807525X A SG10201807525X A SG 10201807525XA SG 10201807525X A SG10201807525X A SG 10201807525XA SG 10201807525X A SG10201807525X A SG 10201807525XA SG 10201807525X A SG10201807525X A SG 10201807525XA
- Authority
- SG
- Singapore
- Prior art keywords
- data
- signal
- window
- data signal
- storage device
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Memory System (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020170115338A KR102273191B1 (ko) | 2017-09-08 | 2017-09-08 | 스토리지 장치 및 그것의 데이터 트레이닝 방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201807525XA true SG10201807525XA (en) | 2019-04-29 |
Family
ID=65441472
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201807525XA SG10201807525XA (en) | 2017-09-08 | 2018-09-03 | Storage device and data training method thereof |
Country Status (5)
Country | Link |
---|---|
US (1) | US10325633B2 (zh) |
KR (1) | KR102273191B1 (zh) |
CN (1) | CN109471591B (zh) |
DE (1) | DE102018116545A1 (zh) |
SG (1) | SG10201807525XA (zh) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
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CN108646984B (zh) * | 2018-05-16 | 2020-01-03 | 华为技术有限公司 | 一种dqs位置调整方法和装置 |
KR102693546B1 (ko) | 2018-11-07 | 2024-08-08 | 삼성전자주식회사 | 스토리지 장치 |
CN109903803B (zh) * | 2019-03-26 | 2021-04-27 | 晶晨半导体(上海)股份有限公司 | 存储模块的测试方法及系统 |
KR20210026353A (ko) | 2019-08-30 | 2021-03-10 | 삼성전자주식회사 | 메모리 장치 트레이닝 방법 및 이를 포함한 전자 기기 및 전자 시스템 |
JP7332406B2 (ja) | 2019-09-13 | 2023-08-23 | キオクシア株式会社 | メモリシステム |
KR20210033719A (ko) * | 2019-09-19 | 2021-03-29 | 에스케이하이닉스 주식회사 | 메모리 장치 및 그 동작 방법 |
DE102020124101A1 (de) | 2020-02-04 | 2021-08-05 | Samsung Electronics Co., Ltd. | Elektronische vorrichtung mit einer speichervorrichtung und trainingsverfahren |
KR20210099675A (ko) * | 2020-02-04 | 2021-08-13 | 삼성전자주식회사 | 메모리 장치를 포함하는 전자 장치 및 그것의 트레이닝 방법 |
CN111506527B (zh) * | 2020-04-13 | 2022-03-18 | 飞腾信息技术有限公司 | 数字高速并行总线自适应区间校正方法、装置及存储介质 |
US11593158B2 (en) | 2020-06-09 | 2023-02-28 | Kingston Digital Inc. | Universal peripheral extender for communicatively connecting peripheral I/O devices and smart host devices |
US11127438B1 (en) * | 2020-06-17 | 2021-09-21 | Western Digital Technologies, Inc. | Background interface training using secondary senses |
CN113568848B (zh) * | 2020-07-29 | 2023-07-11 | 华为技术有限公司 | 处理器、信号调整方法及计算机系统 |
US11393513B2 (en) * | 2020-12-01 | 2022-07-19 | Micron Technology, Inc. | Timing of read and write operations to reduce interference, and related devices, systems, and methods |
KR20220085237A (ko) * | 2020-12-15 | 2022-06-22 | 삼성전자주식회사 | 스토리지 컨트롤러, 스토리지 장치 및 스토리지 장치의 동작 방법 |
CN115344215A (zh) * | 2022-08-29 | 2022-11-15 | 深圳市紫光同创电子有限公司 | 存储器训练方法及系统 |
CN116580743B (zh) * | 2023-04-26 | 2024-01-23 | 珠海妙存科技有限公司 | 一种内存读采样电路及其延时调节方法及读采样装置 |
CN118245407B (zh) * | 2024-05-28 | 2024-08-02 | 广东匠芯创科技有限公司 | Psram控制器及其硬件采样训练方法、设备、介质 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
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KR200177248Y1 (ko) * | 1994-09-03 | 2000-04-15 | 김영환 | 반도체 메모리의 어드레스 천이 검출회로 |
US7443741B2 (en) | 2005-07-07 | 2008-10-28 | Lsi Corporation | DQS strobe centering (data eye training) method |
US7498882B2 (en) | 2006-04-18 | 2009-03-03 | Rambus Inc. | Signaling system with low-power automatic gain control |
KR100832021B1 (ko) | 2006-06-29 | 2008-05-26 | 주식회사 하이닉스반도체 | 반도체 메모리 소자 및 그 구동방법 |
US20090168563A1 (en) | 2007-12-31 | 2009-07-02 | Yueming Jiang | Apparatus, system, and method for bitwise deskewing |
US7924637B2 (en) * | 2008-03-31 | 2011-04-12 | Advanced Micro Devices, Inc. | Method for training dynamic random access memory (DRAM) controller timing delays |
KR101169210B1 (ko) * | 2009-02-13 | 2012-07-27 | 주식회사 실리콘웍스 | 지연고정루프 기반의 클럭 복원부가 구비된 수신부 장치 |
US8037375B2 (en) | 2009-06-30 | 2011-10-11 | Intel Corporation | Fast data eye retraining for a memory |
US8578086B2 (en) | 2009-09-25 | 2013-11-05 | Intel Corporation | Memory link initialization |
US8918686B2 (en) | 2010-08-18 | 2014-12-23 | Kingtiger Technology (Canada) Inc. | Determining data valid windows in a system and method for testing an integrated circuit device |
KR101780440B1 (ko) * | 2010-08-30 | 2017-09-22 | 삼성전자 주식회사 | 멀티 터치에 따른 리스트 데이터 출력 제어 방법 및 이를 지원하는 휴대 단말기 |
KR101791456B1 (ko) | 2010-10-11 | 2017-11-21 | 삼성전자주식회사 | 라이트 트레이닝 방법 및 이를 수행하는 반도체 장치 |
KR101780422B1 (ko) * | 2010-11-15 | 2017-09-22 | 삼성전자주식회사 | 불휘발성 메모리 장치, 그것의 읽기 방법, 그리고 그것을 포함하는 메모리 시스템 |
US8760946B2 (en) | 2012-05-22 | 2014-06-24 | Advanced Micro Devices | Method and apparatus for memory access delay training |
CN103927131B (zh) | 2014-03-25 | 2017-02-15 | 四川和芯微电子股份有限公司 | 同步闪存u盘的启动方法及其控制系统 |
US9147463B1 (en) | 2014-03-25 | 2015-09-29 | Megachips Corporation | Method and apparatus for data capture in DDR memory interface |
US9639495B2 (en) * | 2014-06-27 | 2017-05-02 | Advanced Micro Devices, Inc. | Integrated controller for training memory physical layer interface |
US9558850B1 (en) | 2015-12-01 | 2017-01-31 | International Business Machines Corporation | Efficient calibration of a data eye for memory devices |
KR20170115338A (ko) | 2016-04-07 | 2017-10-17 | 삼성전자주식회사 | 보안 예보 시스템 및 방법 |
-
2017
- 2017-09-08 KR KR1020170115338A patent/KR102273191B1/ko active IP Right Grant
-
2018
- 2018-04-25 US US15/962,206 patent/US10325633B2/en active Active
- 2018-07-09 DE DE102018116545.5A patent/DE102018116545A1/de active Pending
- 2018-08-13 CN CN201810916178.9A patent/CN109471591B/zh active Active
- 2018-09-03 SG SG10201807525XA patent/SG10201807525XA/en unknown
Also Published As
Publication number | Publication date |
---|---|
DE102018116545A1 (de) | 2019-03-14 |
US20190080730A1 (en) | 2019-03-14 |
KR102273191B1 (ko) | 2021-07-06 |
KR20190028605A (ko) | 2019-03-19 |
CN109471591A (zh) | 2019-03-15 |
US10325633B2 (en) | 2019-06-18 |
CN109471591B (zh) | 2023-04-07 |
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