SE9602407D0 - A method for producing a channel region layer in a voltage controlled semiconductor device - Google Patents

A method for producing a channel region layer in a voltage controlled semiconductor device

Info

Publication number
SE9602407D0
SE9602407D0 SE9602407A SE9602407A SE9602407D0 SE 9602407 D0 SE9602407 D0 SE 9602407D0 SE 9602407 A SE9602407 A SE 9602407A SE 9602407 A SE9602407 A SE 9602407A SE 9602407 D0 SE9602407 D0 SE 9602407D0
Authority
SE
Sweden
Prior art keywords
layer
channel region
producing
semiconductor device
controlled semiconductor
Prior art date
Application number
SE9602407A
Other languages
English (en)
Swedish (sv)
Inventor
Christopher Harris
Mietek Bakowski
Lennart Zdansky
Bo Bijlenga
Original Assignee
Abb Research Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Abb Research Ltd filed Critical Abb Research Ltd
Priority to SE9602407A priority Critical patent/SE9602407D0/xx
Publication of SE9602407D0 publication Critical patent/SE9602407D0/xx
Priority to US08/678,548 priority patent/US5786251A/en
Priority to JP10502817A priority patent/JP2000512808A/ja
Priority to PCT/SE1997/001088 priority patent/WO1997049124A1/fr
Priority to EP97928614A priority patent/EP0958601A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/931—Silicon carbide semiconductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)
SE9602407A 1996-06-19 1996-06-19 A method for producing a channel region layer in a voltage controlled semiconductor device SE9602407D0 (sv)

Priority Applications (5)

Application Number Priority Date Filing Date Title
SE9602407A SE9602407D0 (sv) 1996-06-19 1996-06-19 A method for producing a channel region layer in a voltage controlled semiconductor device
US08/678,548 US5786251A (en) 1996-06-19 1996-07-09 Method for producing a channel region layer in a voltage controlled semiconductor device
JP10502817A JP2000512808A (ja) 1996-06-19 1997-06-18 電圧制御型半導体装置にチャンネル領域層を作るための方法
PCT/SE1997/001088 WO1997049124A1 (fr) 1996-06-19 1997-06-18 Procede de production d'une couche d'une region canal dans un dispositif a semi-conducteur commande par tension
EP97928614A EP0958601A1 (fr) 1996-06-19 1997-06-18 Procede de production d'une couche d'une region canal dans un dispositif a semi-conducteur commande par tension

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9602407A SE9602407D0 (sv) 1996-06-19 1996-06-19 A method for producing a channel region layer in a voltage controlled semiconductor device
US08/678,548 US5786251A (en) 1996-06-19 1996-07-09 Method for producing a channel region layer in a voltage controlled semiconductor device

Publications (1)

Publication Number Publication Date
SE9602407D0 true SE9602407D0 (sv) 1996-06-19

Family

ID=26662680

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9602407A SE9602407D0 (sv) 1996-06-19 1996-06-19 A method for producing a channel region layer in a voltage controlled semiconductor device

Country Status (3)

Country Link
US (1) US5786251A (fr)
SE (1) SE9602407D0 (fr)
WO (1) WO1997049124A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8133789B1 (en) * 2003-04-11 2012-03-13 Purdue Research Foundation Short-channel silicon carbide power mosfet
JP4786621B2 (ja) * 2007-09-20 2011-10-05 株式会社東芝 半導体装置およびその製造方法
US8035112B1 (en) 2008-04-23 2011-10-11 Purdue Research Foundation SIC power DMOSFET with self-aligned source contact
US8993424B2 (en) * 2011-11-03 2015-03-31 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a semiconductor transistor device with optimized dopant profile
US9660049B2 (en) 2011-11-03 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor transistor device with dopant profile
JP5597217B2 (ja) * 2012-02-29 2014-10-01 株式会社東芝 半導体装置及びその製造方法
US8933528B2 (en) * 2013-03-11 2015-01-13 International Business Machines Corporation Semiconductor fin isolation by a well trapping fin portion
US11222782B2 (en) * 2020-01-17 2022-01-11 Microchip Technology Inc. Self-aligned implants for silicon carbide (SiC) technologies and fabrication method

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188974A (ja) * 1983-04-11 1984-10-26 Nec Corp 半導体装置の製造方法
JP2615390B2 (ja) * 1985-10-07 1997-05-28 工業技術院長 炭化シリコン電界効果トランジスタの製造方法
JP2913785B2 (ja) * 1990-07-12 1999-06-28 富士通株式会社 半導体装置の製造方法
US5233215A (en) * 1992-06-08 1993-08-03 North Carolina State University At Raleigh Silicon carbide power MOSFET with floating field ring and floating field plate
JP3146694B2 (ja) * 1992-11-12 2001-03-19 富士電機株式会社 炭化けい素ｍｏｓｆｅｔおよび炭化けい素ｍｏｓｆｅｔの製造方法
JPH0799312A (ja) * 1993-02-22 1995-04-11 Texas Instr Inc <Ti> 半導体装置とその製法
US5510281A (en) * 1995-03-20 1996-04-23 General Electric Company Method of fabricating a self-aligned DMOS transistor device using SiC and spacers

Also Published As

Publication number Publication date
US5786251A (en) 1998-07-28
WO1997049124A1 (fr) 1997-12-24

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