EP0958601A1 - Procede de production d'une couche d'une region canal dans un dispositif a semi-conducteur commande par tension - Google Patents

Procede de production d'une couche d'une region canal dans un dispositif a semi-conducteur commande par tension

Info

Publication number
EP0958601A1
EP0958601A1 EP97928614A EP97928614A EP0958601A1 EP 0958601 A1 EP0958601 A1 EP 0958601A1 EP 97928614 A EP97928614 A EP 97928614A EP 97928614 A EP97928614 A EP 97928614A EP 0958601 A1 EP0958601 A1 EP 0958601A1
Authority
EP
European Patent Office
Prior art keywords
layer
sic
type
channel region
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97928614A
Other languages
German (de)
English (en)
Inventor
Christopher Harris
Mietek Bakowski
Lennart Zdansky
Bo Bijlenga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ABB Research Ltd Switzerland
ABB Research Ltd Sweden
Original Assignee
ABB Research Ltd Switzerland
ABB Research Ltd Sweden
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SE9602407A external-priority patent/SE9602407D0/xx
Application filed by ABB Research Ltd Switzerland, ABB Research Ltd Sweden filed Critical ABB Research Ltd Switzerland
Publication of EP0958601A1 publication Critical patent/EP0958601A1/fr
Withdrawn legal-status Critical Current

Links

Definitions

  • step 10) a step carried out after step 2) but before step 5), and in which dopants of p-type are implanted deeply into the area defined by the aperture existing in said silicon layer for creating a deep p-type base layer under the layer of n-type created in step 4), and forming a source region layer of the device, 11) removing the remaining silicon layer by etching,
  • Fig 5 is a view illustrating how the steps shown in Figs 1 and 2 may be carried out in a method according to a second preferred embodiment of the invention.
  • This device is created by epitaxially growing a low doped n-type drift layer 2 on top of a highly doped n-type substrate layer 10, which is adapted to be connected to a drain indicated by a line 11 of the device.
  • a highly doped p-type base layer 6, a n-type highly doped source region layer 5 and a p-type channel region layer 9 are formed by using the inventional method for producing a channel region layer in a SiC-layer for producing a voltage controlled semiconduc ⁇ tor device.
  • the device also includes a source contact 12 arranged in a groove 13 etched into the source region layer 5 through the base layer 6.
  • a gate electrode 15 is ap ⁇ plied upon said insulating layer 14 at least over the channel region layer 9.
  • the function of such a device is well known to those skilled in the art, but it may be summarized here.
  • a voltage is applied to the gate electrode 15 a lateral conducting inversion channel will be created at the interface 16 between the channel region layer 9 and the insulating layer 14 between the source region layer 5 and the drift layer 2, so that, provided that a voltage is applied over the source 12 and the drain 11 in the forward direction of the device an electron current will flow from the source to the drain.
  • the number of layers mentioned in the claims is a minimum number, and it is within the scope of the invention to arrange further layers in the device or dividing any layer into several layers by selective doping of different regions thereof.
  • the layers located on top of each other does not have to be epitaxially grown in the order they are mentioned in the claims, but any other order of growth of these layers is within the scope of the claims.
  • the method may be started from the drift layer and the so called substrate layer and the drain may be grown at the very end of the method.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Dans un procédé de production d'une couche de région canal dans une couche SiC en vue de produire un dispositif à semi-conducteur commandé par tension, une couche (1) de silicium soit a) polycristallin soit b) amorphe est appliquée sur la couche SiC, une ouverture (4) est attaquée dans ladite couche de silicium s'étendant vers la couche SiC, une couche superficielle d'une certaine épaisseur de ladite couche de silicium est oxydée, et l'extension latérale de ladite couche de région canal est déterminée en éliminant ladite couche oxydée; on effectue ensuite une implantation dans la zone exposée par ladite ouverture élargie ainsi formée.
EP97928614A 1996-06-19 1997-06-18 Procede de production d'une couche d'une region canal dans un dispositif a semi-conducteur commande par tension Withdrawn EP0958601A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9602407A SE9602407D0 (sv) 1996-06-19 1996-06-19 A method for producing a channel region layer in a voltage controlled semiconductor device
SE9602407 1996-06-19
PCT/SE1997/001088 WO1997049124A1 (fr) 1996-06-19 1997-06-18 Procede de production d'une couche d'une region canal dans un dispositif a semi-conducteur commande par tension

Publications (1)

Publication Number Publication Date
EP0958601A1 true EP0958601A1 (fr) 1999-11-24

Family

ID=20403059

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97928614A Withdrawn EP0958601A1 (fr) 1996-06-19 1997-06-18 Procede de production d'une couche d'une region canal dans un dispositif a semi-conducteur commande par tension

Country Status (2)

Country Link
EP (1) EP0958601A1 (fr)
JP (1) JP2000512808A (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3935042B2 (ja) * 2002-04-26 2007-06-20 株式会社東芝 絶縁ゲート型半導体装置
US7074643B2 (en) * 2003-04-24 2006-07-11 Cree, Inc. Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9749124A1 *

Also Published As

Publication number Publication date
JP2000512808A (ja) 2000-09-26

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