SE9202182D0 - Mirrored memory multi processor system - Google Patents

Mirrored memory multi processor system

Info

Publication number
SE9202182D0
SE9202182D0 SE9202182A SE9202182A SE9202182D0 SE 9202182 D0 SE9202182 D0 SE 9202182D0 SE 9202182 A SE9202182 A SE 9202182A SE 9202182 A SE9202182 A SE 9202182A SE 9202182 D0 SE9202182 D0 SE 9202182D0
Authority
SE
Sweden
Prior art keywords
ram
processor
mirrored memory
processors
mirrored
Prior art date
Application number
SE9202182A
Other languages
English (en)
Swedish (sv)
Inventor
R W Heugel
Original Assignee
Tandem Telecomm Syst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tandem Telecomm Syst filed Critical Tandem Telecomm Syst
Publication of SE9202182D0 publication Critical patent/SE9202182D0/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2053—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant
    • G06F11/2056—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant by mirroring
    • G06F11/2087—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant by mirroring with a common controller
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols
SE9202182A 1991-07-18 1992-07-16 Mirrored memory multi processor system SE9202182D0 (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US73204091A 1991-07-18 1991-07-18

Publications (1)

Publication Number Publication Date
SE9202182D0 true SE9202182D0 (sv) 1992-07-16

Family

ID=24941949

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9202182A SE9202182D0 (sv) 1991-07-18 1992-07-16 Mirrored memory multi processor system

Country Status (6)

Country Link
US (1) US5495570A (xx)
EP (1) EP0528538B1 (xx)
JP (1) JPH05242060A (xx)
DE (1) DE69227956T2 (xx)
FI (1) FI923273A (xx)
SE (1) SE9202182D0 (xx)

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US5897656A (en) * 1996-09-16 1999-04-27 Corollary, Inc. System and method for maintaining memory coherency in a computer system having multiple system buses
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US6341328B1 (en) * 1999-04-20 2002-01-22 Lucent Technologies, Inc. Method and apparatus for using multiple co-dependent DMA controllers to provide a single set of read and write commands
US6981176B2 (en) * 1999-05-10 2005-12-27 Delphi Technologies, Inc. Secured microcontroller architecture
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US6802023B2 (en) 2001-03-15 2004-10-05 Hewlett-Packard Development Company, L.P. Redundant controller data storage system having hot insertion system and method
US6708285B2 (en) 2001-03-15 2004-03-16 Hewlett-Packard Development Company, L.P. Redundant controller data storage system having system and method for handling controller resets
US6773083B2 (en) 2001-08-29 2004-08-10 Lexmark International, Inc. Method and apparatus for non-volatile memory usage in an ink jet printer
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US7275181B2 (en) * 2003-03-26 2007-09-25 International Business Machines Corporation Autonomic embedded computing “dynamic storage subsystem morphing”
US7330930B1 (en) * 2004-03-09 2008-02-12 Adaptec, Inc. Method and apparatus for balanced disk access load distribution
US7384146B2 (en) * 2005-06-28 2008-06-10 Carestream Health, Inc. Health care kiosk having automated diagnostic eye examination and a fulfillment remedy based thereon
US7849369B2 (en) * 2005-10-25 2010-12-07 Waratek Pty Ltd. Failure resistant multiple computer system and method
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US20080140633A1 (en) * 2006-10-05 2008-06-12 Holt John M Synchronization with partial memory replication
US20080133692A1 (en) * 2006-10-05 2008-06-05 Holt John M Multiple computer system with redundancy architecture
US20080155127A1 (en) * 2006-10-05 2008-06-26 Holt John M Multi-path switching networks
US20080133688A1 (en) * 2006-10-05 2008-06-05 Holt John M Multiple computer system with dual mode redundancy architecture
US20080133869A1 (en) * 2006-10-05 2008-06-05 Holt John M Redundant multiple computer architecture
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US9152511B2 (en) * 2008-06-20 2015-10-06 Freescale Semiconductor, Inc. System for dynamically distributing an available memory resource to redundant and non-redundant storage areas using RAM routing logic
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US7870365B1 (en) 2008-07-07 2011-01-11 Ovics Matrix of processors with data stream instruction execution pipeline coupled to data switch linking to neighbor units by non-contentious command channel / data channel
US7958341B1 (en) 2008-07-07 2011-06-07 Ovics Processing stream instruction in IC of mesh connected matrix of processors containing pipeline coupled switch transferring messages over consecutive cycles from one link to another link or memory
US8145880B1 (en) 2008-07-07 2012-03-27 Ovics Matrix processor data switch routing systems and methods
US8131975B1 (en) 2008-07-07 2012-03-06 Ovics Matrix processor initialization systems and methods
US8327114B1 (en) 2008-07-07 2012-12-04 Ovics Matrix processor proxy systems and methods
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FR3078439A1 (fr) * 2018-02-27 2019-08-30 Stmicroelectronics (Rousset) Sas Procede de gestion du routage de transactions entre des equipements sources, au moins un equipement cible, par exemple une memoire multiports, et systeme sur puce correspondant
CN108829631A (zh) * 2018-04-27 2018-11-16 江苏华存电子科技有限公司 一种提升多核处理器的信息管理方法

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Also Published As

Publication number Publication date
EP0528538A2 (en) 1993-02-24
DE69227956T2 (de) 1999-06-10
FI923273A (fi) 1993-01-19
FI923273A0 (fi) 1992-07-17
JPH05242060A (ja) 1993-09-21
EP0528538B1 (en) 1998-12-23
DE69227956D1 (de) 1999-02-04
EP0528538A3 (en) 1994-05-18
US5495570A (en) 1996-02-27

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